基于fpga的点阵显示控制器的设计 (1)
基于FPGA的8*8点阵显示器的设计
摘要：主要研究基于VHDL语言的8*8点阵显示汉字。首先对单个模块进行设计仿真调试，然后对整体模块的设计，通过编程、调试、仿真实现汉字的行扫描，其硬件系统下载正确的实现也获得了与软件仿真相吻合的结果。
关键字：扫描分频点阵显示
一．课题要求
1.技术要求
（1）EDA技术：EDA（Electronic Design Automation)技术就是依赖功能强大的计算机，在EDA工具软件平台上，对以硬件描述语言HDL（Hardware Description Language)为系统描述手段完成的设计文件，自动的完成逻辑编译、化简、分割、综合、布局布线以及逻辑优化和仿真测试，直至实现既定的电子线路系统功能。
（2）VHDL语言：VHDL(Very--High--Speed Integrated Circuit Hardware Description Language主要用于描述数字系统的结构，行为，功能和接口，除了含有许多硬件特征得语句外，VHDL的语言形式和描述风格与句法是十分类似于一般的计算机高级语言。
（3）层次化设计：EDA设计一般采用自顶向下、由粗到细、逐步求精的方法。设计最顶层是指系统的整体要求，最下层是指具体的逻辑电路实现。自定向下是将数字系统的整体逐步分解为各个子系统和模块，若子系统规模较大则进一步分解为更小的子系统和模块，层层分解，直至整个系统中各子模块关系合理、便于实现为止。
2.功能要求
本次综合型数字电路课程设计组要完成点阵显示控制器的三种功能，分别是按键控制静态显示下一个字、汉字滚动和逐列显示（即先显示两边的各一列然后向外依次显示直至显示整个汉字，之后先显示中间的两行然后向外显示直至显示整个汉字），本次课程设计的所采用的软件是Quarters??6.0，硬件是EP2C5T144C8，通过对于8*8点阵显示相应的汉字，分别通过行和列控制显示。
二．设计方案
本次课程设计采用的是的行共阳列共阴的8*8点阵，因此不可能在同一时刻显示出整个汉字，为了显示出整个汉字，首先制作一个基本矩阵，然后按照时间的顺序进行逐行扫描，首先行给'"00000001",同时列给相应的码值，第一行的的发光二极管就会有相应的亮，然后行给"00000010"，同时列给相应的码值，第二行的的发光二极管就会有相应的亮，用并行操作方式，如此周而复始的重复下去，根据人眼的视觉残留特性，使之形成整个汉字的显示。本次试验采用行扫描。
图一.硬件总体框图
三．单元模块设计仿真结果及分析
1.选择输出模式
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(en:in std_logic;
key:in std_logic_vector(1 downto 0);
Q0,Q1,Q2:in std_logic_vector(7 downto 0);
Y:out std_logic_vector(7 downto 0));
end;
architecture ex1 of control is
begin
process(en,key)
begin
if en='0' then y<="11111111";
else
case key is
when"00"=>y<=Q0;
when"01"=>y<=Q1;
when"10"=>y<=q2;
when others=>y<="11111111";
end case;
end if;
end process;
end ex1;
利用对输入按键的码值来控制显示：
EN Key1 Key0 Y
0 X X "11111111"
1 0 0 Q0
1 0 1 Q1
1 1 0 Q2
1 1 1 "11111111"
仿真波形：
通过仿真波形可以知道只有在EN=‘0’和开关都为高电平的情况下无显示，即输出都为高电平，其余情况下都会输出对应的码值。
2.滚动显示
滚动部分是将50MHZ时钟分为两个不同的频率，一个较快的时钟用来控制扫描的速度显示相应的汉字，一次从上向下逐行扫描，用一个较慢的时钟，当来了一个脉冲hang依次加1，就会有不同的码值输送给列，就会有汉字向上移一行。由于是行扫描在一定的时间里，即高频扫描每种输出的码值，使视觉上就可以实现向上滚动显示汉字的效果。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gundong is
port(clk:in std_logic;
com:out std_logic_vector(7 downto 0);
red:out std_logic_vector(7 downto 0));
end;
architecture ex2 of gundong is
signal st1:std_logic_vector(7 downto 0);
signal osc,osd:std_logic;
signal d_ff:std_logic_vector(25 downto 0);
signal data,d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(7 downto 0);
signal hang:std_logic_vector(6 downto 0);
begin
com<=st1; red<=data;
d0<="11000001"when hang="0000000"else--周字第1行 "11010101"when hang="0000001"else
"11000001"when hang="0000010"else
"11000001"when hang="0000011"else
"11000001"when hang="0000100"else
"11000001"when hang="0000101"else
"10111001"when hang="0000110"else
"01111101"when hang="0000111"else
"11111111"when hang="0001000"else
"11101011"when hang="0001001" else
"11001110"when hang="0001010"else
"10010001"when hang="0001011"else
"00000011"when hang="0001100"else
"10001011"when hang="0001101"else
"01011011"when hang="0001110"else
"11010101"when hang="0001111"else
"11001110"when hang="0010000"else
"11111111"when hang="0010001"else
"11111111";
d1<="11010101"when hang="0000000"else
"11000001"when hang="0000001"else
"11000001"when hang="0000010"else
"11000001"when hang="0000011"else
"11000001"when hang="0000100"else
"10111001"when hang="0000101"else
"01111101"when hang="0000110"else
"11111111"when hang="0000111"else
"11101011"when hang="0001000"else
"11001110"when hang="0001001"else
"10010001"when hang="0001010"else
"00000011"when hang="0001011"else
"10001011"when hang="0001100"else
"01011011"when hang="0001101"else
"11010101"when hang="0001110"else
"11001110"when hang="0001111"else
"11000001"when hang="0010001"else--周字第1行 "11111111";
d2<= "11000001"when hang="0000000"else
"11000001"when hang="0000001"else
"11000001"when hang="0000010"else
"11000001"when hang="0000011"else
"10111001"when hang="0000100"else
"01111101"when hang="0000101"else
"11111111"when hang="0000110"else
"11101011"when hang="0000111"else
"11001110"when hang="0001000"else
"10010001"when hang="0001001"else
"00000011"when hang="0001010"else
"10001011"when hang="0001011"else
"01011011"when hang="0001100"else
"11010101"when hang="0001101"else
"11001110"when hang="0001110"else
"11111111"when hang="0001111"else "11000001"when hang="0010000"else--周字第1行 "11010101"when hang="0010001"else
"11111111";
d3<="11000001"when hang="0000000"else
"11000001"when hang="0000001"else
"11000001"when hang="0000010"else
"10111001"when hang="0000011"else
"01111101"when hang="0000100"else
"11111111"when hang="0000101"else
"11101011"when hang="0000110"else
"11001110"when hang="0000111"else
"10010001"when hang="0001000"else
"00000011"when hang="0001001"else
"10001011"when hang="0001010"else
"01011011"when hang="0001011"else
"11010101"when hang="0001100"else
"11001110"when hang="0001101"else
"11111111"when hang="0001110"else "11000001"when hang="0001111"else--周字第1行
"11000001"when hang="0010001"else
"11111111";
d4<="11000001"when hang="0000000"else
"11000001"when hang="0000001"else
"10111001"when hang="0000010"else
"01111101"when hang="0000011"else
"11111111"when hang="0000100"else
"11101011"when hang="0000101"else
"11001110"when hang="0000110"else
"10010001"when hang="0000111"else
"00000011"when hang="0001000"else
"10001011"when hang="0001001"else
"01011011"when hang="0001010"else
"11010101"when hang="0001011"else
"11001110"when hang="0001100"else
"11111111"when hang="0001101"else
"11000001"when hang="0001110"else--周字第1行 "11010101"when hang="0001111"else
"11000001"when hang="0010000"else
"11000001"when hang="0010001"else
"11111111";
d5<= "11000001"when hang="0000000"else
"10111001"when hang="0000001"else
"01111101"when hang="0000010"else
"11111111"when hang="0000011"else
"11101011"when hang="0000100"else
"11001110"when hang="0000101"else
"10010001"when hang="0000110"else
"00000011"when hang="0000111"else
"10001011"when hang="0001000"else
"01011011"when hang="0001001"else
"11010101"when hang="0001010"else
"11001110"when hang="0001011"else
"11111111"when hang="0001100"else
"11000001"when hang="0001101"else--周字第1行 "11010101"when hang="0001110"else
"11000001"when hang="0001111"else
"11000001"when hang="0010001"else
"11111111";
d6<="10111001"when hang="0000000"else
"01111101"when hang="0000001"else
"11111111"when hang="0000010"else
"11101011"when hang="0000011"else
"11001110"when hang="0000100"else
"10010001"when hang="0000101"else
"00000011"when hang="0000110"else
"10001011"when hang="0000111"else
"01011011"when hang="0001000"else
"11010101"when hang="0001001"else
"11001110"when hang="0001010"else
"11111111"when hang="0001011"else
"11000001"when hang="0001100"else--周字第1行 "11010101"when hang="0001101"else
"11000001"when hang="0001110"else
"11000001"when hang="0001111"else
"11000001"when hang="0010000"else
"11000001"when hang="0010001"else
"11111111";
d7<= "01111101"when hang="0000000"else
"11111111"when hang="0000001"else
"11101011"when hang="0000010"else
"11001110"when hang="0000011"else
"10010001"when hang="0000100"else
"00000011"when hang="0000101"else
"10001011"when hang="0000110"else
"01011011"when hang="0000111"else
"11010101"when hang="0001000"else
"11001110"when hang="0001001"else
"11111111"when hang="0001010"else
"11000001"when hang="0001011"else--周字第1行 "11010101"when hang="0001100"else
"11000001"when hang="0001101"else
"11000001"when hang="0001110"else
"11000001"when hang="0001111"else
"10111001"when hang="0010001"else
"11111111";
first:process(clk)
begin
if clk'event and clk='1'then
if d_ff>=2e8 then d_ff<=(others=>'0');
else d_ff<=d_ff+1;
end if;
end if;
osc<=not d_ff(8);
osd<=not d_ff(24);
end process first;
second:process(osc)
begin
if osc'event and osc='1' then
if st1="00000000" or st1="10000000" then
st1<="00000001";data<=d0;
elsif st1="00000001"then
st1<="00000010";data<=d1;
elsif st1="00000010" then
st1<="00000100";data<=d2;
elsif st1="00000100" then
st1<="00001000";data<=d3;
elsif st1="00001000"then
st1<="00010000";data<=d4;
elsif st1="00010000"then
st1<="00100000"; data<=d5;
elsif st1="00100000" then
st1<="01000000";data<=d6;
elsif st1="01000000" then
st1<="10000000";data<=d7;
end if;
end if;
end process;
third:process(osd)
begin
if osd'event and osd='1'then