阿5307调试笔记

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TFDU5307-TR1中文资料

Document Number Fast Low Profile (2.5 mm) Infrared Transceiver Module (MIR, 1.152 Mbit/s) for IrDA ® ApplicationsDescriptionThe TFDU5307 is an infrared transceiver module compliant to the latest IrDA physical layer standard,supporting IrDA speeds up to 1.152 Mbit/s (MIR) and carrier based remote control modes up to 2 MHz. Inte-grated within the transceiver module are a PIN photo-diode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a sin-gle package.This Vishay MIR transceiver is built in a low profile package using the experiences of the lead frame babyface technology. The transceivers are capable of directly interfacing with a wide variety of I/O devices,which perform the modulation/ demodulation function.At a minimum, a V CC bypass capacitor and a serialresistor for current control are the only external com-ponents required implementing a complete solution.TFDU5307 has a tri-state output and is floating in shutdown mode with a weak pull-up.Features•Compliant to the latest IrDA physical layer specification (up to 1.152 Mbit/s) and TV Remote Control, bi-directionaloperation included.•Sensitivity covers full IrDA range.Recommended operating range is from nose to nose to 70 cm •Operates from2.7 V to 5.5 V within specification•Low power consumption (typ. 0.55 mA Supply current in receive mode, no signal)•Power shutdown mode (< 5 µA Shutdown Current in Full Temperature Range, up to 85°C) •Surface mount package, low profileuniversal (L 8.5 mm x W 2.9 mm x H 2.5 mm)Capable of surface mount soldering to Side and top view orientation•Backward pin compatible to Vishay Semiconductors SIR and MIR infrared transceivers•High efficiency emitter•Directly interfaces with various super I/O and con-troller devices•Tri-state-receiver output, floating in shut down with a weak pull-up•Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US Patent No.6,157,476 •Logic voltage 1.5 V to 5.5 V is independent of IRED driver and analog supply voltage •Only one external component required •TV remote control supported•Transmitter intensity can be adjusted by anexternal resistor for extended range (> 0.7 m) or minimum lowpower (> 0.2 m) IrDA compliance. •Lead (Pb)-free device•Device in accordance to RoHS 2002/95/EC and WEEE 2002/96ECApplications•Telecommunication products (cellular phones, pagers)•Digital still and video cameras•Printers, fax machines, photocopiers, screen pro-jectors•Low power consumption (typ. 0.55 mA Supply current in receive mode, no signal)•Medical and industrial data collection•Notebook computers, desktop PCs, Palmtop Computers (Win CE, Palm PC), PDAs•Internet TV boxes, video conferencing systems •External infrared adapters (dongles)•Kiosks, POS, Point and Pay devices includingIrFM - applications Document Number 82616Parts TableFunctional Block DiagramPin DescriptionPartDescriptionQty / ReelTFDU5307-TR1Oriented in carrier tape for side view surface mounting 750 pcs TFDU5307-TR3Oriented in carrier tape for side view surface mounting 2500 pcs TFDU5307-TT1Oriented in carrier tape for top view surface mounting 750 pcs TFDU5307-TT3Oriented in carrier tape for top view surface mounting2500 pcsPin NumberFunction DescriptionI/OActive1IRED Anode Connect IRED anode to the V CC2 power supply through an external current limiting resistor. A separate unregulated power supply can be used at this pin.2IRED Cathode IRED Cathode, internally connected to the driver transistor3TXDThis Schmitt-Trigger input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 80 μs. When used in conjunction with the SD pin, this pin is also used to control receiver output pulse duration. The input threshold voltage adapts to andfollows the logic voltage reference applied to the V logic pin (pin 7).IHIGH4RXD Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k Ω (typ.) in shutdown mode. The voltage swing isdefined by the applied V logic voltage O LOW5SD Shutdown. Also used for setting the output pulse duration. Setting this pin active for more than 1.5 ms places the module into shutdown mode. Before that (t < 0.7 ms) on the falling edge of this signal, the state of the TXD pin is sampled and used to set the receiver output to long pulse duration (2 µs) or to short pulse duration (0.4 μs) mode. The input threshold voltage adapts to and follows the logic voltagereference applied to the V logic pin (pin 7).I HIGH6V CC1Supply Voltage7V logicV logic defines the logic voltage levels for input and output. The RXD output range is from 0 V to V logic , for optimum noise suppression the inputs’ logic decision levelis 0.5 x V logicI 8GNDGroundDocument Number PinoutTFDU5307weight 75 mgDefinitions:In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes:SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/sMIR and FIR were implemented with IrPhy 1.1, fol-lowed by IrPhy 1.2, adding the SIR Low Power Stan-dard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former version.With introducing the updated versions the old ver-sions are obsolete. Therefore the only valid IrDA stan-dard is the actual version IrPhy 1.4 (in Oct. 2002).Absolute Maximum RatingsReference point Ground (pin 8) unless otherwise noted.Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.ParameterTest ConditionsSymbol Min T yp.Max Unit Supply voltage range, transceiver- 0.3 V < V CC2 < 6 V - 0.5 V < V logic < 5.5 V V CC1- 0.3+ 6.0V Supply voltage range, transmitter- 0.5 V < V CC1 < 6 V - 0.5 V < V logic < 5.5 V V CC2- 0.3+ 6.5V Supply voltage range, V logic - 0.5 V < V CC1 < 6 V - 0.3 V < V CC2 < 6.5 VV logic- 0.3+ 5.5V Input currentfor all pins, except IRED anode pin10mA Output sinking current 25mA Power dissipation see derating curve, figure 4P D 500mW Junction temperature T J 125°C Ambient temperature range (operating)T amb - 25+ 85°C Storage temperature range T stg- 25+ 85°C Soldering temperature see recommended solder profile (figure 3)260°C Average output current, pin 1I IRED(DC)125mA Repetitive pulsed output current, pin 1 to pin 2t < 90 µs, t on < 20 %I IRED(RP)600mA IRED anode voltage, pin 1V IREDA - 0.5+ 6.5V Voltage at all inputs and outputs V in < V CC1 is allowed V in- 0.5+ 5.5V Load at mode pin when used as mode indicator50pF Document Number 82616Eye safety information*) Due to the internal limitation measures the device is a "class 1" device.**) IrDA specifies the max. intensity with 500 mW/sr.Electrical Characteristics TransceiverT amb = 25°C, V CC1 = V CC2 = 2.7 V to 5.5 V unless otherwise noted.Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.*)Standard illuminant A**) The typical threshold level is 0.5 x Vlogic . It is recommended to use the specified min/max values to avoid increased operating current.The inputs in low state are actively loaded for noise protection. See for that the "Controlled pull down current" spec. Equivalently a pull up current stabilizes the state when the inputs are in high state.ParameterT est ConditionsSymbol Min T yp.MaxUnit Virtual source sizeMethod: (1-1/e) encircled energyd 1.82.0mm Maximum intensity for class 1IEC60825-1 or EN60825-1, edition Jan. 2001, operating below the absolute maximum ratingsI e(500)*) **)mW/srParameterT est Conditions Symbol Min T yp.Max Unit Supply voltage V CC1 2.75.5V Idle supply current SD = Low, E e = 1 klx I CC1550900µA Average dynamic supply current, transmitting I IRED = 500 mA, 25 % Duty CycleI CC 11001500µA Shutdown supply currentSD = High, T = 25°C, E e = 0 klx I SD 1µA SD = High, T = 25°C, E e = 1 klx *)I SD 2.5µA Standby supply current SD = High, T = 85°C, not ambient light sensitive I SD 5µA Operating temperature range T A- 25+ 85°C Output voltage low, RXD C Load = 15 pF , I OL = 1 mA V OL 0.4V Output voltage high, RXD I OH = - 500 µAV OH 0.8 x V logic V I OH = - 250 µA, C Load = 15 pFV OH 0.9 x V logicVRXD to V CC1 impedance R RXD 400500600k ΩInput voltage low (TXD, SD)V IL - 0.50.5V Input voltage high (TXD, SD)CMOS level **)V IH V logic - 0.5V logic + 0.5V Input leakage current (TXD, SD)V in = 0.9 x V logicI ICH - 2+ 2µA Controlled pull down currentSD, TXD = "0" to "1", 0 < V in < 0.15 V logic I IRTx + 150µA SD, TXD = "0" to "1", V in > 0.7 V logicI IRTx - 11µA Input capacitance (TXD, SD)C IN5pFDocument Number Optoelectronic Characteristics ReceiverT amb = 25°C, V CC = 2.7 V to 5.5 V unless otherwise noted.Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.*)Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore this additional mode was added in TFDU5307.TFDU5307 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (SD must have been longer active than 1.5 ms). For mode changing see the chapter "Programming"ParameterTest ConditionsSymbol MinTyp.Max Unit Minimum detection threshold irradiance9.6 kbit/s to 1.152 Mbit/s λ = 850 nm - 900 nm E e 40(4)90(9)mW/m 2(µW/cm 2)Maximum detection threshold irradianceλ = 850 nm - 900 nm E e 5(500)kW/m 2(mW/cm 2)No detection receiver input irradianceThreshold! No RXD output below this irradiance value allowedE e4(0.4)mW/m 2(µW/cm 2)Rise time of output signal 10 % to 90 %, C L = 15 pF , V logic = V CCt r(RXD)2060ns Fall time of output signal90 % to 10 %, C L = 15 pF , V logic = V CCt f(RXD)2060ns RXD pulse width of outputsignal, default mode after power on or resetinput pulse length P Wopt > 200 ns t PW300400500nsSIR ENDEC compatibility mode *): RXD pulse width of output signalinput pulse lengthP Wopt > 200 ns, see chapter "Programming"t PW1.72.0 2.9µsStochastic jitter, leading edgeinput irradiance = 100 mW/m 2, 1.152 Mbit/s, 576 kbit/s 80ns input irradiance = 100 mW/m 2, ≤ 115.2 kbit/s350ns Standby /Shutdown delay after shutdown active or (SD low to high transition)0.61.5ms Shutdown active time window for programmingDuring this time the pulse duration of the output can be programmed to the application mode. see chapter "Programming"600µsReceiver start up time power on delay shutdown recovery delay after shutdown inactive (SD high to low transition) and afterpower-on 300µsLatencyt L200µs Document Number 82616TransmitterT amb = 25°C, V CC = 2.7 V to 5.5 V unless otherwise noted.Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.*) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source forthe standard Remote Control applications with codes as e.g. Philips RC5/RC6® or RECS 80. When operated under IrDA full range con-ditions (>120 mW/sr) the RC range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used.**)Typ. conditions for I f = 420 mA, V CC2 = 3.3 V, R s = 2.3 Ω, V CC2 = 5.0 V, R s = 6.4 ΩParameterT est ConditionsSymbol MinT yp.Max Unit IRED operating current,recommended serial resistor for MIR applicationsV CC2 = 3.3 V: R S = 2.0 ΩV CC2 = 5.0 V: R S = 5.6 ΩI D450500mAOutput leakage IRED current TXD = 0 V, 0 < V CC1 < 5.5 V I IRED - 11µA Output radiant intensity recommended application circuit, see figure 1α = 0°, I f =420 mA TXD = High, SD = Low **)I e110500mW/srα = 0°, 15°, I f =420 mA TXD = High, SD = Low **)I e70120500mW/srOutput radiant intensityV CC1 = 5.0 V , α = 0°, 15°TXD = Low or SD = High(Receiver is inactive as long as SD = High)I e0.04mW/srOutput radiant intensity, angle of half intensityα± 24°Peak - emission wavelength *)λp 880900nm Spectral bandwidth Δλ45nm Optical rise time, fall time t ropt , t fopt640ns Optical output pulse durationinput pulse width 217 ns, 1.152 Mbit/sNote: IrDA specification for MIR t opt190(147.6)217240(260)ns ns input pulse width t TXD < 80 µs t opt 20t TXD µs input pulse width t TXD ≥ 80 µst opt2085µs Optical overshoot25%Document Number Recommended Circuit DiagramUsed with a clean low impedance power supply the TFDU5307 only needs an external series current lim-iting resistor. However, depending on the entire sys-tem design and board layout, additional components may be required (see figure 1).The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line.This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current.The resistor R1 is the current limiting resistor and this is supply voltage dependent, see derating curve in fig-ure 4, to avoid too high internal power dissipation.Vishay’s transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin,long, resistive and inductive wiring should be avoided.The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit.The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage.R2, C 1 and C 2 are optional and dependent on the quality of the supply voltages and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and trans-mission range) of the transceiver.The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. A Tantalum capac-itor should be used for C1 while a ceramic capacitor is used for C2.In addition, when connecting the described circuit to the power supply, low impedance wiring should be used.When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at V CC2. Often some power supplies are not apply to follow the fast current rise time. In that case another 4.7 µF (type, see table under C1) at V CC2 will be help-ful.Under extreme EMI conditions as placing an RF-transmitter antenna on top of the transceiver, we rec-ommend to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the RXD port.Keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termi-nation. See e.g. "The Art of Electronics" Paul Horow-itz, Winfield Hill, 1989, Cambridge University Press,ISBN: 0521370957.Table 1.Recommended Application Circuit ComponentsFigure 1. Recommended Application CircuitV IRED V cc G N D SD TXD RXD18147V logicComponentRecommended Value Vishay Part Number C1 4.7 µF , 16 V , T antalum 293D 475X9 016B C20.1 µF , CeramicVJ 1206 Y 104 J XXMTR15 V supply voltage: 5.6 Ω s. text 0.25 W (recommended using two 2.8 Ω, 0.125 W resistors in series). 3.3 V supply voltage: 2.0 Ω s. text 0.25 We.g. 2 x CRCW-1206-2R0-F-RT1 for 3.3 V supply voltageR247 Ω, 0.125 WCRCW-1206-47R0-F-RT1 Document Number 82616I/O and SoftwareIn the description, already different I/Os are men-tioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application.ProgrammingPulse duration SwitchingAfter Power-on the TFDU5307 is in the default short RXD pulse duration mode.Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore an additional mode with extended pulse duration (same as in standard SIR transceivers) is added in TFDU5307. TFDU5307is set to the "short output pulse" as default after power on, and after recovering from the shutdown mode (SD being active longer than 1.5 ms).To switch the transceivers from the short RXD pulse duration mode to the long pulse duration mode and vice versa, follow the procedure described below.Setting to the ENDEC compatibility mode with an RXD pulse duration of 2 µs1. Set SD input to logic "HIGH".2. Set TXD input to logic "LOW". Wait t s ≥ 200 ns.3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting).4. After waiting t h ≥ 200 ns.After that TXD is enabled as normal TXD input and the RXD output is set for the longer RXD - pulse dura-tion mode.Setting back to the default mode with a 400 ns pulse duration1. Set SD input to logic "HIGH".2. Set TXD input to logic "HIGH". Wait t s ≥ 200 ns.3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting).4. After waiting t h ≥ 200 ns TXD can be set to logic "LOW". The hold time of TXD is limited by the maxi-mum allowed pulse length.After that TXD is now enabled as normal TXD input and the RXD output is set for the short RXD - pulse duration mode.The timing of the pulse duration changing procedure is quite uncritical. However, the whole change must not take more than 600 µs. See in the spec. "Shut-down Active Time Window for Programming"Simplified MethodSetting the device to the long pulse duration is simply applying a short active (less than 600 µs) pulse to SD. In any case a short SD pulse will force the device to leave the default mode and go the compatibility mode. Vice versa applying a 1.5 ms (minimum) pulse at SD will cause the device to go back to the default mode by activating a power-on-reset and setting the device to the default short pulse mode. This simplified method takes more time but may be easier to handle.Figure 2. Timing Diagram for changing the output pulse duration18150Document Number Table 2.Truth tableInputsOutputs Remark SD TXD Optical input Irradiance mW/m 2RXD T ransmitterOperationhigh < 600 µs x x weakly pulled (500 k Ω) to V CC10Time window for pulse durationsettinghigh > 1.5 ms x x weakly pulled (500 k Ω) to V CC10Shutdown lowhigh x low (active)I e Transmitting high > 80 ms x high inactive 0Protection is activelow< 4high inactiveIgnoring low signals below the IrDAdefined threshold for noiseimmunity low > Minimum irradiance E e < Maximum irradiance E e low (active)0Response to an IrDA compliantoptical input signal low> Maximum irradiance E eundefinedOverload conditions can causeunexpected outputs Document Number 82616Recommended Solder ProfileSolder Profile for Sn/Pb solderingLead-Free, Recommended Solder ProfileThe lead-frame based transceivers (all types with the name TFDUxxxx) are lead (Pb)-free and qualified forlead (Pb)-free and lead - bearing processing.In case of using a lead-bearing process we recom-mend a solder profile as shown in figure 4.For lead (Pb)-free solder paste like Sn-(3.0-4.0)Ag-(0.5-0.9)C u, there are two standard reflow profiles:Ramp-Soak-Spike (RSS) and Ramp-To-Spike (RTS).The Ramp-Soak-Spike profile was developed prima-rily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-To-Spike profile is used increasingly. Shown below in figure 5 and figure 6 are VISHAY’s recom-mende profiles for use with the TFDUxxxx transceiv-ers for lead (Pb)-free processing.Figure 3. Recommended Solder Profile for Sn/Pb solderingFigure 4. Solder Profile, RSS RecommendationTFDU5307Document Number 82616Rev. 1.5, 07-Apr-06Vishay Semiconductors11A ramp-up rate less than 0.9 °C /s is not recom-mended. Ramp-up rates faster than 1.3 °C/s damagean optical part because the thermal conductivity is less than compared to a standard IC.Current Derating DiagramFigure 6 shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 Ω is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85°C, too.Figure 5. Solder Profile, RTS RecommendationFigure 6. Temperature Derating Diagram5055606570758085902.02.53.03.54.04.55.05.56.0Operating V oltage [V ]at d u ty cycle 20 %A m b i e n t T e m p e r a t u r e (°C )18097 12Document Number 82616 Rev. 1.5, 07-Apr-06TFDU5307Vishay SemiconductorsTFDU5307 - TinyFace (Universal) Package (Dimensions in mm) (Mechanical Dimensions)TFDU5307Document Number 82616Rev. 1.5, 07-Apr-06Vishay Semiconductors13Reel DimensionsTape WidthA max.N W 1 min.W 2 max.W 3 min.W 3 max.mm mm mm mm mm mm mm 163305016.422.415.919.4 14Document Number 82616 Rev. 1.5, 07-Apr-06TFDU5307Vishay SemiconductorsTape Dimensions in mmDrawing-No.: 9.700-5280.01-4Issue: 1; 03.11.03Figure7. Tape drawing, TFDU5307 for top view mountingTFDU5307Document Number 82616Rev. 1.5, 07-Apr-06Vishay Semiconductors15Drawing-No.: 9.700-5279.01-4Issue: 1; 08.12.04Figure 8. Tape drawing, TFDU5307 for side view mounting 16Document Number 82616 Rev. 1.5, 07-Apr-06TFDU5307Vishay SemiconductorsOzone Depleting Substances Policy StatementIt is the policy of Vishay Semiconductor GmbH to1.Meet all present and future national and international statutory requirements.2.Regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.1.Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendmentsrespectively2.Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the EnvironmentalProtection Agency (EPA) in the USA3.Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.We reserve the right to make changes to improve technical designand may do so without further notice.Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, GermanyLegal Disclaimer NoticeVishay Document Number: Revision: 08-Apr-051NoticeSpecifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.。

调试笔记

ftp://192.168.1.131即可打开对应A15的磁盘存储器.A15后有M板时,须拨到1.新使用的A15板子初始化时,执行完文档的过程后须再键入bootChange,把A15的IP地址和网关再输一遍方可.A201S跳线：左边（OFF）为1，右边（ON）为0。

从下往上为高位到低位。

上面的一块最后3位没用，不用管他，其实这一块本来就基本不用动。

基地址跳线说明：主机架（RACK0）：0x700000+0x10000*（槽号-3）第一扩展机架（RACK1）：0xE00000+0x10000*（槽号-3）第二扩展机架（RACK2）：0xD00000+0x10000*（槽号-3）举例说明：如果A201S在主机架的第5槽，则跳线应为：0x700000+0x10000*（5-3）=0x720000M62(电压型±10V)的跳线:两根针的把红帽子拔掉，3根的插在里面两根.M62(电压型0-10V)的跳线:两根针的把红帽子插上，3根的插在外面两根.M351（电流型）的调试方法：由于是电流型，4~20MA对应0~32000，在两个端子之间串上大小合适的电阻（24V/0.004A=6KΩ，24V/0.02A=1.2 KΩ，所以电阻范围是 1.2 KΩ~6KΩ），然后看变量表中是不是对应的值就可以了。

M621（电压型）的调试方法：电压电流转换器把M62输出的电压转换成电流，直接接到柜门的毫安表上。

只要在伺服阀输入的两个端子之间串上大小合适的电阻（input rated command,200Ω）来代替伺服阀即可。

M62电压型的调试方法：在伺服阀输入的两个端子接上200Ω电阻，当作虚拟的伺服阀。

在A15里给M62输出，（-2047~2047，对应-10MA到+10MA），看柜门上的毫安表即可。

7.19.20071》。

M35测试: 用24V串一电阻,输入到对应AI点,从BKME变量表读AI即可.6400—32000对应4-20mA如:电阻用1.675K∩,24/1.675=14mA,(14/20)X32000约等于BKME读出的数21786.2》。

Skyworks Solutions Si5317 1 1 高性能时钟芯片评估板用户指南说明书

Si5317-EVB Si5317 E VALUATION B OARD U SER’S G UIDEDescriptionThe Si5317-EVB User’s Guide provides a complete and simple evaluation of the functions, features, and performance of the Si5317.The Si5317 is a pin-controlled 1:1 jitter-attenuating clock for high-performance applications.The Si5317 is based on Skyworks Solutions' 3rd-generation DSPLL® technology, which provides any-rate jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the application level.Features⏹ No software required. Simple jumpers for deviceconfiguration⏹ Fully powered from either a single USB port or anexternal power supply⏹ Selectable external reference clock or on-boardcrystal⏹ Status LEDs⏹ Header to connect to external test equipment forautomated testingSi5317-EVB1. Functional Block DiagramA functional block diagram of the EVB is shown in Figure1. The Si5317-EVB provides alarm and status outputs, programmable output clock signal format (LVPECL, LVDS, CML, CMOS), selectable loop bandwidths, and ultra low jitter.The Si5317 accepts a single clock input ranging from 1MHz to 710MHz and generates two equal frequency clock outputs ranging from 1 to 710MHz. The clock frequency range and loop bandwidth are selectable from a simple look-up table. The Si5317-EVB has a differential clock input that is AC terminated to 50 and then AC-coupled to the Si5317. The two clock outputs are AC-coupled. The XA-XB reference is usually a 114.285 MHz crystal; but there are provisions for an external XA-XB reference (either differential or single-ended). The device status are available on a ribbon header and LEDs. Control pins are strapped using jumper headers for device configuration and various board options. The board can be powered using either external power supplies or from a PC's USB port. Refer to the Si5317 data sheet for technical details of the device.Figure1.Si5317 EVB Block Diagram2SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Si5317-EVB 2. Si5317-EVB Input and Output Clocks2.1. Input ClocksThe Si5317-EVB has a differential clock input that is ac terminated and ac coupled before being presented to the Si5317. If the input clock frequencies are low (below 10MHz), there are extra considerations that should be taken into account. The Si5317 has a maximum clock input rise time specification of 11 ns that must be met (see CKNtrf in the Si5317 data sheet). Also, if the input clock is LVCMOS, it might be advantageous to replace the input coupling capacitors (C7, C12, C16. and C18) with 0 resistors. When using LVCMOS inputs, the user should consider removing the ac termination and using source series termination located at the driving source. Regardless of the input format, if the clock inputs are not approximately 50% duty cycle, it is highly recommended to avoid ac coupling. For input clocks that are far off of 50% duty cycle, the average value of the signal that passes through the coupling capacitor will be significantly off of the midpoint between the maximum and minimum value of the clock signal, resulting in a mismatch with the common mode input threshold voltage (see Vicm, in the Si5317 data sheet).2.2. XA-XB ReferenceTo achieve a very low jitter generation and for stability during holdover, the Si5317 requires a stable, low jitter reference at its XA-XB pins. To that end, the EVB is configured with a 114.285MHz third overtone crystal connected between pins 6 and 7 of the Si5317. However, the Si5317-EVB is also capable of using an external XA-XB reference oscillator, either differential or single-ended. For details concerning the allowed XA-XB reference frequencies and their RATE settings, see the Si5317 data sheet. J1 and J2 are the SMA connectors with ac termination. AC coupling is also provided that needs to be installed at C6 and C8. Table1 explains the component changes that are needed to implement an external XA-XB reference oscillator.Table 1. XA-XB Reference ConnectionsModeXtal Ext RefExt Ref In+NC J1Ext Ref In-NC J2C6, C8NOPOP installR8install NOPOPRATE0(See note 4)M HRATE1(See note 4)M MNotes:1.Xtal is 114.285 MHz.2. NC - no connect.3. NOPOP - do not install.4. J12 jumper, see Table3.5. C6 on bottom of the board.SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•3Si5317-EVB2.3. Output ClockThe clock outputs are AC-coupled and are available on SMAs J5, J7, J9 and J11. For LVCMOS outputs, it might be desirable to replace the AC coupling capacitors (C9,C14,C17, and C20) with 0 resistors. Also, if greater drive strength is desired for an LVCMOS output, R6 and R10 can be installed.2.4. Pin ConfigurationJ12 is the large jumper header in the center left of the board that implements the jumper plugs that configure the pins of the Si5317. Each pin can be strapped to become either H, M, or L. The H level is achieved by installing a jumper plug between the appropriate middle row pin and its VDD row pin. L is achieved by installing a jumper plug between the appropriate middle row pin and its GND row pin. M is achieved by installing no jumper plug.2.5. Evaluation Board PowerThe EVB can be powered from two possible sources: USB or external supplies. A 3.3V supply is required to run the LEDs because of their rather large forward drop. The Si5317 power supply can be separated from the 3.3V supply so that the Si5317 can be evaluated at a voltage other than 3.3V. It is important to note that when the USB supply is being used, the EVB uses the USB port only for power and that the resulting power supply is strictly 3.3V. Here are the instructions for the various possibilities:2.5.1. External Power SuppliesInstall a jumper between J16.1 and J16.2 (labeled EXT).There should be no USB connection.If the Si5317 is not being operated at 3.3V, two supplies should be connected to J14. Connect the 3.3V supply to J14.1 and J14.2 (labeled 3.3V and GND). Connect the SI5317 power supply between J14.2 and J14.3 (labeled GND and DUT).If the Si5317 is to be operated at 3.3V, J15 (labeled ONE PWR) can be installed, requiring only one external supply. Connect 3.3V power between J14.2 and J14.3 (labeled GND and DUT).2.5.2. USB PowerInstall a jumper between J16.2 and J16.3 (labeled USB).Install a jumper at J15 (labeled ONE PWR).With a USB cable, plug the EVB into a powered USB port.2.5.3. USB 3.3V Power, External Si5317 PowerInstall a jumper between J16.2 and J16.3 (labeled USB).No jumper at J15 (labeled ONE PWR).Connect the Si5317 power supply between J14.2 and J14.3 (labeled GND and DUT).4SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Si5317-EVBSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 53. Connectors and LEDs3.1. LEDs3.2. Jumpers, Headers, and ConnectorsRefer to Figure 2 to locate the items described in this section.Figure 2.EVB Jumper LocationsTable 2. LED DescriptionsLED Label SignificanceD1CS_CA Not used D2LOS2Not usedD3LOS1ON = no valid clock input D4LOL ON = Si5317 is not locked D5DUT_PWR ON = Si5317 power is present D63.3VON = 3.3V power is presentSi5317-EVBTable 3. Configuration Header, J12J12PinJ12.1not usedJ12.2SFOUT0J12.3SFOUT1J12.4FRQSEL0J12.5FRQSEL1J12.6FRQSEL2J12.7FRQSEL3J12.8FRQTBLJ12.9BWSEL0J12.10BSWEL1J12.11DBL2_BYJ12.12not usedJ12.13RATE0J12.14RATE1Table 4. Status Indication Header, J13J13SignalJ13.1INCJ13.3DECJ13.5LOSJ13.7Not usedJ13.9Not usedJ13.11LOLJ13.13RST_B6SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Si5317-EVBSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 74. SchematicC AC K I N 1C K I N 1C K I N C K I N E x t R e f E x t R e f m p e r u g so p t i o n e e o p t i o n lJ 1F i g u r e 3.S i 5317-E V BSi5317-EVB8SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•D U T _P W RG N D3.3VE V m a p o g r o u n d p i n sJ 23J 20J P h o e n i x J 21J 19J 25J 26J 24J 22J 18F i g u r e 4.L E D a n d P o w e r /U S BSi5317-EVBSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 95. Bill of MaterialsItem Qty Reference Part Mfr MfrPartNum BOMDigikeyFootprint 16C1,C2,C3,C13,C15,C1910NFVenkelC0603X7R160-103KNE 603211C4,C7,C9,C10,C11,C12,C14,100N Venkel C0603X7R160-104KNE603C16,C17,C18,C2033C5,C22,C251UF Venkel C0603X7R6R3-105KNE 60352C21,C24220UF Kemet T494B227M004AT 399-4631-1-NDSM_C_3528_2162C23,C2633UF Venkel TA006TCM336MBR 352871D1Yel Panasonic LN1471YTR P11125CT -ND LED_gull 83D2,D3,D4Red Lumex LN1271RAL P493CT-ND LED_gull 92D5,D6Grn Panasonic LN1371G P491CT-ND LED_gull 1110J1,J2,J4,J5,J6,J7,J8,J9,SMA_EDGEJohnson142-0701-801J502-ND SMA_EDGE_p062J10,J11131J1214x3_M_H-DR_THRU any two and one row side by side 20x3_M_HDR_THRU151J14Phoenix_3_screw PhoenixMKDSN 1.5/3-5.08277-1248-NDPhoenix3pinM_p2pitch161J15Jmpr_2pin 171J16Jmpr_3pin 3pin_p1pitch 181J17USB FCI61729-0010BLF609-1039-NDUSB_typeB 194J19,J20,J24,J26Jmpr_1pin 1pin_p1pitch202L1,L2Ferrite Venkel FBC1206-471H 1206215Q1,Q2,Q3,Q4,Q5BSS138On SemiBSS138LT1GBSS138L T10SCT-NDSOT23Si5317-EVB10SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•234R2,R8,R13,R160 ohm Venkel CR0603-16W-000T 603246R3,R4,R5,R7,R9,R1149.9Venkel CR0603-16W-49R9FT 603261R1410Venkel CR0603-16W-10R0FT 603272R15,R2010k Venkel CR603-16W-1002FT 603282R17,R18150Venkel CR0603-16W-1500FT 603291R19R150x4Panasonic EXB-38V151JV Y9151CT-ND1206x4311U1Si5317Skyworks Solutions Si5317A-C-GM QFN-36321U2FAN1540BFairchildFAN1540BPMXFAN1540BMPXCT-ND MLP6331X1114.285 MHz TXC 7MA1400014xtal 3.2 x 2.5343standoff SPC Tech 2397353spacerRichcoNSS-4-4-0142C6,C810NF VenkelC0603X7R160-103KNENOPOP 603121J3Jmpr_2pinNOPOP221R1100Venkel CR0603-16W-1000FT NOPOP 603253R6,R10,R120 VenkelCR0603-16W-000TNOPOP 603302TP1,TP2test_points NOPOP141J1314_M_Header 3M N2514-6002RBNOPOP MHC14K-ND 14pinMdualHead-er_p1pitch 199J18,J21,J22,J23,J25Jmpr_1pinNOPOP1pin_p1pitchItem Qty Reference Part Mfr MfrPartNum BOMDigikeyFootprintSi5317-EVB 6. LayoutFigure5.Silkscreen TopSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•11Si5317-EVB12SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Figure 6.Layer 1Si5317-EVBSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 13Figure 7.Layer 2—Ground PlaneSi5317-EVB14SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Figure 8.Layer 3Si5317-EVBSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 15Figure 9.Layer 4Si5317-EVB16SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Figure 10.Layer 5, FILT_DUT_PWRSi5317-EVBSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 17Figure 11.Layer 6, BottomSi5317-EVB18SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Figure 12.Bottom SilkscreenSi5317-EVB 7. Factory Default ConfigurationJ12Pin JumperJ12.1not used—J12.2SFOUT0HJ12.3SFOUT1LJ12.4FRQSEL0LJ12.5FRQSEL1MJ12.6FRQSEL2MJ12.7FRQSEL3HJ12.8FRQTBL LJ12.9BWSEL0MJ12.10BSWEL1HJ12.11DBL2_BY LJ12.12not used—J12.13RATE0MJ12.14RATE1MThe above jumper settings result in the following:⏹ SFOUT = CMOS output⏹ 10.0 MHz input clock⏹ 10.0 MHz output clock⏹ BW =88 Hz⏹ RATE[1:0] = 114.285 MHz 3rd overtone crystalSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•19Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, speciﬁcations or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conﬂicts, incompatibilities, or other diﬃculties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.Customers are responsible for their products and applications using Skyworks products, which may deviate from published speciﬁcations as a result of design defects, errors, or operation of products outside of published parameters or design speciﬁcations. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published speciﬁcations or parameters.Skyworks, the Skyworks symbol, Sky5®, SkyOne ®, SkyBlue™, Skyworks Green™, Clockbuilder ®, DSPLL ®, ISOmodem ®, ProSLIC ®, and SiPHY ® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identiﬁcation purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at , are incorporated by reference.Portfolio/ia/timingSW/HW/CBProQuality/qualitySupport & Resources/supportSkyworksSolutions,Inc.|Nasdaq:SWKS|*********************| USA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540 |。

Agilent3070 常用元器件调试方法(Analog)

3)三极管三极管分NPN型和PNP型两种.我们一般只对它进行二极管测试,NPN的B为正,C,E分别为二个二极管的负极.PNP刚好相反,B为负极,C,E分别为二个二极管的正极.具体调试方法与二极管一致.
如图a所示,在测试三极管Q25时,正确的程序应为: disconnect all connect s to “E" connect i to “B" diode "B-E", 880m, 597m, idc10m, co3.0, ar1.1,wa10m ! "q15 B-E" test. off failure disconnect all connect s to “C" connect i to “B" diode "B-C", 880m, 603m, idc10m, co3.0, ar1.1,wa10m ! "q15 B-C" test.
subtest "Von" source dcv,am3.3, terminated 500, ico1,on auxiliary dcv, am3.3, on, ico1 detector dcv, expect 100m wait 10m measure 500m, -100m end subtest
电压验证FET功能缺失
Байду номын сангаас
a)FET导通测试(ON)---N管方法:在D极给一个高电平,G极给一个高电平(能够达到导通条件),MOS管会导通,那么D极的电压会被拉到GND,变成低电平
可debug参数：am,terminiated,Wait 时间 Source am不可以为0V,am电压值视电路而定

IBM Worklight V5.0.5 初学者指南模块14：客户端调试说明书

8
© Copyright International Business Machines Corporation 2011, 2013. All rights reserved.
Agenda
About Debugging on a desktop browser Debugging with IBM Worklight debugger Testing the adapter procedures Debugging with Weinre Debugging with iWebInspector Debugging with iOS Remote Web Inspector Debugging with Mobile Browser Simulator
Trademarks
IBM, the IBM logo, and are trademarks or registered trademarks of International Business Machines Corporation, registered in many jurisdictions worldwide. Worklight is a trademark or registered trademark of Worklight, an IBM Company. Other product and service names might be trademarks of IBM or other companies. A current list of IBM trademarks is available on the Web at “Copyright and trademark information” at /legal/copytrade.shtml.

OMAP3530软件调试笔记

硬件环境：采用TI omap3530的天漠科技开发板和公司的板卡。

软件环境：天漠科技开发包：* linux kernel: 2.6.29-sbc8100* u-boot-1.3.3* x-load-1.41后续移植linux-omap:* linux kernel: 2.6.38作者：agan成都莱得科技联系邮箱*****************.cn转载须注明出处！内容简介：描述调试过程中所遇问题及其解决办法和过程，可作为新手的FAQ使用。

1. Issue: 不能从SD卡启动。

Fixed: 自己疏忽造成，手册已经提到要先用"HP Disk Storage Format Tool"格式化SD卡。

2. Issue: 烧写的Xload不能启动。

Fixed: ECC格式不对造成，xload需要使用HW Ecc, 其他全部使用SW ECC。

列表如下：x-loader 'nand ecc hw'u-boot 'nand ecc sw'okernel 'nand ecc sw'rootfs 'nand ecc sw'spash 'not required', default sw without oob3. Issue: 启动过程中打印错误信息"Ignoring unrecognised tag 0x54410008".Fixed: 屏蔽掉U-Boot中的函数'setup_videolfb_tag', 因为它传递了错误的参数给Kernel.4. Issue: 启动过程中打印错误信息"dpll3_m2_clk rate change failed: -22".Fixed: 这个错误发生在初始化SDRAM的PLL时钟的时候。

修改文件"arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h", 修改数组'mt46h32m32lf6_sdrc_params'的第3个指，把133333333改成133000000.SDRAM的默认时钟为266MHZ(LPDDR: Low Power Double Data Rate, so it running 133MHZ instead), 计算结果应该为 133000000, 而非预定义的133333333，所以报了错。

28335的一些调试经验

V4 所有外设配置，针对开发板（除CAN口和EQEP）V5 针对项目，配置了对应的外设（包含有EQEP）V6 针对开发板，对EQEP进行了调试和配置V7 添加控制程序PWM初始状态：（1）上电为低电平（2）初始化GPIO之后变为低电平（InitGPio）（3）InitEPwmGpio之后为低电平（EPWM默认为不上拉（其他的为默认上拉），输入脚）（4）InitEPwm之后，高阻态（通过TZ实现的）（6）如果PWM定时器中断的时间不够，可以改变ET的触发次数值来实现延长中断时间的目的，而不改变PWM的周期TZ调试（1）开发板上由于复用了引脚，因此TZ3~TZ6都不可用，程序中使用了TZ1和TZ2 (要修改为TZ5和TZ6，只需用在InitEPwm中修改两处，以及将InitTzGpio中的注释部分去掉)（2）出现TZ将PWM置于高阻态，测量引脚实际是高电平（3）CBC（适用于电流限制）是出现TZ封锁，TZ消失后恢复（自动的）；one shot（适用于短路电流和过流）是一旦出现，就一直保持是封锁状态（但也可以手动恢复：//EALLOW;//EPwm1Regs.TZCLR.bit.OST = 1;//EPwm1Regs.TZCLR.bit.INT = 1;// EDIS;（4）通过TZ来进行脉冲的封锁与使能逻辑顺序是：关中断——封脉冲（softforce）——开脉冲（清除flag位）——开中断使用232进行控制,232中断里完成清除flag位与开中断的任务。

（5）将机侧和网侧都改为one shot trip sources，CBC在软件trip的时候不是很好用,无法封锁脉冲SCI调试（1）使能FIFO，设置为接收一个数据便进入一次中断（2）串口调试助手应选择16进制发送，即在发送之前把发送内容变为16进制，这样DSP 收到的数才正确（3）ScicRegs.SCIRXBUF.all里的数在读出之后便无效，使用观察窗口看不到接收到的数（4）如果是9600的波特率，5K的开关频率，限于通讯速率，如果发送使用查询模式，一次中断只发送一个数据。

TPS54327 降压转换器评估模块用户手册说明书

User’s GuideTPS54327 Step-Down Converter Evaluation Module User's GuideABSTRACTThis user's guide contains information for the TPS54327 as well as support documentation for theTPS54327EVM-686 evaluation module. Included are the performance specifications, schematic, and the billof materials of the TPS54327EVM-686.Table of Contents1 Introduction (3)2 Performance Specification Summary (4)3 Modifications (5)3.1 Output Voltage Setpoint (5)3.2 Output Filter and Closed Loop Response (5)4 Test Setup and Results (6)4.1 Input/Output Connections (7)4.2 Start-Up Procedure (7)4.3 Efficiency (8)4.4 Load Regulation (9)4.5 Line Regulation (10)4.6 Load Transient Response (10)4.7 Output Voltage Ripple (11)4.8 Input Voltage Ripple (11)4.9 Start-Up (12)5 Board Layout (13)5.1 Layout (13)6 Schematic, Bill of Materials, and Reference (16)6.1 Schematic (16)6.2 Bill of Materials (16)6.3 Reference (16)7 Revision History (17)List of FiguresFigure 4-1. TPS54327EVM-686 Efficiency (8)Figure 4-2. TPS54327EVM-686 Light Load Efficiency (8)Figure 4-3. TPS54327EVM-686 Load Regulation, V IN = 5 V (9)Figure 4-4. TPS54327EVM-686 Load Regulation, V IN = 12 V (9)Figure 4-5. TPS54327EVM-686 Line Regulation (10)Figure 4-6. TPS54327EVM-686 Load Transient Response (10)Figure 4-7. TPS54327EVM-686 Output Voltage Ripple (11)Figure 4-8. TPS54327EVM-686 Input Voltage Ripple (11)Figure 4-9. TPS54327EVM-686 Start-Up Relative to V IN (12)Figure 4-10. TPS54327EVM-686 Start-Up Relative to EN (12)Figure 5-1. Top Assembly (13)Figure 5-2. Top Layer (14)Figure 5-3. Bottom Layer (14)Figure 5-4. Bottom Assembly (15)Figure 6-1. TPS54327EVM-686 Schematic Diagram (16)Trademarks List of TablesTable 1-1. Input Voltage and Output Current Summary (3)Table 2-1. TPS54327EVM-686 Performance Specifications Summary (4)Table 3-1. Output Voltages (5)Table 4-1. Connection and Test Points (7)Table 6-1. Bill of Materials (16)TrademarksSWIFT™ and D-CAP2™ are trademarks of Texas Instruments.All trademarks are the property of their respective owners. Introduction1 IntroductionThe TPS54327 is a single, adaptive on-time, D-CAP2™-mode, synchronous buck converter requiring a verylow external component count. The D-CAP2™ control circuit is optimized for low-ESR output capacitors suchas POSCAP, SP-CAP, or ceramic types and features fast transient response with no external compensation. The switching frequency is internally set at a nominal 700 kHz. The high-side and low-side switching MOSFETs are incorporated inside the TPS54327 package along with the gate drive circuitry. The low drain-to-source on resistance of the MOSFETs allows the TPS54327 to achieve high efficiencies and helps keep the junction temperature low at high output currents. The TPS54327 dc/dc synchronous converter is designed to provide up to a 3-A output from an input voltage source of 4.5 V to 18 V. The output voltage range is from 0.76 V to 7 V. Rated input voltage and output current range for the evaluation module are given in Table 1-1.The TPS54327EVM-686 evaluation module is a single, synchronous buck converter providing 1.05 V at 3 A from 5-V to 18-V input. This user’s guide describes the TPS54327EVM-686 performance.Performance Specification Summary 2 Performance Specification SummaryA summary of the TPS54327EVM-686 performance specifications is provided in Table 2-1. Specifications are given for an input voltage of VIN = 12 V and an output voltage of 1.05 V, unless otherwise noted. The ambient temperature is 25°C for all measurement, unless otherwise noted.3 ModificationsThese evaluation modules are designed to provide access to the features of the TPS54327. Some modifications can be made to this module.3.1 Output Voltage SetpointTo change the output voltage of the EVMs, it is necessary to change the value of resistor R1. Changing the value of R1 can change the output voltage above 0.765 V. The value of R1 for a specific output voltage can be calculated using Equation 1.For output voltage from 0.76 V to 7.0 V:R1VO =0.7651+R2æö´ç÷èø(1)Table 3-1 lists the R1 values for some common output voltages. For higher output voltages of 1.8 V or above, a feedforward capacitor (C4) may be required to improve phase margin. Pads for this component (C4) are provided on the printed-circuit board. Note that the values given in Table 3-1 are standard values and not the exact value calculated using Table 3-1.3.2 Output Filter and Closed Loop ResponseThe TPS54327 relies on the output filter characteristics to ensure stability of the control loop. The recommended output filter components for common output voltages are given in Table 3-1. It may be possible for otheroutput filter component values to provide acceptable closed loop characteristics. R3 and TP4 are provided for convenience in breaking the control loop and measuring the closed loop response. ModificationsTest Setup and Results 4 Test Setup and ResultsThis section describes how to properly connect, set up, and use the TPS54327EVM-686. The section also includes test results typical for the evaluation modules and efficiency, output load regulation, output line regulation, load transient response, output voltage ripple, input voltage ripple, start-up, and switching frequency. Test Setup and Results 4.1 Input/Output ConnectionsThe TPS54327EVM-686 is provided with input/output connectors and test points as shown in Table 4-1. A power supply capable of supplying 2 A must be connected to J1 through a pair of 20 AWG wires. The load must be connected to J2 through a pair of 20 AWG wires. The maximum load current capability is 3 A. Wire lengths must be minimized to reduce losses in the wires. Test point TP1 provides a place to monitor the V IN input voltages with TP2 providing a convenient ground reference. TP8 is used to monitor the output voltage with TP9 as the ground reference.4.2 Start-Up Procedure1.Ensure that the jumper at JP1 (Enable control) is set from EN to OFF.2.Apply appropriate VIN voltage to VIN and PGND terminals at J1.3.Move the jumper at JP1 (Enable control) to cover EN and ON. The EVM enables the output voltage.4.3 EfficiencyFigure 4-1 shows the efficiency for the TPS54327EVM-686 at an ambient temperature of 25°C.0.00.51.01.52.02.53.00.010.020.030.040.050.060.070.080.090.0100.0V IN = 12 VV IN = 5 VOutput Current (A)E f f i c i e n c y (%)Figure 4-1. TPS54327EVM-686 EfficiencyFigure 4-2 shows the efficiency at light loads for the TPS54327EVM-686 at an ambient temperature of 25°C.0.0010.010.11100.010.020.030.040.050.060.070.080.090.0100.0V IN = 12 VV IN = 5 V Output Current (A)E f f i c i e n c y (%)Figure 4-2. TPS54327EVM-686 Light Load EfficiencyTest Setup and Results 4.4 Load RegulationThe load regulation for the TPS54327EVM-686 is shown in Figure 4-3 and Figure 4-4 .−0.5−0.4−0.3−0.2−0.10.00.10.20.30.40.5Output Current (A)O u t p u t V o l t a g e D e v i a t i o n (%)Figure 4-3. TPS54327EVM-686 Load Regulation, V IN = 5 V.−0.5−0.4−0.3−0.2−0.10.00.10.20.30.40.5Output Current (A)O u t p u t V o l t a g e D e v i a t i o n (%)Figure 4-4. TPS54327EVM-686 Load Regulation, V IN = 12 V. Test Setup and Results4.5 Line RegulationThe line regulation for the TPS54327EVM-686 is shown in Figure 4-5.−0.5−0.4−0.3−0.2−0.10.00.10.20.30.40.5Input Voltage (V)O u t p u t V o l t a g e D e v i a t i o n (%)Figure 4-5. TPS54327EVM-686 Line Regulation4.6 Load Transient ResponseThe TPS54327EVM-686 response to load transient is shown in Figure 4-6. The current step is from 0.75 A to 2.25 A. Total peak-to-peak voltage variation is as shown.V = 20 mV / div (dc offset -1.006 V)OUT I = 1A / div (0.75A to 2.25A load step)OUT Time = 10 µsec / divFigure 4-6. TPS54327EVM-686 Load Transient ResponseTest Setup and Results Test Setup and Results 4.7 Output Voltage RippleThe TPS54327EVM-686 output voltage ripple is shown in Figure 4-7. The output current is the rated full load of 3 A.V= 20 mV / div (ac coupled)OUTPH = 5 V / divTime = 1 µsec / divFigure 4-7. TPS54327EVM-686 Output Voltage Ripple4.8 Input Voltage RippleThe TPS54327EVM-686 input voltage ripple is shown in Figure 4-8. The output current is the rated full load of 3 A.V= 50 mV / div (ac coupled)INPH = 5 V / divTime = 1 µsec / divFigure 4-8. TPS54327EVM-686 Input Voltage RippleTest Setup and Results 4.9 Start-UpThe TPS54327EVM-686 start-up waveform relative to V IN is shown in Figure 4-9.V= 10 V / divINSS = 5 V / divV= 500 mV / divOUTTime = 2 msec / divFigure 4-9. TPS54327EVM-686 Start-Up Relative to V INThe TPS54327EVM-686 start-up waveform relative to enable (EN) is shown in Figure 4-10.EN = 10 V / divSS = 5 V / divV= 500 mV / divOUTTime = 2 msec / divFigure 4-10. TPS54327EVM-686 Start-Up Relative to EN Board Layout5 Board LayoutThis section provides description of the TPS54327EVM-686, board layout, and layer illustrations.5.1 LayoutThe board layout for the TPS54327EVM-686 is shown in Figure 5-1 through Figure 5-4. The top layer contains the main power traces for VIN, VO, and ground. Also on the top layer are connections for the pins of theTPS54327 and a large area filled with ground. Many of the signal traces also are located on the top side. The input decoupling capacitors are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. An analog ground (GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected at a single point on the top layer near C6. The bottom layer is primarily power ground but also has a trace to connect VIN to the enable jumper, a trace to connect VREG5 to TP5, and the feedback trace from VOUT to the voltage setpoint divider network.Figure 5-1. Top AssemblyBoard Layout Figure 5-2. Top LayerFigure 5-3. Bottom Layer Board LayoutFigure 5-4. Bottom AssemblySchematic, Bill of Materials, and Reference 6 Schematic, Bill of Materials, and Reference6.1 Schematicis the schematic for the TPS54327EVM-538.Figure 6-16.2 Bill of Materials1.TPS54327, Single Synchronous Converter With Integrated High Side and Low Side MOS FET data sheet(SLVSAG1) Revision History 7 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.Changes from Revision * (November 2010) to Revision A (October 2021)Page •Updated the numbering format for tables, figures, and cross-references throughout the document. (3)•Updated the user's guide title (3)IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements.These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.TI objects to and rejects any additional or different terms you may have proposed.Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2022, Texas Instruments Incorporated。

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阿5307调试笔记
1．void * 定义的类型是和机器的数据宽度一致，相当于int *
2．如果是函数或者数组如a[10] 或void delay（void）等，数组名或者函数名，如a或者delay就是地址，不用加“&”
3．NuCleus 的任务管理中，可以使用NU_Change_Preemption函数来进行保护，不让其他的任务打断他，使用的方法是
NU_Change_Preemption(NU_NO_PREEMPT); //禁止优先级抢占
…….
用户程序
…….
NU_Change_Preemption(NU_PREEMPT); //使能优先级抢占
4．读写CF卡时，调用NU_Read函数时，地址会自动加，不用手动添加偏移量
假设文件的前三个数据是“1”，“2”，“3”
Sta =NU_Read(FileP,&str1,1600);
Sta =NU_Read(FileP,&str2,1600);
Sta =NU_Read(FileP,&str3,1600);
运行之后，str1 = 1 ，str2 = 2 ，str3 = 3。

5．两个优先级一样的任务，当正在运行中的那个不挂起时，另一个任务即时就绪也不会得到运行，直到正在运行的那个任务挂起或者终止。

6．FLASH的下载
在欲下载的工程目录下运行linux-img.bat ，会在目录下生成app.txt 文件，把app.txt 拷贝到1-xidian-write-flash/main下面，然后运行1-xidian-write-flash/code-flash-test 下面的make.bat，然后把这个程序烧写到5307里，运行即可。

7．CF卡读写的问题，频繁的对CF卡进行读写，会造成无法读取CF卡的情况。

8．VHDL程序里面，PORT里面定义的引脚，即使后面的程序未用到，也一定要给他分配引脚号，不然会影响其他引脚的工作。

9．SingleStep调试的时候，如果reset，它仅仅是重新从main函数进行跑起，并没有运行main之前的初始化
10．除了直接操作底层的几个函数之外，GUI的大部分画图工作都是由Task_LCD完成的，其他的任务仅仅是修改framebuffer里的数据，然后发信号量给Task_LCD，也就是说可能会出现这种情况，一个任务，他先发送了信号量，紧接着又通过底层操作控制液晶，液晶执行的顺序是，先执行底层操作的那部分函数，当这个任务挂起的时候，Task_LCD这个任务得到信号量，再执行前面的操作，也就造成了程序没有顺序执行，而是颠倒了过来，这里必须要注意。

11．sprintf函数的功能
相当于字符串拷贝函数，这里要注意，字符串以0结尾，所以最后面会多一个0
12．5307的中断分析
5307的中断基本上分为7个中断级别，它的内部有10个中断源，分别由寄存器ICR0~ICR9来分别设置它的中断级别，另外它有三个外部中断输入，由寄存器IRQPAR来分配中断级别。

系统初始化的时候，这7个中断级别分别对应7个中断向量，分别为
DC.L _INT_Level_1_Auto ;25
DC.L _INT_Level_2_Auto ;26
DC.L _INT_Level_3_Auto ;27
DC.L _INT_Level_4_Auto ;28
DC.L _INT_Level_5_Auto ;29
DC.L _INT_Level_6_Auto ;30
DC.L _INT_Level_7_Auto ;31
我们需要为这几个中断向量指定中断服务程序的入口地址，如
MOVEA.L #0,A0 ;level 4 Pointer to the vector table
MOVE.L #0x1c,D0 ; vector number is #0x1c ,offset is 0x6c
LSL.L #2,D0 ; Adjust for the vector size
ADDA.L D0,A0 ; Add in offset to vector base
MOVE.L #_INT_Uart1_Interrupt, D0
MOVE.L D0,(A0)
则是为UART1指定入口的地址，他指向了_INT_Uart1_Interrupt，而在_INT_Uart1_Interrupt中，我们则进一步告诉它我们的中断服务程序的入口地址，
XDEF _INT_Uart1_Interrupt
_INT_Uart1_Interrupt:
LEA.L -60(A7),A7
MOVEM.L D0-D7/A0-A6,(A7)
JSR _Interrupt_UART1
MOVEM.L (A7),D0-D7/A0-A6
LEA.L 60(A7),A7
RTE
这样，当发生级别为4的中断时，系统会自动跳转到Interrupt_UART1去执行程序。

这里我们需要注意的地方是，中断级别的分配，例如，
imm->sim.IRQPAR = 0x20; /* 定义外部中断的级别: IRQ1=2, IRQ3=3,IRQ5=5 */ 这个时候我们就把外部中断1分配到了中断级别2，外部中断3分配到了中断级别3，外部中断5分配到了中断级别5，我们再继续给内部中断分配中断级别，这里我们以UART1和UART2来说明，UART1的控制器为ICR4，UART2的控制器为ICR5，我们设置ICR4[IL]=101，ICR5[IL]=101，这时，他们的中断级别都是5，这时我们还需要向他们分别分配优先级，一共有四种级别，由ICR寄存器的IP位来设置，这里我们设置ICR4[IP]=11，ICR5[IP]=01，这时，UART1具有比UART2更高的优先级，我们注意到IRQ5，UART1，UART2都具有相同的中断级别，但是系统规定，外部中断的优先级在10和01之间，所以最终的优先级顺序为UART1，IRQ5，UART2，这里要说明一下，IL=7的优先级最高，下来是IL=6，也就是说，每一个级别的中断最多只有5个中断源，而一共是7个中断级别，所以一共有35级优先级。

13．。