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CY7C68013A的特点及应用

CY7C68013的特点及应用【V1.0】1、USB2.0的主要特点USB协议的2.0版本于2000年4月推出。

支持以下3种速度模式：低速模式（low speed） 1.5Mb/s；全速模式（full speed） 12Mb/s高速模式（high speed） 480Mb/sUSB2.0协议支持现存的所有USB设备，既可以把USB1.1设备插入USB1.1的PC机接口，并且在电气上兼容USB1.1的连接线。

1.1 数据包USB传输的数据包的类型用称之为Packet Ids（PIDs）的特定代码来定义。

USB包中共有4种PID类型，如表1所列。

表1 USB2.0的数据包类型PID类型 PID名称令牌IN，OUT，SOF，SETUP 数据 DATA0，DATA1，DATA2，MDATA 握手 ACK，NAK，STALL，NYET 特殊类型 PRE，ERR，SPLIT，PIN注：黑体字表示USB2.0增加的PID类型。

在全速模式时，每个OUT传输发送OUT数据包，不考虑外设是否处于“忙”状态而不能接收数据。

针对这种浪费带宽的情况，在高速模式时推荐使用新的 PID类型“PING”。

主机先对OUT端点发出个较短的“PING”令牌，访问当前外设是否有数据文凭间来存放OUT的数据包。

仅仅当外部设备回答 “ACK”时，主机才发送较长OUT数据包。

SETUP邻牌只用于控制传输。

它数据包中的前8个字节。

通过这8个字节，外设对主机的设备请求进行译码。

SOF令牌代表一个USB帧的开始。

ACK（Acknowlegde）表示成功，数据接收无误。

NAK（Negavite Acknowlegde）表示忙，得发。

这并不是出错，USB外设没有应答表示出错。

STALL表示未知错误，外设未能理解主机发出的设备请求，可能是外设端出错，或是主机访问并存在的资源。

USB协议提供了从stall状态恢复的方法。

NYET（Not Yet）类似于ACK，表示数据接收无误，并且指出外设还没准备好接收下一个OUT数据包。

cy7c68013

声明本文节译于Cypress半导体公司的免费器件手册（CY7C68013，EZ-USB FX2TM USB Microcontroller，High-speed USB Peripheral Controller），原文从该公司网站获取。

由于本人水平所限，其中不当甚至错误之处在所难免，敬请指正，译者不对设计结果承担任何责任。

2006年7月目录1.0 EZ-USB FX2TM特性 (3)2.0 应用 (4)3.0 功能总览 (5)3.1 USB信号速率 (5)3.2 8051微处理器 (5)3.2.1 8051时钟频率 (5)3.2.2 UARTS (5)3.2.3 特殊功能寄存器 (6)3.3 I2C兼容总线 (6)3.4 总线 (6)3.5 USB启动模式 (6)3.6 再枚举 (7)3.7总线供电应用 (7)3.8 中断系统 (7)3.8.1 INT2 中断请求和使能寄存器 (7)3.8.2 USB中断的自动向量 (8)3.8.3 FIFO/GPIF 中断(INT4) (9)3.9 复位和唤醒 (9)3.9.1 复位引脚 (9)3.9.2 唤醒引脚 (10)3.10 程序/数据RAM (10)3.10.1 大小 (10)3.10.2内部代码存储器, EA = 0 (10)3.10.3 外部代码存储器, EA = 1 (11)3.11 寄存器地址 (13)3.12 端点RAM (13)3.12.1 大小 (13)3.12.2 组织 (13)3.12.3 设置数据缓冲器 (14)3.12.4 端点配置(高速模式) (14)3.12.5 默认的全速交替设置 (14)3.12.6默认的高速交替设置 (15)3.13 外部FIFO接口 (15)3.13.1 体系结构 (15)3.13.2 主/从控制信号 (15)3.13.3 GPIF和FIFO 的时钟速率 (16)3.14 GPIF (16)3.14.1 6个控制输出信号 (16)3.14.2 6个备妥输入信号 (16)3.14.3 9个GPIF地址输出信号 (17)3.14.4 长转移模式 (17)3.15 USB上载和下载 (17)3.16 自动指针访问 (17)3.17 I2C兼容控制器 (17)3.17.1 I2C兼容端口引脚 (18)3.17.2 I2C兼容接口启动加载访问 (18)3.17.3 I2C兼容接口通用寄存器访问 (18)1.0 EZ-USB FX2TM特性Cypress的EZ-USB FX2TM是世界上第一款集成了USB 2.0接口的微控制器。

CY7C68013A中文资料

EZ-USB FX2LP™ USB MicrocontrollerCY7C68013A/CY7C68014A CY7C68015A/CY7C68016A1.0Features (CY7C68013A/14A/15A/16A)•USB 2.0–USB-IF high speed certified (TID # 40440111)•Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor•Fit, form and function compatible with the FX2—Pin-compatible—Object-code-compatible—Functionally-compatible (FX2LP is a superset)•Ultra Low power: I CC no more than 85 mA in any mode —Ideal for bus and battery powered applications •Software: 8051 code runs from:—Internal RAM, which is downloaded via USB —Internal RAM, which is loaded from EEPROM —External memory device (128 pin package)•16 KBytes of on-chip Code/Data RAM•Four programmable BULK/INTERRUPT/ISOCHRO-NOUS endpoints—Buffering options: double, triple, and quad•Additional programmable (BULK/INTERRUPT) 64-byte endpoint•8- or 16-bit external data interface •Smart Media Standard ECC generation •GPIF (General Programmable Interface)—Allows direct connection to most parallel interface—Programmable waveform descriptors and configu-ration registers to define waveforms—Supports multiple Ready (RDY) inputs and Control (CTL) outputs•Integrated, industry-standard enhanced 8051—48-MHz, 24-MHz, or 12-MHz CPU operation —Four clocks per instruction cycle —Two USARTS—Three counter/timers—Expanded interrupt system —Two data pointers•3.3V operation with 5V tolerant inputs•Vectored USB interrupts and GPIF/FIFO interrupts •Separate data buffers for the Set-up and Data portions of a CONTROL transfer•Integrated I 2C controller, runs at 100 or 400 kHz •Four integrated FIFOs—Integrated glue logic and FIFOs lower system cost —Automatic conversion to and from 16-bit buses —Master or slave operation—Uses external clock or asynchronous strobes —Easy interface to ASIC and DSP ICs•Available in Commercial and Industrial temperature grade (all packages except VFBGA)A d d r e s s (16)x20PLL/0.5/1.0/2.08051 Core 12/24/48 MHz,four clocks/cycleI 2CVCC1.5kD+D–A d d r e s s (16) / D a t aB u s (8)FX2LPGPIFCY Smart USB 1.1/2.0EngineUSB 2.0XCVR16 KB RAM4 kB FIFOIntegrated full- and high-speedXCVRAdditional I/Os (24)ADDR (9)CTL (6)RDY (6)8/16D a t a (8)24 MHz Ext. XTALEnhanced USB core Simplifies 8051 code “Soft Configuration”Easy firmware changes FIFO and endpoint memory (master or slave operation)Up to 96 MBytes/s burst rateGeneralprogrammable I/F to ASIC/DSP or bus standards such as ATAPI, EPP , etc.Abundant I/Oincluding two USARTS High-performance micro using standard toolswith lower-power optionsMasterFigure 1-1. Block Diagramconnected for full speedECC1.1Features (CY7C68013A/14A only)•CY7C68014A: Ideal for battery powered applications —Suspend current: 100 µA (typ)•CY7C68013A: Ideal for non-battery powered applica-tions—Suspend current: 300 µA (typ)•Available in five lead-free packages with up to 40 GPIOs —128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs),56-pin QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VFBGA (24 GPIOs)1.2Features (CY7C68015A/16A only)•CY7C68016A: Ideal for battery powered applications—Suspend current: 100 µA (typ)•CY7C68015A: Ideal for non-battery powered applica-tions—Suspend current: 300 µA (typ)•Available in lead-free 56-pin QFN package (26 GPIOs)—2 more GPIOs than CY7C68013A/14A enabling addi-tional features in same footprintCypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP™ (CY7C68013A/14A) is a low-power version of the EZ-USB FX2™ (CY7C68013), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications.The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum-allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcon-troller in a package as small as a 56 VFBGA (5mm x 5mm). Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The FX2LP draws considerably less current than the FX2 (CY7C68013), has double the on-chip code/data RAM and is fit, form and function compatible with the 56-, 100-, and 128-pin FX2.Five packages are defined for the family: 56VFBGA, 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.2.0 Applications•Portable video recorder•MPEG/TV conversion•DSL modems•ATA interface•Memory card readers•Legacy conversion devices•Cameras•Scanners•Home PNA•Wireless LAN•MP3 players•NetworkingThe “Reference Designs” section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit for more information.3.0Functional Overview3.1USB Signaling SpeedFX2LP operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000:•Full speed, with a signaling bit rate of 12 Mbps •High speed, with a signaling bit rate of 480 Mbps.FX2LP does not support the low-speed signaling mode of 1.5Mbps.3.28051 MicroprocessorThe 8051 microprocessor embedded in the FX2LP family has 256 bytes of register RAM, an expanded interrupt system,three timer/counters, and two USARTs.3.2.18051 Clock FrequencyFX2LP has an on-chip oscillator circuit that uses an external 24-MHz (±100-ppm) crystal with the following characteristics:•Parallel resonant •Fundamental mode •500-µW drive level•12-pF (5% tolerance) load capacitors.An on-chip PLL multiplies the 24-MHz oscillator up to 480MHz, as required by the transceiver/PHY , and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically.The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051clock, at the selected 8051 clock frequency—48, 24, or 12MHz.3.2.2USARTSFX2LP contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are available on separate I/O pins, and are not multi-plexed with port pins.UART0 and UART1 can operate using an internal clock at 230KBaud with no more than 1% baud rate error. 230-KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz)such that it always presents the correct frequency for 230-KBaud operation.[1]3.2.3Special Function RegistersCertain 8051 SFR addresses are populated to provide fast access to critical FX2LP functions. These SFR additions are shown in Table 3-1. Bold type indicates non-standard,enhanced 8051 registers. The two SFR rows that end with “0”and “8” contain bit-addressable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not implemented in FX2LP . Because of the faster and more efficient SFR addressing, the FX2LP I/O ports are not addressable in external RAM space (using the MOVX instruction).3.3I 2C BusFX2LP supports the I 2C bus as a master only at 100-/400-KHz.SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3V, even if no I 2C device is connected.3.4BusesAll packages: 8- or 16-bit “FIFO” bidirectional data bus, multi-plexed on I/O ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus.Figure 3-1. Crystal Configuration12 pf12 pf24 MHz20 × PLLC1C212-pF capacitor values assumes a trace capacitanceof 3 pF per side on a four-layer FR4 PCANote:1.115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.3.5USB Boot MethodsDuring the power-up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0), or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2LP enumerates using internally stored descriptors. The default ID values for FX2LP are VID/PID/DID (0x04B4, 0x8613, 0xAxxx where xxx = Chip revision).[2]3.6ReNumeration™Because the FX2LP’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.When first plugged into USB, the FX2LP enumerates automat-ically and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumeration™, happens instantly when the device is plugged in, with no hint that the initial download step has occurred.Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0. Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device will handle device requests over endpoint zero: if RENUM = 0, the Default USB Device will handle device requests; if RENUM = 1, the firmware will.3.7Bus-powered ApplicationsThe FX2LP fully supports bus-powered designs by enumer-ating with less than 100 mA as required by the USB 2.0 speci-fication.3.8Interrupt System3.8.1INT2 Interrupt Request and Enable RegistersFX2LP implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual (TRM) for more details.3.8.2USB-Interrupt AutovectorsThe main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required to identify the individual USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a “jump” instruction to the USB Interrupt service routine.Table 3-1. Special Function Registersx8x9x Ax Bx Cx Dx Ex Fx 0IOA IOB IOC IOD SCON1PSW ACC B 1SP EXIF INT2CLR IOE SBUF12DPL0MPAGE INT4CLR OEA3DPH0OEB4DPL1OEC5DPH1OED6DPS OEE7PCON8TCON SCON0IE IP T2CON EICON EIE EIP 9TMOD SBUF0A TL0AUTOPTRH1EP2468STAT EP01STAT RCAP2LB TL1AUTOPTRL1EP24FIFOFLGS GPIFTRIG RCAP2HC TH0reserved EP68FIFOFLGS TL2D TH1AUTOPTRH2GPIFSGLDATH TH2E CKCON AUTOPTRL2GPIFSGLDATLXF reserved AUTOPTRSET-UP GPIFSGLDATLNOXTable 3-2. Default ID Values for FX2LPDefault VID/PID/DIDVendor ID0x04B4Cypress SemiconductorProduct ID0x8613EZ-USB FX2LPDevice release0xAnnn Depends on chip revision(nnn = chip revision where firstsilicon = 001)Note:2.The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.The FX2LP jump instruction is encoded as follows.If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will direct the jump to the correct address out of the 27 addresses within the page.3.8.3FIFO/GPIF Interrupt (INT4)Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table3-4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.Table 3-3. INT2 USB InterruptsUSB INTERRUPT TABLE FOR INT2 Priority INT2VEC Value Source Notes1 00SUDAV Set-up Data Available2 04 SOF Start of Frame (or microframe)3 08SUTOK Set-up Token Received4 0C SUSPEND USB Suspend request5 10USB RESET Bus reset6 14HISPEED Enteredhigh speed operation7 18 EP0ACK FX2LP ACK’d the CONTROL Handshake8 1C reserved9 20 EP0-IN EP0-IN ready to be loaded with data10 24 EP0-OUT EP0-OUT has USB data11 28 EP1-IN EP1-IN ready to be loaded with data12 2C EP1-OUT EP1-OUT has USB data13 30 EP2 IN: buffer available. OUT: buffer has data14 34 EP4 IN: buffer available. OUT: buffer has data15 38 EP6 IN: buffer available. OUT: buffer has data16 3C EP8 IN: buffer available. OUT: buffer has data17 40 IBN IN-Bulk-NAK (any IN endpoint)18 44reserved19 48 EP0PING EP0 OUT was Pinged and it NAK’d20 4C EP1PING EP1 OUT was Pinged and it NAK’d21 50 EP2PING EP2 OUT was Pinged and it NAK’d22 54 EP4PING EP4 OUT was Pinged and it NAK’d23 58 EP6PING EP6 OUT was Pinged and it NAK’d24 5C EP8PING EP8 OUT was Pinged and it NAK’d25 60 ERRLIMIT Bus errors exceeded the programmed limit26 6427 68 reserved28 6C reserved29 70 EP2ISOERR ISO EP2 OUT PID sequence error30 74 EP4ISOERR ISO EP4 OUT PID sequence error31 78 EP6ISOERR ISO EP6 OUT PID sequence error32 7C EP8ISOERR ISO EP8 OUT PID sequence errorIf Autovectoring is enabled (AV4EN = 1 in the INTSET-UP register), the FX 2LP substitutes its INT4VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte at 0x0055 will direct the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2LP pushes the program counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service routine.3.9Reset and Wakeup3.9.1Reset PinThe input pin, RESET#, will reset the FX2LP when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C680xxA the reset period must allow for the stabilization of the crystal and the PLL. This reset period should be approximately 5 ms after VCC has reached 3.0V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 µs after VCC has reached 3.0V[3]. Figure3-2 shows a power-on reset condition and a reset applied during operation. A power-on reset is defined as the time reset is asserted while power is being applied to the circuit. A powered reset is defined to be when the FX2LP has previously been powered on and operating and the RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation and can be found on the Cypress web site. For more information on reset imple-mentation for the FX2 family of products visit the .Table 3-4. Individual FIFO/GPIF Interrupt SourcesPriority INT4VEC Value Source Notes 180EP2PF Endpoint 2 Programmable Flag2 84 EP4PF Endpoint 4 Programmable Flag388EP6PF Endpoint 6 Programmable Flag48C EP8PF Endpoint 8 Programmable Flag590EP2EF Endpoint 2 Empty Flag694EP4EF Endpoint 4 Empty Flag798EP6EF Endpoint 6 Empty Flag89C EP8EF Endpoint 8 Empty Flag9A0 EP2FF Endpoint 2 Full Flag10A4EP4FF Endpoint 4 Full Flag11 A8EP6FF Endpoint 6 Full Flag12AC EP8FF Endpoint 8 Full Flag13 B0GPIFDONE GPIF Operation Complete14 B4GPIFWF GPIF WaveformNote:3.If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 µs.3.9.2Wakeup PinsThe 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscil-lator restarts, after the PLL stabilizes, and then the 8051receives a wakeup interrupt. This applies whether or not FX2LP is connected to the USB.The FX2LP exits the power-down (USB suspend) state using one of the following methods:•USB bus activity (if D+/D– lines are left floating, noise on these lines may indicate activity to the FX2LP and initiate a wakeup).•External logic asserts the WAKEUP pin •External logic asserts the PA3/WU2 pin.The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network to be used as a periodic wakeup source. Note that WAKEUP is by default active LOW.3.10Program/Data RAM3.10.1SizeThe FX2LP has 16 KBytes of internal program/data RAM,where PSEN#/RD# signals are internally ORed to allow the 8051 to access it as both program and data memory. No USB control registers appear in this space.Two memory maps are shown in the following diagrams:Figure 3-3 Internal Code Memory, EA = 0Figure 3-4 External Code Memory, EA = 1.3.10.2Internal Code Memory, EA = 0This mode implements the internal 16-KByte block of RAM (starting at 0) as combined code and data memory. When external RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This allows the user to connect a 64-KByte memory without requiring address decodes to keep clear of internal memory spaces.Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM spaces have the following access:•USB download •USB upload •Set-up data pointer •I 2C interface boot load.3.10.3External Code Memory, EA = 1The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as data memory.Figure 3-2. Reset Timing PlotsV IL 0V3.3V 3.0VT RESETVCCRESET#Power on ResetT RESETVCCRESET#V IL Powered Reset3.3V0VTable 3-5. Reset Timing ValuesConditionT RESET Power-on Reset with crystal 5 msPower-on Reset with external clock200 µs + Clock stability timePowered Reset 200 µsFigure 3-3. Internal Code Memory, EA = 0Inside FX2LPOutside FX2LP7.5 KBytes USB regs and 4K FIFO buffers (RD#,WR#)0.5 KBytes RAM Data (RD#,WR#)*(OK to populate data memory here—RD#/WR#strobes are not active)40 KBytes External Data Memory (RD#,WR#)(Ok to populate data memory here—RD#/WR#strobes are not active)16 KBytes RAM Code and Data(PSEN#,RD#,WR#)*48 KBytes External Code Memory (PSEN#)(OK to populate programmemory here—PSEN# strobe is not active)*SUDPTR, USB upload/download, I 2C interface boot accessFFFFE200E1FF E0003FFF0000DataCodeFigure 3-4. External Code Memory, EA = 1Inside FX2LPOutside FX2LP7.5 KBytes USB regs and 4K FIFO buffers (RD#,WR#)0.5 KBytes RAM Data (RD#,WR#)*(OK to populatedata memory here—RD#/WR#strobes are not active)40 KBytes External Data Memory (RD#,WR#)(Ok to populate data memory here—RD#/WR#strobes are not active)16 KBytes RAM Data(RD#,WR#)*64 KBytes External Code Memory (PSEN#)*SUDPTR, USB upload/download, I 2C interface boot accessFFFFE200E1FFE0003FFF0000DataCode3.11Register Addresses3.12Endpoint RAM3.12.1Size•3× 64 bytes (Endpoints 0 and 1)•8 × 512 bytes (Endpoints 2, 4, 6, 8)3.12.2Organization•EP0•Bidirectional endpoint zero, 64-byte buffer •EP1IN, EP1OUT•64-byte buffers, bulk or interrupt •EP2,4,6,8•Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4 and EP8 can be double buffered, while EP2 and 6 can be either double, triple, or quad buffered. For high-speed end-point configuration options, see Figure 3-5.3.12.3Set-up Data BufferA separate 8-byte buffer at 0xE6B8-0xE6BF holds the Set-up data from a CONTROL transfer.3.12.4Endpoint Configurations (High-speed Mode)Endpoints 0 and 1 are the same for every configuration.Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. When operating in full-speed BULK mode only the first 64 bytes of each buffer are used. For example in high-speed, the max packet size is 512 bytes but in full-speed it is 64 bytes. Even though a buffer is configured to be a 512byte buffer, in full-speed only the first 64 bytes are used. The unused endpoint buffer space is not available for other opera-tions. An example endpoint configuration would be:FFFFE800E7BF E740E73F E700E6FF E500E4FF E480E47F E400E200E1FFE000E3FF EFFF2 KBytes RESERVED64 Bytes EP0 IN/OUT 64 Bytes RESERVED 8051 Addressable RegistersReserved (128)128 bytes GPIF Waveforms512 bytes 8051 xdata RAMF000(512)Reserved (512)E78064 Bytes EP1OUT E77F 64 Bytes EP1IN E7FF E7C0 4 KBytes EP2-EP8buffers(8 x 512)EP2–1024 double buffered; EP6–512 quad buffered (column 8).3.12.5Default Full-Speed Alternate Settings3.12.6Default High-Speed Alternate Settings6464645125121024102410241024102410241024512512512512512512512512512512EP0 IN&OUTEP1 IN EP1 OUTFigure 3-5. Endpoint Configuration1024102410245125125125125125125125125125125125125125125125125125125125125125125125125125125125125125121024102410241024102410245125121024102451251251251251251251251210241024512512512512512512646464646464646464646464646464646464646464646464646464646464646464123456789101112Table 3-6. Default Full-Speed Alternate Settings [4, 5]Alternate Setting 0123ep064646464ep1out 064 bulk 64 int 64 int ep1in 064 bulk 64 int 64 int ep2064 bulk out (2×)64 int out (2×)64 iso out (2×)ep4064 bulk out (2×)64 bulk out (2×)64 bulk out (2×)ep6064 bulk in (2×)64 int in (2×)64 iso in (2×)ep8064 bulk in (2×)64 bulk in (2×)64 bulk in (2×)Notes:4.“0” means “not implemented.”5.“2×” means “double buffered.”6.Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.Table 3-7. Default High-Speed Alternate Settings [4, 5]Alternate Setting 0123ep064646464ep1out 0512 bulk [6]64 int 64 int ep1in 0512 bulk [6]64 int64 intep20512 bulk out (2×)512 int out (2×)512 iso out (2×)ep40512 bulk out (2×)512 bulk out (2×)512 bulk out (2×)ep60512 bulk in (2×)512 int in (2×)512 iso in (2×)ep80512 bulk in (2×)512 bulk in (2×)512 bulk in (2×)3.13External FIFO Interface3.13.1ArchitectureThe FX2LP slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic. The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally controlled transfers.3.13.2Master/Slave Control SignalsThe FX2LP endpoint FIFOS are implemented as eight physi-cally distinct 256x16 RAM blocks. The 8051/SIE can switch any of the RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between “USB FIFOS” and “Slave FIFOS.” Since they are physically the same memory, no bytes are actually transferred between buffers.At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dual-port in the 8051-I/O domain. The blocks can be configured as single, double, triple, or quad buffered as previ-ously shown.The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface.In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16-bit interface).In Slave (S) mode, the FX2LP accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. When using an external IFCLK, the external clock must be present before switching to the external clock with the IFCLKSRC bit. Each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#.3.13.3GPIF and FIFO Clock RatesAn 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alter-natively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register turns this clock output off, if desired. Another bit within the IFCONFIG register will invert the IFCLK signal whether internally or externally sourced. 3.14GPIFThe GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013A/15A to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia.The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and deter-mines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that will be executed to perform the desired data move between the FX2LP and the external device.3.14.1Six Control OUT SignalsThe 100- and 128-pin packages bring out all six Control Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define the CTL waveforms. The 56-pin package brings out three of these signals, CTL0–CTL2. CTLx waveform edges can be programmed to make transitions as fast as once per clock (20.8 ns using a 48-MHz clock).3.14.2Six Ready IN SignalsThe 100- and 128-pin packages bring out all six Ready inputs (RDY0–RDY5). The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. The 56-pin package brings out two of these signals, RDY0–1.3.14.3Nine GPIF Address OUT SignalsNine GPIF address lines are available in the 100- and 128-pin packages, GPIFADR[8..0]. The GPIF address lines allow indexing through up to a 512-byte block of RAM. If more address lines are needed, I/O port pins can be used.3.14.4Long Transfer ModeIn master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 232 transactions. The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction.。

CY7C68013的slave FIFO的读写速度(极限96MB)

Question:
How can the local transfer rate of 96 MB/s be achieved?
Response:
The burst rate of 96MB/s can be achieved by running the Slave FIFOs at 48 MHz (internal or external clock), while asserting SLWR or SLRD/SLOE for the entire data burst phase. Assuming active low polarity signals, when writing to the Slave FIFOs, SLWR should be held low as each word is clocked on the rising edge of IFCLK. The case is similar for reading from the Slave FIFOs; SLOE/SLRD should be held low as each new word is read on every rising edge of IFCLK.
Response:>
You won't find this anywhere in the FX2 TRM because it assumes a conservative approach (single-wait state access). However, it is possible to read or write a byte/word on every IFCLK edge while SLRD and SLWR remain asserted. This type of access gets you the highest achievable bandwidth over the physical interface (96MB/s).

【博文连载】CY7C68013同步FIFO配置

【博文连载】CY7C68013同步FIFO配置在VIP Mini开发板资料包08_USB_Keil_Project目录下，Bingo 提供了CY7C68013的同步FIFO配置工程，以及其他的一些功能。

软件版本为Keil UVision 4.73.00，C51V95200。

首先介绍一下68013的Slave FIFO，对于CY7C68013的通信接口而言，最主要的有GPIF 与Slave FIFO。

Slave FIFO模式是FX2最常用的模式。

芯片工作于Slave FIFO模式下，该芯片就像一个USB FIFO。

一端接USB口，另外一端就是一个简单的FIFO接口。

USB的数据直接从上位机传递到该FIFO中，用户可以直接用现成的驱动程序和固件程序进行开发，省去了很多熟悉USB协议和驱动开发的工作。

Slave FIFO通过内部的FIFO 乒乓操作，实现数据的实时传输，框图如下所示：在Slave FIFO模式，68013与处理器只需要如下一个信号的链接，通过简单的片选，写入/读取实现，别可以实现数据的双向通信。

全功能接口如下所示：USB_Camera_Demo工程如下所示，我们主要关心的为USB_Camera_Demo.c、intr.c，其他内容Bingo已经完整的整理封装好。

关于同步FIFO的配置，详见USB_Camera_Demo.c，这里给出最重要的几个寄存器的介绍，请同步参照《FX2+TechRefManual》《USB68013_slave_fifo说明文档》寄存器配置手册。

手册Page342如下图所示：其中EF为EMPTY标志，FF为FULL标志:备注：FLAGA = PF；FLAGB = FF；FLAGC = EF；FLAGD = EP2PF，默认由FIFOADDR选择。

USB控制芯片cy7c68013中文手册

■ 符合行业标准的集成增强型 8051 ❐ 48 MHz、 24 MHz 或 12 MHz CPU 操作 ❐ 每个指令周期四个时钟 ❐ 两个 USART ❐ 三个计数器/定时器 ❐ 扩展的中断系统 ❐ 两个数据指针
■ 3.3V 工作电压，容限输入为 5V
■ 向量化 USB 中断和 GPIF/FIFO 中断
■ 16 K 字节片上代码/数据 RAM
■ 四个可编程的 BULK/INTERRUPT/ISOCHRONOUS 端点 ❐ 缓冲区大小选项：两倍，三倍，四倍
■ 附加的可编程 (BULK/INTERRUPT) 64 位端点
■ 8 位或 16 位外部数据接口
■ 可生成智能介质标准错误校正码 ECC
■ 通用可编程接口 (General Programmable Interface， GPIF) ❐ 可与大多数并行接口直接连接 ❐ 由可编程波形描述符和配置寄存器定义波形 ❐ 支持多个 Ready (RDY) 输入和 Control (CTL) 输出
4 KB8/16源自FIFO丰富的 I/O 接口包含两个 USART
通用可编程 I/F 符合 ASIC/DSP 或总线标准，例如 ATAPI、 EPP 等
高达 96 MB/s 突发速率
增强型 USB 核简化 8051 代码
“软配置”容易进行固件更换
FIFO 和端点存储器（主控端或从属端操作）
1.1 特色（仅限 CY7C68013A/14A）
片上 PLL 可根据收发器 /PHY 的需要将 24 MHz 振荡器倍频到 480 MHz，而内部计数器可将其分频以用作 8051 时钟。默认的 8051 时钟频率是 12 MHz。 8051 的时钟频率可以由 8051 通过 CPUCS 寄存器动态更改。

USB芯片CY7C68013使用

CY7C68013芯片使用图一CY7C68013内部构造C Y7C68013特点：支持USB2.0，内部包括USB2.0收发器、串行接口引擎（SIE）以及增强型51内核；灵活配置，可“软配置”RAM，取代了传统51的RAM和ROM，程序可以通过以下方式下载：通过USB口下载；通过外部E2PROM装载；外界存储设备（仅128引脚支持）模式灵活，可设置为主从模式，主模式下可对外部FIFO、存储器、ATAn接口设备进行高速读写操作，从模式下外部主控器（例如DSP、MCU）可把GPIF端口当作FIFO进行高速读写操作。

支持与外设通过并行8位或者16位总线传输硬件连接方式在Slave FIFO方式下，外部逻辑与FX2的连接信号图如下：图一从模式下的硬件连接IFCLK：FX2输出的时钟，可做为通讯的同步时钟；FLAGA，FLAGB，FLAGC，FLAGD：FX2输出的FIFO状态信息，如满，空等；SLCS：FIFO的片选信号，外部逻辑控制，当SLCS输出高时，不可进行数据传输；SLOE：FIFO输出使能，外部逻辑控制，当SLOE无效时，数据线不输出有效数据；SLRD：FIFO读信号，外部逻辑控制，同步读时，FIFO指针在SLRD有效时的每个IFCLK 的上升沿递增，异步读时，FIFO读指针在SLRD的每个有效—无效的跳变沿时递增；SLWR：FIFO写信号，外部逻辑控制，同步写时，在SLWR有效时的每个IFCLK的上升沿时数据被写入，FIFO指针递增，异步写时，在SLWR的每个有效—无效的跳变沿时数据被写入，FIFO写指针递增；PKTEND：包结束信号，外部逻辑控制，在正常情况下，外部逻辑向FX2的FIFO中写数，当写入FIFO端点的字节数等于FX2固件设定的包大小时，数据将自动被打成一包进行传输，但有时外部逻辑可能需要传输一个字节数小于FX2固件设定的包大小的包，这时，它只需在写入一定数目的字节后，声明此信号，此时FX2硬件不管外部逻辑写入了多少字节，都自动将之打成一包进行传输；FD[15:0]：数据线；FIFOADR[1:0]：选择四个FIFO端点的地址线，外部逻辑控制。

CY7C68013A固件函数说明

CY7C68013A固件函数说明Anchor EZ-USB Firmware LibraryThe EZ-USB Firmware Library is provided to accelerate USB peripheral development. The library provides constants, data structures, macros, and functions that simplify the use of common EZ-USB resources. The user simply includes the EZUSB.H and EZREGS.H header files in their source and links the EZUSB.LIB library file with the resulting binary.The FilesThe header file EZUSB.H is located in the ..\examples\inc directory. It contains constant definitions, macro definitions, data structures, global variable declarations, and function prototypes for the EZ-USB library.The header file EZREGS.H is located in the ..\examples\inc directory. It contains bit mask definitions, and EZ-USB register variable declarations.The library object file EZUSB.LIB is located in the ..\examples\lib directory. It contains the binary for the EZ-USB library functions. The source files for EZUSB.LIB are also located in ..\examples\lib.The object file USBJMPTB.OBJ is located in the ..\examples\lib directory. It contains the interrupt vector and the jump table for the EZ-USB USB interrupt. If this object file is linked with your project, enable autovectoring prior to enabling interrupts. The function names called by the jump table can be found in the source file USBJMPTB.A51.Functionsvoid EZUSB_Discon(BOOL renum)Description: This function performs a USB disconnect. Itdisconnects the device, delays for 500ms, and returns. The parameter renum determines if the EZ-USB re-numerate bit is set in the USBcontrol register. If renum is TRUE, the re-numerate bit is set and following a return fromthis function the 8051 will be responsible for handling all USB device requests on endpoint 0.If renum is FALSE, the re-numerate bit is not modified. If the re-numerate bit is clear thenthe EZ-USB serial interface engine handles most of the USB device requests on endpoint 0. void EZUSB_Susp(void) Description: This function suspends the processor in response to a USB suspend event. This function will not return until the suspend has been cleared by a USB bus resume or a wake-up event on theEZ-USB wake-up pin. If a suspend event is not pending, this function will returnimmediately.void EZUSB_Resume(void)Description: This function generates the K-state on the USB bus required for a USB device remote wake-up. This function should be called following a USB suspend. It automatically determines ifthe wake-up was result of a USB resume or a remote wake-up, and generates the K-stateaccordingly.void EZUSB_Delay1ms(void)Description: This function implements a busy loop that takes 1 millisecond to complete and then returns. void EZUSB_Delay(WORD ms)Description: This function performs a busy wait for a given number of milliseconds. The parameter ms determines the length of the busy wait. Upon completion of the delay the function returns. CONFIGDSCR*EZUSB_GetConfigDscr(BYTE ConfigInst) Description: This function returns a pointer to the n th instance of a configuration descriptor in the descriptor table. The instance is determined by the ConfigInst parameter. If the descriptor table does not contain the given number of instances then the function returns aNULL pointer.INTRFCDSCR*EZUSB_GetIntrfcDscr(BYTE ConfigIdx, BYTE IntrfcIdx, BYTE AltSetting)Description: This function returns a pointer to a given interface descriptor found in the givenconfiguration/alternate setting. The parameters ConfigIdx, IntrfcIdx, andAltSetting specify the interface. If the descriptor table does not contain the giveninterface then the function returns a NULL pointer.STRINGDSCR*EZUSB_GetStringDscr(BYTE StrInst)Description: This function returns a pointer to the n th instance of a string descriptor in the descriptor table.The instance is determined by the StrInst parameter. If the descriptor table does notcontain the given number of instances then the function returns a NULL pointer.void EZUSB_InitI2C(void)Description: This function initializes the EZ-USB i2c interface. It must be called once before calling EZUSB_WriteI2C() or EZUSB_ReadI2C().BOOL EZUSB_WriteI2C(BYTE addr, BYTE length, BYTE xdata *dat)Description: This function writes a string of data to the EZ-USB i2c interface. The parameter addr specifies the i2c device address. The parameters length and *dat specify the data to be sent and its length. This function returns immediately before all of the provided data is sent(the i2c library code is interrupt driven). If data is currently being sent or received at the timeof this function call it will return FALSE, and the data will not be sent. Else if the i2c port isnot busy then the data is queued up and the function returns TRUE.BOOL EZUSB_ReadI2C(BYTE addr, BYTE length, BYTE xdata *dat)Description: This function read a string of data from the EZ-USB i2c interface. The parameter addr specifies the i2c device address. The parameters length and *dat specify the buffer into which the data will be copied and its length. This function returns immediately, before all ofthe requested data is read into the buffer. The user must poll the i2c status to determine whenthe data is available. If data is currently being sent or received at the time of this function callit will return FALSE, and the data will not be read. Else if the i2c port is not busy then theread is queued up and the function returns TRUE.Global Variablescode DEVICEDSCR DeviceDscrDescription: This global is used by the descriptor tableparsing functions. It points to the head of the device descriptor table. For a complete description of the descriptor table, see the FrameWorks documentation.code CONFIGDSCR ConfigDscrDescription: This global is used by the descriptor table parsing functions. It points to the first configuration descriptor. For a complete description of the descriptor table, see the FrameWorks documentation.code STRINGDSCR StringDscrDescription: This global is used by the descriptor table parsing functions. It points to the first string descriptor. For a complete description of the descriptor table, see the FrameWorks documentation.code DSCR UserDscrDescription: This global is used by the descriptor table parsing functions. It points to the first user descriptor. For a complete description of the descriptor table, see the FrameWorks documentation.struct I2CPCKT I2CPcktDescription: This global is used by the i2c interface functions. It stores the current status of the i2c interface.。

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红色飓风II开发板USB2FPGA实验指导（ver1.0）Red Logic工作室二〇〇六年四月三日目录第一章FX2特性介绍 (3)1．1介绍 (3)1．2结构 (3)1．3特征 (4)第二章Slave FIFO传输 (5)2．1概述 (5)2．2硬件连接 (5)2．3 Slave FIFO的几种传输方式 (6)2．3．1 同步Slave FIFO写 (6)2．3．2 同步Slave FIFO读 (9)2．3．3异步Slave FIFO写 (11)2．3．4异步Slave FIFO读 (12)第三章寄存器设置 (15)3．1 IFCONFIG (15)3．2 PINFLAGSAB/CD (16)3．3 FIFORESET (17)3．4 FIFOPINPOLAR (18)3．5 EPxCFG (18)3．6 EPxFIFOCFG (19)3．7 EPxAUTOINLENH/L (20)3．8 EPxFIFOPFH/L (21)3．9 INPKTEND (22)3．10 OUTPKTEND (22)3．11 EPxFIFOIE和EPxFIFOIRQ (22)3．12PORTACFG (23)3．13 EPxFIFOBCH EPxFIFOBCL (23)3．14 EP24\68FIFOFLAG (24)3．15其它通用寄存器 (25)第四章同步slave fifo测试操作指南 (26)4．1安装软件包 (26)4．2同步写FIFO测试 (26)4．3同步读FIFO测试 (30)4．4同步读写FIFO测试 (31)第五章红色飓风II开发板USB2FPGA软件设计 (33)5．1 68013固件程序设计 (33)5．2 FPGA源代码设计 (35)第六章USB2FPGA硬件原理图 (37)第七章改板后注意的问题 (37)附录1 版本历史 (39)一．FX2特性介绍1．1介绍Cypress Semiconductor公司的EZ－USB FX2是世界上第一款集成USB2.0的微处理器，它集成了USB2.0收发器、SIE（串行接口引擎）、增强的8051微控制器和可编程的外围接口。

FX2这种独创性结构可使数据传输率达到56Mbytes/s，即USB2.0允许的最大带宽。

在FX2中，智能SIE可以硬件处理许多USB1.1和USB2.0协议，从而减少了开发时间和确保了USB的兼容性。

GPIF（General Programmable Interface）和主/从端点FIFO（8位或16位数据总线）为ATA、UTOPIA、EPP、PCMCIA和DSP等提供了简单和无缝连接接口。

1．2结构CY7C68013结构图如图1所示。

它有三种封装形式：56SSOP，100TQFP和128TQFP。

1．3特征：★内嵌480MBit/s的收发器，锁相环PLL，串行接口引擎SIE——集成了整个USB 2.0协议的物理层。

★为适应USB 2.0的480MBit/s的速率，FIFO端点可配置成2，3，4个缓冲区。

★内嵌可工作在48MHz的增强型8051，它具有以下特征：- 具有256Byte的寄存器空间，两个串口，三个定时器，两个数据指针。

- 四个机器周期（工作在48MHz下时为83.3ns）即组成一个指令周期。

- 特殊功能寄存器（包括I/O口控制寄存器）可高速访问。

- 应用USB向量中断，具有极短的ISR响应时间。

- 只用作USB事务管理，控制，不参与数据传输，较好地解决了USB高速模式的带宽问题。

★“软配置”——USB固件可由USB总线下载，片上不需集成ROM。

★拥有四个FIFO接口，可工作在内部或外部时钟下。

端点和FIFO接口的应用使外部逻辑和USB总线可高速连接。

★内嵌通用可编程接口GPIF，它是一个状态机，可充当主控制器，提供外部逻辑和USB总线的“无胶粘贴”。

★一种单片USB 2.0外设解决方案，不需要外部的协议物理层，FX2把所有的功能集成在一个芯片上。

二、Slave FIFO 传输2．1概述当有一个与FX2芯片相连的外部逻辑只需要利用FX2做为一个USB 2.0接口而实现与主机的高速通讯，而它本身又能够提供满足Slave FIFO 要求的传输时序，可以做为Slave FIFO 主控制器时，即可考虑用此传输方式。

Slave FIFO 传输的示意图如下：在这种方式下，FX2内嵌的8051固件的功能只是配置Slave FIFO 相关的寄存器以及控制FX2何时工作在Slave FIFO 模式下。

一旦8051固件将相关的寄存器配置完毕，且使自身工作在Slave FIFO 模式下后，外部逻辑（如FPGA ）即可按照Slave FIFO 的传输时序，高速与主机进行通讯，而在通讯过程中不需要8051固件的参与。

2．2硬件连接(标准)在Slave FIFO 方式下，外部逻辑与FX2的连接信号图如下：IFCLK：FX2输出的时钟，可做为通讯的同步时钟；FLAGA，FLAGB，FLAGC，FLAGD：FX2输出的FIFO状态信息，如满，空等；SLCS：FIFO的片选信号，外部逻辑控制，当SLCS输出高时，不可进行数据传输；SLOE：FIFO输出使能，外部逻辑控制，当SLOE无效时，数据线不输出有效数据；SLRD：FIFO读信号，外部逻辑控制，同步读时，FIFO指针在SLRD有效时的每个IFCLK 的上升沿递增，异步读时，FIFO读指针在SLRD的每个有效—无效的跳变沿时递增；SLWR：FIFO写信号，外部逻辑控制，同步写时，在SLWR有效时的每个IFCLK的上升沿时数据被写入，FIFO指针递增，异步写时，在SLWR的每个有效—无效的跳变沿时数据被写入，FIFO写指针递增；PKTEND：包结束信号，外部逻辑控制，在正常情况下，外部逻辑向FX2的FIFO中写数，当写入FIFO端点的字节数等于FX2固件设定的包大小时，数据将自动被打成一包进行传输，但有时外部逻辑可能需要传输一个字节数小于FX2固件设定的包大小的包，这时，它只需在写入一定数目的字节后，声明此信号，此时FX2硬件不管外部逻辑写入了多少字节，都自动将之打成一包进行传输；FD[15:0]：数据线；FIFOADR[1:0]：选择四个FIFO端点的地址线，外部逻辑控制。

2．3 Slave FIFO的几种传输方式2．3．1 同步Slave FIFO写同步Slave FIFO写的标准连接图如下：同步Slave FIFO写的标准时序如下：IDLE：当写事件发生时，进状态1；状态1：使FIFOADR[1:0]指向IN FIFO，进状态2；状态2：如FIFO满，在本状态等待，否则进状态3；状态3：驱动数据到数据线上，使SLWR有效，持续一个IFCLK周期，进状态4；状态4：如需传输更多的数，进状态2，否则进状态IDLE。

状态跳转示意图如下：几种情况的时序图示意如下（FULL，EMPTY，SLWR，PKTEND均假定低有效）：图示FIFO中本来没有数据，外部逻辑写入第一个数据时的情况。

图示假定FX2设定包大小为512字节，外部逻辑向FIFO端点中写入的数据达512字节时的情况。

此时FX2硬件自动将已写入的512字节打成一包准备进行传输，这个动作就和在普通传输中，FX2固件向FIFO端点中写入512字节后，把512这个数写入EPxBC中一样，只不过这个过程是由硬件自动完成的。

在这里可以看出“FX2固件不参与数据传输过程”的含义了。

外部逻辑只须按上面的时序图所示的时序向FIFO端点中一个一个字节（或字）地写数，写到一定数量，FX2硬件自动将数据打包传输，这一切均不需固件的参与，由此实现高速数据传输。

图示的是FIFO端点被写满时的情况。

2．3．2 同步Slave FIFO读：同步Slave FIFO读的标准连接图如下：同步Slave FIFO读的标准时序如下：IDLE：当读事件发生时，进状态1；状态1：使FIFOADR[1:0]指向OUT FIFO，进状态2；状态2：使SLOE有效，如FIFO空，在本状态等待，否则进状态3；状态3：从数据线上读数，使SLRD有效，持续一个IFCLK周期，以递增FIFO读指针，进状态4；状态4：如需传输更多的数，进状态2，否则进状态IDLE。

状态跳转示意图如下：几种情况的时序图示意如下（FULL，EMPTY，SLRD，SLOE均假定低有效）：图示正常情况时的时序。

图示FIFO被读空时的情况。

2．3．3 异步Slave FIFO写：异步Slave FIFO写的标准连接图如下：异步Slave FIFO写的标准时序如下：IDLE：当写事件发生时，进状态1；状态1：使FIFOADR[1:0]指向IN FIFO，进状态2；状态2：如FIFO满，在本状态等待，否则进状态3；状态3：驱动数据到数据线上，使SLWR有效，再无效，以使FIFO写指针递增，进状态4；状态4：如需传输更多的数，进状态2，否则进状态IDLE。

2．3．4 异步Slave FIFO读：异步Slave FIFO读的标准连接图如下：异步Slave FIFO读的标准时序如下：IDLE：当读事件发生时，进状态1；状态1：使FIFOADR[1:0]指向OUT FIFO，进状态2；状态2：如FIFO空，在本状态等待，否则进状态3；状态3：使SLOE有效，使SLRD有效，从数据线上读数，再使SLRD无效，，以递增FIFO读指针，再使SLOE无效，进状态4；状态4：如需传输更多的数，进状态2，否则进状态IDLE。

状态跳转示意图如下：几种情况的时序图示意如下（FULL，EMPTY，SLRD，SLOE均假定低有效）：图示正常情况时的时序。

三、寄存器设置slave fifo模式下常用寄存器IFCONFIG EPxFIFOPFH/LPINFLAGAB PORTACFGPINFLAGCK INPKTENDFIFORESET EPxFLAGIEFIFOPINPOLAR EPxFLAGIRQEPxCFG EPxFIFOBCH:LEPxFIFOCFG EPxFLAGSEPxAUTOINLENH:L EPxBUF3．1 IFCONFIG（E601）：接口配置寄存器IFCLKSRC：FIFO时钟内部/外部时钟源选择，0外部时钟源，1内部时钟源。

3048MHZ：如选择内部时钟，30MHz/48MHz频率选择，0 IFCLK时钟30M，1 IFCLK 时钟48M。

IFCLKOE：IFCLK时钟输出使能，0关闭，1打开。

IFCLKPOL：IFCLK输出反转使能，0不反转，1反转。