非常经典清华大学李宇根 PLL讲义

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清华大学电子电路与系统基础(2)第一讲

• 鼓励参加
– 一些思路的探讨，对理论课的加强
李国林电子电路与系统基础清华大学电子工程系 2016年秋季学期 3
运算放大器大纲
• 运算放大器及其外端口特性
• 理想运算放大器特性
• 负反馈线性应用
– 四种负反馈放大器 – 其他…
• 非线性应用
– 开环 – 闭环
• 负反馈 • 正反馈
李国林电子电路与系统基础
二阶模型的解
Rout R2 Rin

R2 R1 1
一阶模型的解
Av 0
Rin , Rout 0
Av 0 1
理想模型的解 R2 Rin , Rout 0 R1 Av 0 仅和外接电阻有关，和运放无关 20 这是我们希望的：随便换个运放，得到相同的结果
vid
O
vip
二端口网络描述方程
vid
vout Vsat
vid vin
负饱和区等效电路
李国林电子电路与系统基础
Vsat
iid 0 vout Vsat
vid
Vsat
10
二端口网络描述方程
清华大学电子工程系 2016年秋季学期
线性区外端口特性等效电路
vn1
1 vout Av 0
vout
舍入误差 vn1 0.0001 vin v out 9.9994
李国林电子电路与系统基础
R2 R1
R 1 vin 2 vin 10vin R1 1 R2 1 1 公式变得极度简单 Av 0 R 1
– 助教联系方式和作业批改班级分配情况见网络学堂
李国林电子电路与系统基础清华大学电子工程系 2016年秋季学期 2

清华大学微积分B2讲义week2

y
时, 将y看作常数, 对变量x求导
u yx y 1 sin( x y) x y cos( x y). x
同理有
u x y (ln x)sin( x y) x y cos( x y). y
例2:
三元函数
ue
x z
sin( x y).
u 解： e x z sin( x y) e x z cos( x y); x u u x z e cos( x y ); e x z sin( x y ). y z
2 y 2 x 的例6： f ( x, y) x 4 y 求f 在 (1,2) 沿
2
2
切向量的方向导数.
2 y 2 x , 解：
y 4 x.
在 (1,2) 切向量
数学名家介绍 (一)
莱布尼茨 (Leibniz, Gottfried Wilhelm, 1646.7.11716.11.14)德国数学家、物理学家和哲学家等数理逻辑的创始人 .生于莱比锡，卒于汉诺威 .1661年入莱比锡大学学习法律，又曾到耶拿大学学习几何 .1666 年获法学博士学位 .1673 年当选为英国皇家学会会员 .1676 年任汉诺威图书馆馆长 .1700 年当选为巴黎科学院院士，促成组建了柏林科学院并任首任院长 . 他的研究领域涉及到逻辑学、数学、力学、地质学、法学、历史学、语言学、生物学以及外交、神学等诸多方面 .他与牛顿并称为微积分的创立者 .他系统阐述了二进制计数法，并把它和中国的八卦联系起来 . 在哲学方面，著有《单子论》，内含辩证法的因素.
0
开区域内连续函数：设D是开区域.若函数 f
在D的每个点上都连续，则称 f 在D内连续. 闭区域上连续函数：设D是闭区域. 若函数 f 在D的每个内点上都连续, 且对于D的每个边界

清华大学量子力学讲义Lecture10

x(t ) 的贡献之和，
i S [ x ( t )]
每条路径对几率幅的贡献＝Const e
，
)dt ，作用量 S [ x(t )] Lc ( x, x
t1
tN
经典作用量 Lc
1 2 V (x )， mx 2
xN i
tN t1
K ( xN , t N ; x1 , t1 ) c [dx(t )]e
2）跃迁振幅 ˆ (t , t ) x U ' 将 t0 时的坐标本征态 x ' 演化到 t 时刻，传播子 0 ˆ K ( x ", t ; x ', t0 ) x " U (t , t0 ) x '
可看成是从坐标本征态 x ' 经时间 t t0 后跃迁到另一坐标本征态 x " 的振幅。
V mgl2 sin 。
4
虽然粒子在 AB 和 CD 部分相比于 AC 部分也有势差，而且与空间位置有关，但对两条路径的势差来说抵销了，无贡献。设粒子从 B 到 D 的时间是 T，则粒子经过两条路径的势差导致在 D 处产生相位差
ABD ACD
m gl2T sin ，

0

0
显然是 t0 时的坐标本征态 x ', t0 跃迁到 t 时刻的坐标本征态 x ", t 的振幅。
由完备性条件，
d
3
x x, t x, t 1 ，
K ( x3 , t3 ; x1 , t1 ) x3 , t3 x1 , t1 d 3 x2 x3 , t3 x2 , t2 x2 , t2 x1 , t1 d 3 x2 K ( x3 , t3 ; x2 , t2 ) K ( x2 , t2 ; x1 , t1 ),

清华大学断裂力学讲义线弹性断裂力学共37页

清华大学断裂力学讲义线弹性断裂力学
51、没有哪个社会可以制订一部永远适用的宪法，甚至一条永远适用的法律。 ——杰斐逊 52、法律源于人的自卫本能。——英格索尔
53、人们通常会发现，法律就是这样一种的网，触犯法律的人，小的可以穿网而过，大的可以破网而出，只有中等的才会坠入网中。 ——申斯通 54、法律就是法律它是一座雄伟的大夏，庇护着我们大家；它的每一块砖石都垒在另一块砖石上。 ——高尔斯华绥 55、今天的法律未必明天、天下之事常成于困约，而败于奢靡。——陆游 52、生命不等于是呼吸，生命是活动。——卢梭
53、伟大的事业，需要决心，能力，组织和责任感。 ——易卜生 54、唯书籍不朽。——乔特
55、为中华之崛起而读书。 ——周恩来

清华PLL讲义

Æ Simply speaking, we will learn where to, when to, and how to use PLL for various applications.
5
W. Rhee, Institute of Microelectronics, Tsinghua University
8
W. Rhee, Institute of Microelectronics, Tsinghua University
I. Overview of Clocking and Frequency Generation
10
W. Rhee, Institute of Microelectronics, Tsinghua University
3
W. Rhee, Institute of Microelectronics, Tsinghua University
Course Assessment
• Homework: • Midterm exam: • Final exam: • Term project:
10% 20% 30% 40%
PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 1)
Woogeun Rhee Institute of Microelectronics Tsinghua University
PLL Design and Clock/Frequency Generation (PLL设计与时钟/频率产生)
Course Outline – First Half
I. Overview of Clocking and Frequency Generation 1. Course introduction 2. Phase-locked clocking in modern communication systems II. Phase-Lock Basics 1. PLL linear model 2. Loop components 3. Loop dynamics 4. Transient response and acquisition 5. PLL behavioral simulations III. PLL Design 1. System design perspectives - spur and modulation - phase noise/jitter - settling time - bandwidth optimization 2. Circuit design aspects - phase detector - charge pump - frequency divider - voltage-controlled oscillator 3. Delay-locked loop (Midterm Examination)

清华大学中级微观经济学讲义(清华李稻葵)30

The Endowment Allocation
2 OB 2 6 4 OA 6 8
ω = (2,2)
B
The Endowment Allocation
2 OB 2 6 4 OA 6 8 The endowment allocation
A ω = (6,4) B
ω = (2,2)
The Endowment Allocation
/ Remarks on the Final
Final Examination: 1. Final exam is comprehensive. 2. It mainly covers the material after midterm. 3. The materials before midterm are important in two ways: 1) some problems may directly come from those chapters. 2) the materials before midterm provide a foundation for new materials. The format of the final will be the same as that in the midterm. Office Hour: 4-5 pm Thursday
Starting an Edgeworth Box
Height = A B ω2 + ω2
= 4+ 2 =6
The dimensions of the box are the quantities available of the goods.
A B ω1 + ω1 = 6 + 2 = 8 Width =

非常经典清华大学李宇根 PLL讲义 Lecture12

Spring Semester, 2008PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 12)Woogeun Rhee Institute of Microelectronics Tsinghua UniversityTerm Project• Design 645MHz fractional-N PLL circuit: - fref = 40MHz, fout = 645MHz with 50% duty cycle - Due date: June 24th40MHzfref(1) (2)645MHzPFD(3)CP(4)VCO(5)2(6)foutPLL BW: ~500kHz16/17 k-bit ACCUM2W. Rhee, Institute of Microelectronics, Tsinghua UniversityTerm Project (continued)• Do followings: 1. Design loop filter for ~500kHz PLL bandwidth. 2. Draw open-loop gain Bode plot based on LPF design from (a). 3. Plot node 3, 4 and check the lock time. 4. Plot node 1, 2 after PLL is fully settled. What is the amount of static phase offset? 5. Plot node 5, 6 for 10 VCO cycles (i.e. zoom-in plot). 6. Estimate the spur level based on VCO gain and waveform at node 3. 7. Verify (f) result by having FFT and measure spur level at VCO output in dBc. E1. Plot eye diagram of VCO output and measure jitter in time domain. (extra) E2. Run phase noise simulation of open-loop VCO and calculate closed-loop RJ. (extra) E3. Calculate closed-loop RJ by defining approximated noise bandwidth. (extra) E4. Tell whether DJ or RJ is dominant. (extra) • Note: Ideal blocks allowed for PFD & LPF design3W. Rhee, Institute of Microelectronics, Tsinghua UniversityV. Applications 3. Clock Multiplier Unit (CMU)4W. Rhee, Institute of Microelectronics, Tsinghua UniversityCMU Design Considerations• Similar to RF frequency synthesizer - Use of frequency divider and PFD/CP - Trade-off between noise and spur • Different from RF frequency synthesizer - Less stringent lock-in time - Ultimately interested in pk-pk jitter. - Noisier supply voltage - Noisier reference clock - Lower supply voltage - Mostly in digital CMOS process - Ring VCO and on-chip LPF preferred.5W. Rhee, Institute of Microelectronics, Tsinghua UniversityJitter• Absolute jitter (long-term jitter) - Phase error w.r.t. ideal referenceΔTabs ,rms = lim1 2 ΔT12 + ΔT22 + ⋅ ⋅ ⋅ + ΔTN N →∞ N• Cycle-to-cycle jitter (short-term jitter) - No need for referenceΔTcc ,rms ≈ lim1 (T2 − T1 )2 + (T3 − T2 )2 + ⋅ ⋅ ⋅ + (TN − TN −1 )2 N →∞ N• Period jitter - For PLL, period jitter = absolute jitter.ΔTp ,rms = lim1 (T − T1 )2 + (T − T2 )2 + ⋅ ⋅ ⋅ + (T − TN −1 )2 N →∞ N*Note:Periodic jitter (PJ) is often considered DJ by sinusoidal modulation, which is different from period jitter.W. Rhee, Institute of Microelectronics, Tsinghua University6Total Jitter (TJ)RJpk-pk (14*σ)• Total jitter (TJpp) - RJpp + DJpp = 14 x RJrms + DJpp • Random jitter (RJ) - Non-systematic jitter - Gaussian distribution • Deterministic jitter (DJ) - Systematic jitter - Coupling and ISI - Duty cycle distortionDJDJ dominant (modulation)RJ dominant (noise)Pspurfo7W. Rhee, Institute of Microelectronics, Tsinghua UniversityRandom Jitter (RJ)Bathtub Curve• For BER = 10-12, RJpp = 14 x RJrmsRef: “Jitter Fundamentals,” Wavecrest Company8W. Rhee, Institute of Microelectronics, Tsinghua UniversityRJ and Noise Integration BandwidthfoCDR tracking BWPDLPFCDRN• CDR tracking BW should be considered for TXPLL design. - SONET: 50kHz – 80MHz - Typically (Baud Rate) / 1667 – (Baud Rate) / 29W. Rhee, Institute of Microelectronics, Tsinghua UniversitySupply Noise EffectfoCDR tracking BWPDLPFCDRN10W. Rhee, Institute of Microelectronics, Tsinghua UniversityJSSC’96, von Kaenel et al. Supply Noise ConsiderationSupply w/o NoiseSupply w/t Noise(f 3dBLess power but needs more careful design for 50% duty cycle.Cascaded PLLsParallel PLLsISSCC’03, Wong et al.Cascaded PLLsV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionInside PCCurrent ComingFB-DIMM•DDR2 DRAM + high-speed serial linkÆPoint-to-point serial link communication •Overcomes trade-off between speed and capacity.[Li, ITC’04], [PCI-SIG]s o 123H s H s e H s H s −Δτ=−⋅()[()()]()H 1(s)H 3(s)H 2(s)ΔτLC VCORing VCO[Noguchi, ISSCC’02][Herzel, JSSC’03][Moon, JSSC’04][Williams, CICC’04]Dual-Path VCOsTimeTimeVarious Coarse-Tuning Gains(with BW FINE = 1)Various Coarse-Tuning Bandwidths(with BW FINE = 1)(CppSim tool from M.I.T. used for simulation)PLL Behavioral Simulation(<80kHz)(10MHz)VDDINBINBIASOUT OUTBR1R2Narrowbanding (for coarse tuning)4th -pole of PLL (for fine tuning)Resistor noise contribution to PLLH(f)fF RCF BWLinear Amplifier and Noise ConsiderationPhase Noise PerformancesMeasured RJ VariationMeasured VCO Tuning CurvePSRR PerformanceV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionFractional-N PLL for Wireline Applications?Flexible Frequency Planning with ΔΣPLL•Conventional PLL makes it difficult to accommodate various reference clock frequencies.Digital Clock Generation with <1ppm Resolution•PLL with ring VCO needs wide bandwidth to suppress VCO noise.ÆLow f ref /f bw ratio makes it difficult to implement ΔΣfractional-N PLL.ÆSuffer from cycle-to-cycle jitter problem due to quantization noise.Fractional-N PLL for Digital SystemL f ) d B c /H z )Basic ConceptsEquivalent Discrete-Time Model Frequency ResponseL ) B c H zBehavioral Simulation Results500MHz Output Spectrum(Fref= 14.318MHz, N=37.15603)VCO Control Voltage•FIR-embedded frequency divider reduces output cycle-to-cycle jitter.ISCAS’07, Chi et al.Measured Output SpectraV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionElectromagnetic Interference (EMI)•Radiation emission is strictly regulated by FCC.•Can be reduced by shielded cables but expensive and bulky.ÆHow about modulating clock to reduce peak power?Modulation Profile Clock SpectrumCarrier(w/o modulation)Spread Spectrum ClockingJSSC’03, Chang et al.By Voltage ModulationBy Divider Modulation By ΔΣModulation ISSCC’99, Li et al.ISSCC’05, Lee et al.。

清华电子系李老师计算机硬件技术基础Chap3_l42

例
data1 data2
DB 12, 34, 56 DB 12H, 34H, 56H
；十进制；十六进制；字符；字符串
MOV AL, ‘G’ string DB ‘1234’
15
A、B、C、D、E、F开头的十六进制数前面加，、、、、、开头的十六进制数前面加开头的十六进制数前面加0，结尾的标识符区别。与H结尾的标识符区别。结尾的标识符区别寄存器名AH、BH、CH、 DH 如寄存器名、、、变量名 abcdH 等
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名字] 名字 [名字 [: ]
助记符
操作数, [ 操作数
]
；注释] [；注释
名字项
助记符项
操作数项
注释项
名字项用一个符号表示。名字项用一个符号表示。对符号的规定: 对符号的规定由字符A~Z ，a~z ，0~9及符号、$、下划线等组成，及符号@、、下划线_ 等组成， ① 由字符及符号最长31个字符，超出部分忽略。最长个字符，超出部分忽略。个字符不能用数字打头，以免与十六进制数相混。 ② 不能用数字打头，以免与十六进制数相混。不使用汇编程序中的保留字。如指令的助记符等如指令的助记符等) ③ 不使用汇编程序中的保留字。 (如指令的助记符等对定义的符号不区分大小写。 ④ 对定义的符号不区分大小写。
例
mov AL, 0AH mov AL, AH mov BX, 0abcdH
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名字] 名字 [名字 [: ]
助记符
操作数, [ 操作数
]
；注释] [；注释
名字项
助记符项
操作数项
注释项
4．注释项．
由分号引出，用来说明语句或程序的功能。由分号引出，用来说明语句或程序的功能。汇编程序对分号后的内容不做处理。汇编程序对分号后的内容不做处理。作用：作用： ①注释程序，增强程序可读性。注释程序，增强程序可读性。 ②可放在语句最前，暂时注释某语句，调试程序用。可放在语句最前，暂时注释某语句，调试程序用。

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Spring Semester, 2008PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 14)Woogeun Rhee Institute of Microelectronics Tsinghua UniversityFinal Examination• Date & time: June 24th (7:15pm – 9:00pm) • Place: 6B204 (Lecture room) • You can bring one A4 sheet with formula or anything written. Must be hand-written!! • Using calculator is allowed (maybe not necessary).2W. Rhee, Institute of Microelectronics, Tsinghua UniversityV. Advanced Topics 1. Coupling3W. Rhee, Institute of Microelectronics, Tsinghua UniversityCoupling Effect on Clock JitterJSSC’96, von Kaenel et al.Without Supply NoiseSiRF’06, Jenkins et al.With Supply Noise4W. Rhee, Institute of Microelectronics, Tsinghua UniversityReview: Effect of External Noise CouplingIdeal Oscillator With Good Isolation With Coupling• Coupling within fo/(2Q) will be increased by fo/(2Qfm) - Just behaviors like circuit noise!! • Interference coupling near Fout can be reduced only by isolation.5W. Rhee, Institute of Microelectronics, Tsinghua UniversityCoupling Mechanism• Substrate noise • Supply noise • Ground bouncing • Crosstalk6W. Rhee, Institute of Microelectronics, Tsinghua UniversitySubstrate Noise in SoC“Substrate noise coupling is still one of the least understood phenomena in mixed signal/RF SoC designs”<ISSCC04, Pelgrom>7W. Rhee, Institute of Microelectronics, Tsinghua UniversityLiving with Substrate Noise• Use known physical isolation methods. Develop rules of thumb for layout. • Simulate noise effect during floor planning or layout. Requires sophisticated and accurate software.8W. Rhee, Institute of Microelectronics, Tsinghua UniversitySubstrate Noise Coupling Mechanism(possible noise) nFETp+ n n nnFETnwiring; inductorNoise sources: substrate contacts drain/source junctions metal levels Noise receivers: substrate contacts drain/source junctions nFET channel (body effect) metal levels9W. Rhee, Institute of Microelectronics, Tsinghua UniversitySubstrate Noise Effect10W. Rhee, Institute of Microelectronics, Tsinghua UniversitySubstrate Noise in ASIC Environment •Synthesized digital circuits usually have 3-terminal transistorswith global supply and ground.•More complicated with huge number of transistors and different voltage islands.•Power/ground grids good for lowering impedance not for isolation. ÆDifficult to form customized substrate contacts.•Support for substrate modeling extraction??ÆBetter to have more silicon experience.Coupling Near Reference Clock Frequency•Strong intermodulation effect in reference clock path.On-Chip Digital Noise Injection•Isolation from time-modulated impedances such as switching circuits is very important!!Active Cancellation of Substrate NoiseA-SSCC’06, Kazama et al.•On-chip substrate noise cancellation-High demanding but challenging.What About Supply Noise?ISSCC’04, Takamiya et al.•Spectral analysis for both power and clock networks.Active Cancellation of Supply NoiseVLSI’04, Gu et al.•Active decoupling capacitor using Miller effect to save area.IV LΔΔ=Crosstalk•Packaging level solutions-GND between two critical signals.-Multiple wires to reduce inductance.-Separate critical pins away from noisy line. -Decoupling capacitors, floor bonding, ….Timing Isolation•Well-controlled timing isolation can reduce digital noise coupling.Slew Rate Reduction•Reduced digital power consumption.•Reduced substrate noise coupling from digital blocks.V. Advanced Topics2. Layout & Floor PlanningLayout for Matching and Coupling Reduction ÆSee “Ch. 18 Layout and Packaging,”Design of Analog CMOS Integrated Circuits by Razavi; shielding, interdigitizing, …Some Basic Guidelines•Separate analog and digital blocks.•High-frequency blocks close to output pads.•Routing VDD and GND together (do not make ring).•Avoid crossing between clock and analog signal.•Shielding for critical signals, e.g. VCO control input.•Use differential and symmetric configuration if possible.•Use guard ring and substrate/well contracts.•Star connection for VDD/GND•Minimizing VDD/GND inductance with multiple pads.•Decoupling cap should be close to chip.Some Tips•Don’t spend too much time in compacting/minimizing area for analog circuits.ÆFloor planning and understanding coupling is much more important!!ÆBe generous with decoupling cap area and substrate contact area. They will pay you back.ÆTop-down approach is fast and reliable.•Top-down approach is fast and reliable.•Divide and conquer!!Power/Ground Planning•How to reduce pin numbers?Use of Substrate ContactsSubstrate and GNDSubstrate = GND•Substrate contact tied to another quiet GND or same GND?•What about digital GND?Floor-Bonding (Down-Bonding)•Floor-bonding can minimize impedance.•Use conductive Epoxy for better ground plane.Capacitance at V = 25fFV. Advanced Topics3. On-Chip Calibration and TestabilityWhy On-Chip Monitoring?•Design migration is not straightforward anymore.ÆDemand for technology-friendly design •Modeling inaccuracy in advanced technologyex) history effect, self-heating in SOI, leakage current, …)•More process variation (VthÆMore conservative design than necessary •How to perform external diagnosis for GHz operation?•Detects zero-time crossing uncertainty caused by jitter.JSSC’06, Nose et al.•Interpolated jitter oversampling and Vernier delay line.ISSCC’05, Ishida et al.•Jitter detection w/o reference clock.•Peak jitter detection in amplitude.ÆRelaxes PSRR and resolution of delay lines.•Long-and mid-term jitter detection (FBW ~ FREF/2)On-Chip Jitter Measurement (4)Off-Chip Measurement On-Chip MeasurementISSCC’07, Liu et al.•Peak jitter detection in amplitude.ÆRelaxes PSRR and resolution of delay lines.•Long-and mid-term jitter detection (PLL BW –F REF /2)Static Offset MeasurementAutomatic Static Phase Offset CorrectionISSCC’07, Liu et al.On-Chip Leakage Compensation•Thin-oxide capacitor with on-chip leakage compensation.ÆHow to overcome gate voltage dependency?Circuit ExamplePatent filed: S. Wyatt et al. (BUR8-2003-0230)V. Advanced Topics 4. Future ChallengesFuture Challenges•High Performance ΔΣfractional-N PLL in wireless/wireline -How to reduce nonlinear effect and quantization noise?•Low jitter PLL/DLL/CDR for high-speed serial links•All-digital PLLs•Autonomic PLL with self calibration•On-chip testability & diagnosis (BIST)-Jitter monitor, supply voltage monitor•Leakage compensation•Low-noise wide-range VCOs•…ÆNeeds Innovation!谢谢！。