锁相技术译文翻译

锁相技术译文翻译英文原名：An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI译文：45纳米SOI全数字片上测量电路表征锁相环响应特性English中文 An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI Dennis Fischette, Richard DeSantis, and John Haeseon LeeAdvanced Micro Devices, Inc., Sunnyvale, CA 94085-3905 USAAbstract —An all-digital measurement circuit, built in 45-nm SOI-CMOS enables on-chip characterization of phase-locked loop (PLL) response to a self-induced phase step. This technique allows estimation of PLL closed-loop bandwidth and jitter peaking. The circuit can be used to plot step-response vs. time, measure static phase error, and observe phase-lock status.INTRODUCTIONMany applications such as PCI Express ™require a PLL to produce a low-jitter clockat a given frequency while meeting stringentbandwidth and jitter peaking requirements.Process, voltage, and temperature (PVT) variations as well as random device mismatchmake it difficult to guarantee a narrow rangefor PLL response. For example, loopparameters such as VCO gain could vary by more than 2X over PVT corners. In Fig. 1, we see the closed-loop jitter transfer functions of two PLLs with identical reference clock and output frequencies. One PLL exhibits large peaking and low bandwidth while the other shows little peaking but high bandwidth. Although differences in this example are more extreme than usual, similar but smaller differences often result from PVT variations.45纳米SOI 全数字片上测量电路表征锁相环响应特性作者信息摘要——全数字化测量电路，45纳米SOI-CMOS 工艺使其能够片上表征锁相环（PLL ）对自诱导相步进的响应。

这种技术允许估计PLL 闭环带宽和抖动峰值。

该电路可用于绘制阶跃响应随时间变化的曲线，测量静态相位误差，并观察相位锁定状态。

导言 许多应用像PCI Express™需要一个PLL 产生一个低抖动额定频率时钟的同时满足精确带宽和抖动峰值的要求。

工艺，电压和温度（PVT ）的变化与器件选用随机性一样会造成失配，使其难以确保PLL 的窄带响应。

例如，环路参数如VCO 增益变化可能超过PVT 角2倍上以。

图1中，我们看到两个具有相同参考时钟和输出频率PLL 的闭环抖动传递函数。

一个PLL 展现出大峰值和窄带宽，而另一个则是小峰值宽带宽。

虽然这个例子中显示的差异比通常所见要极端，这种相似而差异的特性往往会因PVT 变化而变小。

PLL response is often measured on a test bench using signal generators, oscilloscopes, and/or spectrum analyzers. For example, the transfer functions in Fig. 1 were automatically generated by modulating the 100-MHz reference clock with various frequencies while observing the amplitudes of the resulting output spurs. Such methods, which may require many seconds to complete, motivate the need for faster, less expensive, and preferably on-chip techniques to characterize PLL response [1]-[3]. Fig. 2 shows the PLL output phase transient response to an induced phase step. Similar to other second-order feedback systems, the PLL tends to overcorrect (or overshoot) as it works to eliminate the induced phase error. If the PLL is underdamped, as in this example, the PLL may ring several times before settling to its final lock state. A key metric in the PLL step-response is crossover, defined here as the elapsed time from input step to onset of phase overshoot. Another key metric is MaxOvershoot. It measures the maximum overcorrection in the step response.PLL 响应往往是通过一个使用信号发生器、示波器、和/或频谱分析仪组成的试验台来测试的。

例如，图1中，传递函数是通过调制100MHz 能产生各种频率的参考时钟，同时观察输出马刺产生的幅值自动生成的。

这样的方法，可能需要若干秒才能完成，使得对更快、更便宜方法需求更为迫切，而最好的方法便是通过片上技术来表征锁相环响应特性[1]-[3]。

图2显示了PLL 对致相步进响应的输出瞬态相位。

类似于其他二阶反馈系统，锁相环往往因其工作是消除相位误差而趋于过调（或过调）。

如果PLL 工作在欠阻尼状态，比如在这个例子中，环锁相环可能在其到达最终时钟状态前，经过几次锁定。

锁相环阶跃响应的一个关键指标是交叉反应，在此定义为从输入步进到相位超调开始出现所用的时间。

另一个关键指标是最大超调量。

它可以测量阶跃响应的最大过调量。

Transient simulations and closed-form loop equations [4] show that crossover is inversely proportional to the PLL ’s 3dBclosed-loop bandwidth; the smallercrossover is, the higher the bandwidth(Fig. 3). Notice that crossover is largely independent of the size of the phase step. Both simulations and loop equations also predict that MaxOvershoot is proportional to the maximum peaking in the closed-loop transfer function; the larger MaxOvershoot is, the greater the peaking (Fig. 4). Notice that the magnitude of the overshoot is also proportional to the input step size. These relationships between time- and frequency-domain behaviors allow us to make fast time-domain measurements and then relate the results back to frequency-domain performance specifications. The circuit瞬态模拟和闭环回路方程[4]表明，交叉反应和PLL 的3dB 闭环带宽成反比；交叉反应越小，带宽越大（图3）。

请注意，交叉反应在很大程度上与相位步长无关。

模拟和回路方程还预测到闭环传递函数中最大超调与最大峰值是成正比的;最大超调越大，峰值越高（图4）。

请注意，超调幅度也正比于输入步长。

时域和频域的这种特性让我们能够进行快速时域测量，然后将这些结果关联到频域性能指标中。

本文呈现的电路实现显示，PLL 阶跃响应可能被全数字化片上有限状态机捕获，从而实现快速表征锁相implementation presented in this paper shows that the PLL step response may be captured by an all-digital, on-chip finite state machine, allowing for fast PLL characterization. Silicon results indicate that this circuit could allow for Power-on calibration of the PLL bandwidth and peaking for compensation of process variations.CIRCUIT DESIGN The PLL under test (Fig. 5) is a standard integer-N charge-pump PLL. The only modification is the addition of loop measurement circuitry. The feedback divisor (N) is programmable from 5 to 63 although N>=8 during loop measurement tests. The charge-pump current, loop-filter resistance, and VCO gain are programmable to allow for bandwidth and peaking adjustments as well as jitter optimization. The PLL bandwidth may be configured from 3 to 25 MHz while the peaking may be varied from <1 to >4 dB. The VCO operates from 1.6 to 5 GHz. The expected reference clock frequency range is 100 to 200 MHz. 环。