英文资料及翻译 (2)

英文资料及中文翻译

PDIUSBD12----USB interface device with parallel bus

The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in microcontroller based systems and communicates with the system microcontroller over the high-speed general purpose parallel interface. It also supports local DMA transfer.This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments.This results in the fastest way to develop the most cost effective USB peripheral solution.The PDIUSBD12 fully conforms to the USB specification Rev. 2.0 (basic speed). It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices.Assuch, the PDIUSBD 12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations.The PDIUSBD12 low suspend power consumption along with the Lazy Clock output allowsfor easy implementation of equipment that is compliant to the ACPI(TM),OnNOW(TM), and USB power management requirements. The low operating power allows the implementation of bus powered peripherals. In addition; it also incorporates features like SoftConnect(TM), GoodLink(TM), programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals.

1. DMA transfer

Direct Memory Address (DMA) allows an efficient transfer of a block of data between https://www.360docs.net/doc/7c19291556.html,ingaDMAcontroller, data transfer between the

PDIUSBD12’s main endpoint (endpoint 2) and local shared memory can happen autonomously without local CPU intervention.

Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is set up for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and are terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA

enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer.

The PDIUSBD12 can be programmed for single-cycle DMA or burst mode DMA. In single-cycle DMA, the DMREQ pin is deactivated for every single acknowledgement by the DMACK_N before being re-asserted. In burst mode DMA, the DMREQ pin is kept active for the number of bursts programmed in the device before going inactive.This process continues until the PDIUSBD12 receives a DMA termination notice through pin EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed.

For DMA read operation,the DMREQ pin will only be activated whenever the buffer is full, signalling that the host has successfully transferred a packet to the PDIUSBD12.With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases the effective throughput.When the host does not fill up the buffer completely (lessthan64 bytesor 128 bytes for single direction ISO configuration), the DMREQ pin will be deactivatedat the last byte of the buffer regardless of the current DMA burst count. It will be re-asserted on the next packet with a refreshed DMA burst count.

Similarly, for DMA write operations, the DMREQ pin remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA writeoperation before the data is sent to the host. The only exception is at the end of DMA transfer, when the reception of pin EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token.

For isochronous transfers, the local CPU and DMA controller have to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms).

The assertion of pin DMACK_Nautomatically selects the main endpoint (endpoint 2), regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints.

DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N.

The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual address mode, pins DMREQ, DMACK_N and EOT_N are not used; instead CS_N, WR_N and RD_N control signals are used. The I/O mode Transfer Protocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle and the destination during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC. Command description

2. Command procedure

There are three basic types of commands: Initialization, Data Flow and General Commands. Respectively, these are used to initialize the function; for data flow between the function and the host; and some general commands.

2.1 Initialization commands

Initialization commands are used during the enumeration process of the USB network. These commands are used to enable the function endpoints. They are also used to set the USB assigned address.

⑴Set Address/Enable

Code (Hex):D0

Transaction: write 1 byte

This command is used to set the USB assigned address and enable the function.

⑵Set endpoint enable

Code (Hex):D8

Transaction: write 1 byte

Thegeneric/Isochronous endpoints can only been abled when the function is enabled via the Set Address/Enable command.

⑶Set mode

Code (Hex):F3

Transaction: write 2 bytes

The Set mode command is followed by two data writes. The first byte contains the configuration bits. The second byte is the clock division factor byte.

⑷CLOCK DIVISION

The value indicates the clock division factor for CLKOUT. The FACTOR output frequency is 48 MHz/(N+1) where N is the Clock Division Factor. The reset value is 11. This will produce the output frequency of 4 MHz which can then be programmed up or down by the user. The minimum value is 1 giving the range of frequency from 4 to 24 MHz. The minimum value of N is 0, giving a maximum frequency of 48 MHz.The maximum value of N is 11 giving a minimum frequency of 4 MHz.The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset.

⑸Set DMA

Code (Hex): FB

Transaction: read/write 1 byte

The set DMA command is followed by one data write/read to/from the DMA configuration register.DMA Configuration register: During DMA operation, the two-byte buffer header (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of this headers.For DMA read operations, the header will be skipped by the PDIUSBD12. For DMA write operations, the header will be automatically added by the PDIUSBD12. This provides for a clean and simple DMA data transfer.

2.2 Data flow commands

Data flow commands are used to manage the data transmission between the USB endpoints and the external microcontroller. Much of the data flow is initiated via an

interrupt to the microcontroller. The microcontroller utilizes these commands to access and determine whether the endpoint FIFOs have valid data.

⑴Read interrupt register

Code (Hex):F4

Transaction: read 2 bytes

This command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 5) are cleared by reading the endpoint last transaction status register through Read Last Transaction Status command. The other bits are cleared after reading the interrupt registers.

⑵Select Endpoint

Code (Hex):00 to 05

Transaction: read 1 byte (optional)

The Select Endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, which returns this byte.

FU LL/EMPTY: A ‘1’ indicates the buffer is full, ‘0’ indicates an empty buffer. STALL: A ‘1’ indicates the selected endpoint is in the stall state.

Fig 11. Select Endpoint command: bit allocation.

⑶Read Endpoint status

Code (Hex):80 to 85

Transaction: read 1 byte

⑷Read last transaction status register

Code (Hex):40 to 45

Transaction: read 1 byte

The Read Last Transaction Status command is followed by one data read that returns the status of the last transaction of the endpoint. This command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read.This command is useful for debugging purposes. Since it keeps track of every transaction, the status information is overwritten for each new transaction.

⑸Read buffer

Code (Hex):F0

Transaction: read multiple bytes (max. 130)

The Read Buffer command is followed by a number of data reads, which returns the contents of the selected endpoint data buffer. After each read, the internal buffer pointer is incremented by 1.The buffer pointer is not reset to the top of the buffer by the Read Buffer command.This means that reading or writing a buffer can be interrupted by any other command (except for Select Endpoint).

The data in the buffer are organized as follows:

* byte 0: reserved; can have any value

* byte 1: number/length of data bytes

* byte 2: data byte 1

* byte 3: data byte 2

* etc.

The first two bytes will be skipped in the DMA read operation. Thus, the first read

will get Data byte 1, the second read will get Data byte 2, etc. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet.

⑹Write buffer

Code (Hex):F0

Transaction: write multiple bytes (max. 130)

The Write Buffer command is followed by a number of data writes, which load the endpoints buffer. The data must be organized in the same way as described in the Read Buffer command. The first byte (reserved) should always be ‘0’.During DMA writes operation, the first two bytes will be bypassed. Thus, the first write will write into Data byte 1, the second write will write into Data byte 2, etc.

For non-isochronous transfer(bulk or interrupt), the buffer should be completely filled before the data is sent to the host and a switch to the next buffer occurs. The exception is at the end of DMA transfer indicated by activation of EOT_N, when the current buffer content (completely full or not) will be sent to the host.

Remark: There is no protection against writing or reading over a buffer’s boundary or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation.Data in an OUT buffer are only meaningful after asuccessful transaction.The exception is during DMA operation on the main endpoint (endpoint 2), in which case the pointer is automatically pointed to the second buffer after reaching the boundary (double buffering scheme).

⑺Clear buffer

Code (Hex):F2

Transaction: none

When a packet is received completely, an internal endpoint buffer full flag is set. All Subsequent packets will be refused by returning a NAK.When the microcontroller has read the data, it should free the buffer by the Clear Buffer command. When the buffer is cleared, new packets will be accepted.

⑻Validate buffer

Code (Hex): FA

Transaction: none

When the microprocessor has written data into an IN buffer, it should set the buffer full flag by the Validate Buffer command. This indicates that the data in the buffer are valid and can be sent to the host when the next IN token is received.

⑼Set endpoint status

Code (Hex):40 to 45

Transaction: write 1 byte

A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the content of the packet. If the endpoint should stay in its stalled state, the microcontroller can re-stall it.When a stalled endpoint is unstalled (either by the Set Endpoint Status command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer and if it is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.Even when unstalled, writing Set Endpoint Status to ‘0’ initializes the endpoint.

2.3 General commands

Send resume

Code (Hex)：F6

Transaction：none

Sends an upstream resume signal for 10 ms.This command is normally issued when the device is in suspend. The RESUME command is not followed by a data read or write.

Read current frame number

Code (Hex)：F5

Transaction：read 1 or 2 bytes

This command is followed by one or two data reads and returns the frame number of the last successfully received SOF. The frame number is returned Least Significant byte first.

PDIUSBD12带并行总线的USB接口器件

PDIUSBD12是一款性价比很高的USB器件，它通常用作微控制器系统中实现与微控制器进行通信的高速通用并行接口，它还支持本地的DMA传输。这种实现USB接口的标准组件使得设计者可以在各种不同类型微控制器中选择出最合适的微控制器。这种灵活性减小了开发的时间，风险以及费用（通过使用已有的结构和减少固件上的投资），从而用最快捷的方法实现最经济的USB外设的解决方案。PDIUSBD12完全符合USB1.1版的规范，它还符合大多数器件的分类规格，成像类海量存储器件，通信器件，打印设备以及人机接口设备。同样地，PDIUSBD12理想地适用于许多外设。例如，打印机，扫描仪，外部的存储设备（Zip驱动器）和数码相机等等。它使得当前使用SCSI的系统可以立即降低成本。PDIUSBD12所具有的低挂起功耗连同LazyClock输出可以满足使用ACPI，OnNOW和USB电源管理的要求，低的操作功耗可以应用于使用总线供电的外设。此外它还集成了许多特性，包括SoftConnet TM，GoodLink TM，可编程时钟输出，低频晶振和终止寄存器集合。所有这些特性都为系统显著节约了成本，同时使USB功能在外设上的应用变得容易。

1. DMA传输

直接存储器寻址（DMA）允许在主端点和本地共享存储器间实现数据块的有效传输。使用DMA控制器，PDIUSBD12的主端点和本地共享存储器间的数据传输可自主进行而不需要本地CPU的干预。要处理任何DMA传输，本地CPU从主机接收必要的SETUP信息并对 DMA控制器进行相应的编程，典型的对DMA控制器的

传输模式，字节计数寄存器和地址计数器进行正确的编程。在该模式下，PDIUSBD12发出请求时开始传输。当字节计数器减少为零时终止。在DMA控制器编程之后，本地CPU在初始化传输时将PDIUSBD12中的DMA使能位置位。

PDIUSBD12可编程为单周期DMA或突发模式DMA。在单周期DMA中，DMREQ 在每单个应答后直到被DMACK_N重新激活之前保持无效。在突发模式DMA中，DMREQ在器件中突发编程时一直保持有效。该过程持续到PDIUSBD12通过EOT_N 接收到一个DMA终止信息。这时产生一个中断指示本地CPU DMA操作已经完成。

在DMA读操作时DMREQ仅当缓冲区完全表示主机成功的发送了一个信息包到PDIUSBD12时才有效。由于具有双缓冲配置，主机可以在第一个缓冲区被读出时对第二个缓冲区进行填充，这种并行的处理有效的增加了数据吞吐量。当主机没有完全填满缓冲区的情况下（单向ISO配置时小于64或128字节），DMREQ会在缓冲区的最后一个字节时无效而不管当前的DMA突发计数。在更新了DMA突发计数的下一个包发送时，DMREQ再次被激活。

DMA的写操作与之相似，当缓冲区未装满时，DMREQ一直有效。当缓冲区填满时，在下一个IN标志将信息包送入主机。当传输完成之后，DMREQ变为无效。同样的，双缓冲配置在这也改善了数据的吞吐量。在非同步传输中，批量模式和中断。在数据被发送到主机之前，缓冲区需要通过DMA写操作完全装满。唯一的例外是，在DMA传输结束时，EOT_N接收的信号将会停止DMA写操作并且在下一个IN标志置位时将缓冲区的内容传送到主机。

在同步模式中，本地CPU和DMA控制器必须保证它们在一个USB帧（1ms）中能够吞吐的最大信息包的规模。DMACK_N的激活将自动选择主端点（端点2）而不管当前选择的端点。PDIUSBD12的DMA操作可通过普通的I/O对其它端点的存取实现交叉存取。DMA操作可通过以下方式终止：复位DMA使能寄存器位或EOT_N加上DMACK_N以及 RD_N/WR_N的激活。

PDIUSBD12支持单地址模式中的DMA传输，也可以在DMA控制器的双地址模式中工作。在单地址模式中DMA通过DREQ DMACK_N,EOT_N,WR_N和RD_N控制线实现传输。在双地址模式中DMREQ,DMACK_N和EOT_N未用，取而代之的是CS_N,WR_N和RD_N控制信号。需要遵循PDIUSBD12的I/O模式传输协议。在读周期中对DMAC信号源进行访问，在写周期对目标进行访问，传输需要两个单独的总线周期来储存暂存在DMAC中的数据。

2. 命令描述

有3种基本的类型的命令：初始化，数据流和通用命令。

2.1 初始化命令

初始化命令在USB网络进行枚举处理时使用，这些命令用于使能端点的功能，还可用来设置USB配的地址。

⑴设置地址/使能

命令：D0h

处理：写1字节

该命令用于设置USB分配的地址和使能功能。

地址写入的值即为地址

使能置1使能该功能

⑵设置端点使能

命令：D8h

处理：写1字节

通过设置设置地址/使能命令后才可使能普通/同步端点

普通/同步

端点值1表示普通/同步端点使能

⑶设置模式

命令：F3h

处理：写2字节

设置模式命令后跟2个写入的数据，第一个字节包含配置字节信息，第二个字节是时钟分频因素字节。

配置字节

无LazyClock：1 表示CLKOUT不会切换到LazyClock，0表示CLKOUT在Suspend 脚变高之后切换到LazyClock，LazyClock频率是30KHz±40%，编程值将不过会被总线复位所改变。

时钟运行：1表示内部时钟和PLL即使在挂起状态下仍然运行，0表示只要不需要时，内部时钟晶振和PLL就停止运行，为了满足严格的挂起电流要求，该位需要设置为0，已编程的值不会被总线复位所改变。

中断模式：1表示报告所有的错误和“NAKing”并产生一个中断。0表示只有OK 被报告。编程值不会被总线复位所改变。

SoftConnect：1表示如果VBUS可用，上行数据上拉电阻就被连接，0表示不连接。已编程的值不会被总线复位所改变。

端点配置：该2位设置端点配置如下：

模式 0 非同步模式

模式 1 同步输出模式

模式 2 同步输入模式

模式 3 同步输入/输出模式

⑷时钟分频系数字节

时钟分频系数：该值用来表示CLKOUT的时钟分频系数，用N表示分频系数，那么输出频率就为48MHz/(N+1)，复位值为11。这产生4MHz的输出频率，然后可由用户自行调节。当N为0时，得到最大频率48MHz，当N取最大11时，得到最小频率4MHz。PDIUSBD12的设计确保了在改变频率时不会出现干扰，已编程的值不会被总线复位所改变。

SET_TO_ONE：该位需要在任何DMA读或写操作之前置为1。该位在上电复位值为0。复位后可将其一直设为1。

仅有SOF中断模式：将该位置1后，仅当帧时钟的起始（SOF）时刻引起中断的产生而不管引脚中断模式的设置状态设置（DMA位5）

⑸设置 DMA

命令：FBh

处理：读/写1字节

设置DMA命令后跟1个字节数据写入/读出 DMA配置寄存器

DMA配置寄存器

在DMA操作中，两字节的缓冲区头（状态和字节长度信息）不参与传送。这就允许了DMA数据的连续性，不插入信息头。DMA读操作时，信息头被PDIUSBD12跳过，在DMA写操作时，信息头由PDIUSBD12自动添加，这就提供了一个简洁的DMA数据传输。

DMA突发串：选择DMA操作的突发串长度

00 单周期 DMA

01 突发串 4 周期 DMA

10 突发串 8 周期 DMA

11 突发串 16 周期 DMA

DMA使能：向该位写入1会通过激活DMREQ启动DMA操作，在激活DMREQ之前需要装满（DMA读操作）或清空（DMA写操作）主端点缓冲区。在单周期DMA模式中，DMREQ在突发串数目耗尽后无效，然后下一个突发串时重新激活，这个过程一直持续到EOT_N和DMACK_N以及RD_N或WR_N一起被激活。此时将该位置0并终止DMA操作，DMA操作也可通过直接向该位写入0来终止。

DMA方向：该位决定了DMA传输时数据流的方向，1表示从外部共享存储器到PDIUSBD12（DMA写操作），0表示从PDIUSBD12到外部共享存储器（DMA读操作）。自动重装：当该位设为1，DMA操作会自动重新启动。

中断脚模式：0表示正常的中断脚模式，中断寄存器所有位的逻辑或产生中断，当该位写入1时表示中断会在USB总线上行数据流出现帧时钟

（SOF）起始位时产生中断。其它中断仍然有效。

端点索引4中断使能：该位为1表示只要端点缓冲区包含一个有效的信息包就会

产生中断，通常在DMA操作时关闭以减少不必要的CPU

响应。

端点索引5中断使能：该位为1表示只要端点缓冲区有效，见缓冲区生效命令，

就会产生中断，通常在DMA操作时关闭以减少不必要的

CPU响应。

2.2 数据流命令

数据流命令用于管理USB端点和外部微控制器之间的数据传输，通过微控制器中断初始化大量的数据流。微控制器利用这些命令访问和决定端点的FIFO是否含有有效的数据。

⑴读中断寄存器

命令：F4h

处理：读2字节

中断寄存器字节1

中断寄存器字节 2

该命令指示中断的来源，通过读端点最后处理状态寄存器将端点中断位（位0~5）清零，其它位在读中断寄存器后被清零。

总线复位：在总线复位后将产生一个中断将该位置1。总线复位与通过RESET_N 脚的硬件

复位基本相同，有一点除外，就是总线复位产生一个中断并且器件在

默认地址0处使能。

挂起改变：当PDIUSBD12没有收到3个SOF时，将会进入挂起状态并将挂起改变位置位。任何挂起或唤醒状态的改变都会将该位置位并产生中断。DMA EOT：该位表示DMA操作已结束。

⑵选择端点

命令：00-05h

处理：可选读1字节

选择端点命令将内部指针初始化到选择的缓冲区起始位置。可选的该命令可跟一个返回的读出字节。

满/空 1表示缓冲区已满，0 表示缓冲区为空。

停止 1表示选择的端点处于停止状态。

⑶读端点状态

命令：80-85h

处理：读1字节

⑷读最后处理状态寄存器

命令：40-45h

处理：读1字节

读最后处理状态寄存器命令后跟一个数据返回端点最后处理的状态，该命令同时复位中断寄存器中的相应位并将状态清零表示已经读取，由于它保留了每次处理的记录，所以该命令在以调试为目的时很有用。在每次新的处理之后会将原来的状态信息覆盖。

数据接收/发送成功：1表示数据已经成功地接收或发送。

SETUP信息包：1表示最后成功接收的信息包有一个SETUP标志，对IN缓冲区进行读总为0。

数据0/1包：1表示最后成功接收/发送包含有一个DATA1 PID。

前一状态未读：1表示在前一状态被读出之前发生了第二个事件。

⑸读缓冲区

命令：F0h

处理：读多个字节，最大130

读缓冲区命令后，返回一系列从选择的端点数据缓冲区读出的数据，每读一个字节，内部缓冲区指针自动加一，读缓冲区命令不会将缓冲区指针复位到缓冲区起始端，这意味着可被其它的命令所中断（选择端点命令除外）。

缓冲区数据结构如下

字节1：保留;可为任意值

字节2：数据字节的数目/长度

字节3：数据字节1

字节4：数据字节2

……

头两个字节在DMA读操作中可跳过。因此第一个读出的字节是数据字节1。第二个读出的是数据字节2等等。PDIUSBD12可通过USB信息包的EOP终止来决定包

的最后一个字节。

⑹写缓冲区

命令：F0h

处理：写多个字节，最大130

写缓冲区命令后跟一系列需要写入端点缓冲区的数据，数据的结构必须与前面描述的读缓冲区命令一样。第一个字节（保留）总为0。在DMA写操作中，头两个字节会被绕过，因此，第一个写入的字节是数据字节1。第二个写入的是数据字节2等等。在非同步传输（批量或中断）中，数据被发送到主机之前缓冲区必须被完全填满并切换到下一个缓冲区。例外的情况是，当前的缓冲区内容将要被发送到主机时，由有效的EOT_N指示DMA传输的结束。

⑺清缓冲区

命令：F2h

处理：无

当一个信息包完全接收之后，内部端点缓冲区满标志置位，所有后续的包将被返回的NAK拒绝，当微控制器已读取数据，它应当通过清缓冲区命令来释放缓冲区，当缓冲区清空之后新的信息包就可被接受了。

⑻使缓冲区有效

命令：Fah

处理：无

当微控制器已将数据写入IN缓冲区，它应当通过使缓冲区有效命令设置缓冲区满标志，这表示缓冲区内的数据有效并可在接收到下一个IN标志时将其送入主机。

⑼设置端点状态

命令：40-45h

处理：写1字节

当一个停止控制的端点接收到SETUP标志时自动解除停止，而不管信息包的内容如何，如果端点应当停在停止状态，微控制器可以重新停止它。

当一个停止的端点解除了停止，设置端点命令或接收到一个SETUP标志，它同时被重新初始化将缓冲区刷新，如果是OUT缓冲区就等待一个DATA 0 PID，如果是IN缓冲区就写入一个DATA 0 PID，即使在解除停止时，将设置端点状态写为0，也将初始化端点。

停止 1 表示端点处于停止状态

2.3普通命令

发送恢复

命令：F6h

处理：无

发送一个上行数据流恢复信号10ms，该命令通常用于器件处于挂起状态时，恢复命令后不跟读出或写入的数据

读当前帧数目

该命令后跟1到2个读出的字节并返回最后成功接收的SOF帧数目，帧数目为返回的低位字节。