锁相技术译文翻译

锁相技术译文翻译英文原文：An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI译文：45纳米SOI全数字片上测量电路表征锁相环响应特性年级专业：姓名：学号：2013 年 6 月 2 日英文中文An On-Chip All-Digital MeasurementCircuit to Characterize Phase-LockedLoop Response in 45-nm SOIAbstract—An all-digital measurement Circuit , built in 45-nm SOI-CMOS enables on-chip characterization of phase-locked loop (PLL) response to a self-induced phase step.This technique allows estimationof PLL closed-loop bandwidth and jitterpeaking. The circuit canbe used to plot step-response vs.time, measure static phase error,and observe phase-lock status. INTRODUCTIONMany applications such as PCI Express? require a PLL to produce alow-jitter clock at a given frequency while meeting s tringent bandwidth and jitter peaking r 45纳米SOI全数字片上测量电路表征锁相环响应特性摘要---建立在45纳米的SOI-CMOS上一个全数字测量电路，它能够表征PLL对自诱导相步进的响应这项技术允许对PLL闭环带宽和抖动峰值的估计。

这个电路被用来绘制阶跃响应随时间变化的曲线，测量静态相位误差和观察相位锁定状态。

介绍很多应用例如PCI Express?需要一个PLL来产生一个低抖动的在一个给定频率的时钟，这个频率满足精确带宽和抖动峰值的要求。

equirements. Process, voltage, and tem perature (PVT) variations as well as rand om device mismatch make it difficult toguarantee a narrow range for PLL resp onse. For example ,loop parameters suc h as VCO gaincould vary by more than 2X overPVT corners. In Fig. 1, we see the closed-loop jitter transfer functions of two PLLs with identical reference clock and output frequencies. One PLL exhibits largepeaking and low bandwidth while theother shows little peaking but high ban dwidth. Although differences in this exa mple are more extreme than usual, similar but smaller differences often result from PVT variations.PLL response is often measured on atest bench using signal generators, osci lloscopes, and/or spectrum analyzers.For example, the transfer functions in Fi 工艺，电压，和温度（PVT）变化以及随机的选择不搭配的器件都使得很难保证一个窄的变化范围的PLL响应，例如，环路参数如VCO增益变化可能超过PVT角2倍上以。

图一中，我们可以看到两个具有相同参考时钟和输出频率PLL的闭环抖动传递函数一个PLL展现大的峰值和低带宽，而另一个展示了小峰值但是高带宽虽然这个例子中显示的差异比通常的要极端，这种相似会随着PVT的变化而变小PLL的响应往往使用一个信号发生器、示波器，和/或频谱分析仪。

g. 1 were automatically generated by modulating the 100-MHz reference clock with various frequencies while observin g the amplitudes of the resulting output spurs. Such methods, which may requi re many seconds to complete, motivate the need for faster, less expensive, and preferably on-chip techniques to charac terize PLL response [1]-[3]. Fig. 2 shows the PLL output phase transient respons e to an induced phase step. Similar to other second-order feedback systems, t he PLL tends to overcorrect (or oversho ot) as it works to eliminate the induced phase error. If the PLL is underdamped, as in this example, the PLL may ring sev eral times before settlingto its final lock state. A key metric in the PLL step-resp onse is crossover, defined here as the elapsed time from input step toonset of phase overshoot. Another key metric is MaxOvershoot. It 例如，在图一中传递函数是通过调制100MHz能产生各种频率的参考时钟同时观察输出马刺产生的幅值自动生成的。

这种方法，可能需要一些时间去完成，这促进了更快，更便宜的方法的需要。

比较好的方法是片上系统来表征PLL的响应特性[1]-[3]。

表二表明致相步进响应的输出瞬态相位。

类似于其他二阶反馈系统，PLL倾向于过调（或过调），那是因为它是为了消除相位误差。

如果锁相环工作在欠阻尼状态，在这种状态下，PLL可能要经过几次锁存在达到最终锁measures the maximum overcorrectionin the step response.Transient simulations and closed-form loop equations [4] show that crossover is inversely proportional to the PLL’ｓ 3dB closed-loop bandwidth; the smaller crossoveris, the higher the bandwidth (Fig. 3). Notice that crossover is largely independent of the size ofthe phasestep. Both simulations and loop equations also predict that MaxOvershoot is p roportional to the maximum peaking inthe closed-loop transfer function; the larger MaxOvershoot is, the greaterthe peaking (Fig. 4). Notice thatthe magnitude of the overshoot isalso proportional to theinput stepsize .These relations hips between time- and frequency-domain behaviors allow us to make fast time-domain measurements and then relate the results back to frequency-domain performance specifications. The 存状态之前锁相环阶跃响应的一个关键指标是交叉反应。

在此定义为从输入步进到相位超调开始出现所用的时间另一个关键指标是最大超调量。

它可以测量阶跃响应的最大过调量。

瞬态模拟和闭环回路方程[4]表明交叉反应和PLL的3dB闭环带宽成反比；交叉反应越小，带宽越大（图3）。

请注意，交叉反应在很大程度上与相位步长无关。

模拟和回路方程还预测到闭环传递函数中最大超调与最大峰值是成正比的;circuitimplementation presented in this papershows that the PLL step response maybe captured byanall-digital, on-chip finite statemachine, allowing for fast PLL characterization.Silicon results indicate that this circuit could allow for Power-on calibration of the PLL bandwidth and peaking for com pensation of process variations.CIRCUIT DESIGNThe PLL under test (Fig. 5) isa standard integer-N charge-pump PLL. The only modification is theaddition of loop measurement circuitry.The feedback divisor (N) isprogrammable from 5 to 63 ，although N>=8 during loop measurement tests. The charge-pump current, loop-filter resistance, and VCO gain are pro grammable to allow for bandwidth andpeaking adjustments aswell as jitter opt 最大超调越大，峰值越高（图4）。