Assembling Low-Level Tests to High-Level Symbolic Test

Assembling Low-Level Tests to High-LevelSymbolic Test FramesG. Jervan, A. Markus, J. Raik, R. UbarTallinn Technical UniversityEhitajate tee 5, EE0026, Tallinn, ESTONIA, e-mail: raiub@pld.ttu.eeAbstract: A hierarchical test generation approach for digital systems which uses register-transfer (RT) and gate level system descriptions is presented. Theproposed test generator implements novel fault simulation and test generationapproaches based on alternative graph models. A uniform fault model anduniform simulation and decision procedures are used at both levels. Experimentalresults showing the efficiency of the approach are provided.1. IntroductionTest generation for real life digital circuits and systems on the gate-level is extremely complex. It has been shown that test generation for combinational circuits is an NP-complete problem [1]. During recent times, as a possible solution for the problem, hierarchical test generation methods have evolved [2-3] which take advantage of higher abstraction level information while generating tests for the gate-level faults. In hierarchical testing, top-down and bottom-up strategies are known. In the bottom-up approach, tests generated at the lower level will be later assembled at the higher abstraction level. Generality of the approach lays in possibility of using precalculated library tests for components during higher level test synthesis. On the other hand, high-level constraints cannot be considered in creating libraries of test patterns, which can cause that solutions cannot be found even if they exist.Current paper represents a method which allows to implement both, bottom-up and top-down approaches at the uniform basis. In the top-down approach, constraints will be extracted at the higher level with the goal to be considered when deriving tests for components at the lower level. In the hierarchical approach of the paper, different system levels (RTL and gate-level) are represented by alternative graphs (AG) [4]. AGs provide a uniform system representation, uniform fault model and an application of standardized procedures throughout the levels. Differently from known methods, both control and data paths are handled by uniform fault activation and fault propagation methods. Uniform approaches for gate- and higher level descriptions afford easily to adopt gate-level fault propagation and line justification methods and tools to higher level ones.2. Alternative graphs as a system modelAlternative graph is defined as a non-cyclic directed graph whose nodes are labelled by variables (constants or algebraic expressions). For each value from a set of predefined values of a non-terminal node variable, there exists a corresponding output branch from the node. Consider a situation where all variables are fixed to some value. By these values, for each non-terminal node a certain output branch is chosen entering into a successor node. Let us call these connections between nodes - activated branches, and the chains of them - activated paths. For each combination of values of variables, there exists a main activated path from the root node to some terminal node. This relation describes a mapping from a Cartesianproduct of the sets of values for variables in all nodes to the joint set of values for variables in terminal nodes. Therefore, by AGs it is possible to represent arbitrary digital functions Y=F(x), where Y is the variable whose value will be calculated on the AG and x is the vector of all variables in nodes of the AG.As a hierarchical input to the test generator are descriptions where the architecture of the circuit is described at the RTL and the low-level structure is given at the gate level. Both these levels can be described by AG models. In the RTL descriptions, designs are partitioned into datapath and control parts. Datapath is represented by a netlist of interconnected blocks. The building blocks of datapath are registers, multiplexers and functional units (FU), where functions can be arbitrary arithmetic or logic operations. Datapath can be represented by a system of AGs, where for each primary output and for each register, an AG corresponds. In the graph models, the non-terminal nodes correspond to control signals and terminal nodes represent operations. Register transfers and constant assignments are treated as special cases of operations. Branches between the nodes determine, which operation will be assigned to the variable by each value combination of the control signals. Figure 1 explains the AG representation of a datapath register for the general case.Figure 1 Alternative graph representation for a datapath registerThe control part of an RTL description is described as a Finite State Machine (FSM) state table. Similar to the datapath, the state table can be represented by an AG model. In that case the non-terminal nodes correspond to current state and conditions (FSM inputs), and terminal nodes hold the values of next state and control signals (FSM outputs). Fig. 2 shows an example of a fragment of a FSM state table and the corresponding AG representation. In the AG, q denotes the next state and q’ denotes the current state value. The variables out1, out2, out3 and out4 are output variables of the FSM. The graph in Fig.2. describes the behavior ofthe FSM at the current state being s5.Figure 2 Representing a fragment of a FSM state table by an AGM U X R E G. ... op. 1 op. 2 op. n select enabl e rese t =0 =1 =n-1reg .3. Uniform fault model for different system levelsThe main idea of the AG-fault model lies in the relationship of faults to nodes in graphs, in the similar way as logical level stuck-at faults are related to Boolean variables in logical expressions. In the binary case, each node of an AG is labelled by a Boolean variable and, therefore, is related to stuck-at faults of this variable. In the general case, each path in a graph describes the behavior of the system in a specific mode of operation. The faults having effect on the behavior can be associated with nodes along the given path. A fault causes an incorrect leaving the path activated by a test. From this point of view, we can introduce now the following general fault model for nodes m with node variables z(m) in AG-representations of digital systems: 1) the output branch at z(m)=i of a node m is always activated (z(m)/∅⇒i),2) the branch at z(m)=i of a node m is broken (z(m)/i ⇒∅), or 3)instead of the given branch at z(m)=i of m, another branch at z(m)=j or a set {j} is activated (z(m)/i ⇒{j}).The fault model is directly related to nodes and describes the faulty behavior of the system clearly in terms of the model. In the model, at first, the situation how an AG is activated is described (a value i of the node variable is given), and, secondly, the new faulty activation{j} is described.All the procedures of simulation and test generation, like fault activation, fault propagation and line justification for a component with output variable Y described by a graph G(Y), are performed by uniform path tracing procedures in G(Y). In simulation, the main activated path (MAP) will be traversed at given values of variables. For activating a fault at m ∈G(Y), at first, a MAP through m will be activated, then, additional paths from the faulty activated branches of m will be activated, to produce a value of Y which differs from that produced by MAP. For fault propagation, a MAP will be activated to produce a I-path or F-path. For line justification, again a MAP will be activated.4. Test Generation AlgorithmThe hierarchical test generation approach presented consists of five main stages. These are fault manifestation, fault propagation, constraint justification, constraint satisfaction and low-level test. The test generation algorithm has been implemented as a systematic search and therefore an inconsistency in any stage will cause a backtrack and a return to the last decision. In the following, the different stages will be explained more in detail.Figure 3 A scanning test exampleFault manifestation . As it was mentioned above, there exist two types of nodes in AG models: terminal nodes and non-terminal nodes. Appropriate tests for the types have to be set up during the fault manifestation stage. The two types of tests are referred to as scanning test and conformity test , respectively. Scanning tests are applied to terminal nodes and their aim is to test the functional units (FU), registers and constants of the datapath. Conformity tests areOp. 1 Op. 2set up for non-terminal nodes and they target the multiplexers of datapath as well as control signal decoders in the control.During the scanning test, a terminal node under test is selected. The path is activated to the node in the respective AG. The symbolic fault-effect value is assigned to the variable corresponding to the graph, and symbolic test vectors are assigned to the variables of the arguments of the function labelling the node under test. These symbolic values are later treated as justification objectives. Figure 3 presents a simple example where scanning test is performed for operation Op.1 in the graph Register . The faults targeted by the scanning test are marked by gray areas in the figure.Conformity test is similar to the scanning test in the way that a path is activated to the node under test, and the fault effect value is assigned to the graph variable. In addition, the successor nodes of the node under test must be distinguished from each other. The symbolic values to be backtraced during the justification are assigned to the variables labelling corresponding terminal nodes of the graph. Due to the fact that conformity test for a node must be carried out with each value of the control signal under test, there exist multiple test patterns in conformity tests per each non-terminal node.There could exist some additional, technology dependent, criteria included to the conformity tests. E.g. in the case of AND-OR type multiplexers that most of the VLSI technologies are utilizing, the set of conformity tests for a node must cover zeros in all bit positions of its selected successor nodes. An example in Figure 4 presents the conformity test for the control signal select . The faults targeted by the test are marked with gray areas.Figure 4 Conformity testFault effect Propagation . Subsequent to the manifestation phase, the fault effect has to be propagated to primary outputs of the whole circuit. Basing on the values assigned to the control signals during the manifestation, a terminal node of the FSM AG, which will provide the initial state and the control vector, will be chosen. The propagation procedure will follow, where decisions are made, both on the datapath graphs as well as on the control part graph. If in the control part graph any nodes containing logic conditions are traversed then corresponding path activation constraints will be created. The procedure will end when the fault effect value has reached a primary output.Constraint justification . The aim of the justification is to backtrace the values and symbols that were set during the manifestation and propagation phases. The backtrace is performed via a constraint extraction. Each time that a backward step is made during the justification, the contents of the constraints will be updated. This is done according to the control vectors that are active at the respective time frames. Justification will end when all the variables in the constraints are primary inputs or constants.Op. 1 Op. 2The constraints can be divided into two categories: path activation constraints and transformation constraints. Path activation constraints are the constraints required to provide a transparent path through the circuit. Transformation constraints, in turn, reflect the value changes along the activated path. Path activation constraints are the constraints corresponding to the conditions to be satisfied in the FSM and to the values that are required to create a transparent path through an FU. Transformation constraints describe the changes in low-level test vectors on their way from primary inputs to the inputs of the module under test. During each time frame that is earlier than the manifestation time, the justification procedure selects a justification objective. In current implementation the objective is the first unjustified variable in the transformation constraints, or in case the transformation constraints are justified, the objective will be the first unjustified variable in the path activation constraints, respectively. At every justification step, the constraints containing only constant variables will be simulated. This improvement to the test generation algorithm makes it possible to detect obvious inconsistancies at early stages of path activation and hence reduces the search space.At this point of the algorithm we have created the high-level symbolic test frames. In the following phases, actual values have to be calculated for the symbolic values of the frames. Constraint satisfaction. Subsequent to the constraint justification, the constraints have to be solved. In order to achieve that goal, any known Constraint Satisfaction Problem (CSP) solving algorithm can be applied. Only the path activation constraints are managed during constraint satisfaction. Transformation constraints are considered in the low-level test.Low-level test.This step targets the gate-level structural faults in the modules under test (MUT). During the low-level test, random values are generated to the variables of transformation constraints. The constraints are simulated to obtain the transformed vectors at the inputs of MUT, which in turn are applied to a fault simulation of the module. If a fault is detected at the output of the module, it is also detected at the primary outputs of the whole device. This is true because the fault effect propagation has previously guaranteed a transparent path from the output of the module to the primary outputs.The vectors that detect previously undetected faults are compiled into final test vectors for the whole hierarchical circuit. This takes place by substituting the symbolic values in the high-level symbolic test frames by the actual values found during constraint satisfaction and low-level test.In the above algorithm description, transprency aspects were not included. Current test generator is open in terms of transparency rules and supports different levels of transparencies: I-paths, F-paths, etc. The required rules can be provided by the user. In the experiments presented in current paper, the tests were carried out by implementing a transparency based on the F-path method.5. E xperimental resultsExperiments were carried out on a Greatest Common Divisor (GCD) circuit. The synthesized RTL version of the circuit has 5 registers and an FSM with 12 states. The circuit was chosen as it reveals a number of difficult test generation problems. It contains a global data dependent loop and only one of the registers is directly observable. The datapath of the circuit is shown in Figure 5. The test results were the following. At the high level, all of the 9 scanning tests were generated, the conformity test generation had a partial success. The achieved fault coverage was 95,1 %. The actual quality of the test sequence was measured at the low-level by applying gate-level fault simulation to the whole circuit. The level of 100%fault coverage was not reached either because of the redundancy of the embedded blocks or because of the bad testability of the circuit. Table 1. presents the experimental results. The experiment was run on a Sun Ultrasparc 1 computer.Figure 5 Datapath of the GCD circuitTable 1 Number of gate-level faults1066 Gate-level fault coverage (%)95,1 Test generation time (s)37,1 Number of generated symbolic test patterns53 Total test length (number of clock cycles) 6276. ConclusionsCurrent paper describes a new hierarchical test generation system based on using alternative graphs. Differently from known methods both, higher and lower design abstraction levels, and both, control and data paths are handled here by uniform fault models and by uniform fault propagation methods. Uniform basis for gate- and higher level descriptions allow easily to adopt and generalize gate-level simulation and ATPG methods and tools to higher level ones. As the result the complexity of the problem reduces and the efficiency of test generation and fault simulation increases.References[1] H.Fujiwara. Logic Testing and Design for Testability. MIT Press, Cambridge, Massachusets,1985.[2] J.Lee and J.H.Patel. ARTEST: An Architectural Level Test Generator for Data Path Faults andControl Faults. Proc. Int. Test Conf. Oct. 1991, pp. 729-738.[3] S.R.Rao, B.Y.Pan, J.R.Armstrong. Hierarchical Test Generation for VHDL Behavioral Models.Proc. EDAC, Feb. 1993, pp. 175-183.[4] R.Ubar. Test Synthesis with AGs. IEEE Design and Test of Computers, Vol.13, No.1, Spring1996, pp.48-57.[5] J.Raik, R.Ubar, G.Jervan, H.Krupnova. A Constraint-Driven Gate-Level Test Generator. Proc. ofthe Baltic Electronic Conference, Tallinn (Estonia), Oct. 7-11, 1996, pp. 237-240.[6] R.Ubar, M.Brik. Multi-Level Test Generation and Fault Diagnosis for Finite State Machines.Dependable Computing - EDCC-2. Lecture Notes in Computer Science No. 1150. Springer Verlag, 1996, pp.264-281. mux3 reg3 reg4 mux4 mux1mux2reg5reg1reg2= <x y result。