嵌入式系统论文

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嵌入式系统在计算机控制中的应用简介摘要：嵌入式系统的广泛应用，已经渗入到我们日常生活的各个方面。

在手机、MP3（Moving Picture Expert Group Layer 3，一种按运动图象专家组制定的标准压缩编码的数字音频文件格式的声音播放器）、PDA（Personal Digital Asistant，个人数字助理）、数码相机、空调，甚至电饭锅、手表里，都有嵌入式系统的身影。

关键词：嵌入式系统数码相机芯片正文：嵌入式系统的广泛应用，已经渗入到我们日常生活的各个方面。

嵌入式系统小到一个芯片，大到一个标准的PC机或一台独立的设备，种类繁多，让人顿生目不暇接之感。

当今工业界的自动化、信息化和网络化已经成为一种不可逆转的趋势。

在工业自动化控制、通信、仪器仪表、汽车、航空航天、消费类电子产品等领域更是嵌入式系统的天下。

1 嵌入式系统定义和分类嵌入式系统的“嵌入”特性意味着系统的本身与其所控制和管理的系统是融为一体的，是其中的一个有机组成部分，是各种控制系统的基本构造单元。

硬件形式的嵌入系统多为专用的或可编程控制的芯片，是最主要的嵌入式系统，而软件形式的嵌入式系统则主要是各种专门用途的控制软件系统。

嵌入式系统在有的应用情况下是显式存在的，即用户可明显感觉到该系统的存在，但更多的情况下用户在实际使用过程中很难察觉到其存在性，即使是有经验的技术人员也需要经过充分的比较，才能确定在某一特定过程中是否有嵌入式系统的参与。

根据IEEE（国际电气和电子工程师协会）的定义，嵌入式系统是“控制、监视或者辅助设备、机器和车间运行的装置”。

嵌入式系统论文英文

J Sign Process SystDOI 10.1007/s11265-011-0650-6Instruction Cache Locking for Embedded Systems using Probability ProfileTiantian Liu· Minming Li · Chun Jason XueReceived: 27 August 2010 / Revised: 31 August 2011 / Accepted: 21 November 2011© Springer Science+Business Media, LLC 2011Abstract Cache is effective in bridging the gap between processor and memory speed. It is also a source of unpredictability because of its dynamic and adaptive behavior. A lot of modern processors provide cache locking capability which locks instructions or data of a program into cache so that a more precise estimationof execution time can be obtained. The selection of instructions or data to be locked in cache has dramatic influence on the system performance. For real-time systems, cache locking is mostly utilized to improve the Worst-Case Execution Time (WCET). However, Average-Case Execution Time (ACET) is also an im-portant criterion for some embedded systems, espe-cially for soft real-time embedded systems, such as image processing systems. This paper aims to utilize instruction cache (I-Cache) locking technique to guar-antee a minimized estimable ACET for embedded sys-tems by exploring the probability profile information.A Probability Execution Flow Tree (PEFT) is intro-duced to model an embedded application with runtime profile information. The static I-Cache locking problem is proved to be NP-Hard and two kinds of locking, fully locking and partially locking, are proposed to find the instructions to be locked. Dynamic I-Cache locking can further improve the ACET. For dynamic I-Cache locking, an algorithm that leverages the application’s branching information is proposed. All the algorithms are executed during the compilation time and the re-sults are applied during the runtime. ExperimentalT. Liu (B) · M. Li · C. J. XueDepartment of Computer Science, City University ofHong Kong, Kowloon, Hong Konge-mail: tiantianster@ results show that the proposed algorithms reduce the ACET of embedded applications further compared to state-of-the-art techniques.Keywords Cache locking· Probability Profile · ACET1 IntroductionCaches are known for their effectiveness in bridging the gap between processor and memory speed, but noto-rious for their unpredictability. With the utilization of cache, the Average-Case Execution Time (ACET) ofan application is improved dramatically. However, the unpredictable dynamic behavior of cache also makesthe estimation of an application’s ACET difficult and imprecise. ACET is an important metric for the designof some embedded systems[1, 2 ], especially for soft real-time embedded systems, such as image processing systems. With the use of cache, the ACET of an ap-plication is most likely to be overestimated, which in turn leads to an unnecessary increased hardware costof embedded systems.To remedy the unpredictability of cache, cache lock-ing technique is provided by a wide selection of modern processors, such as ARM9 series[3 ], MIPS32 series [4] and MCF5249[5]. Cache locking is to select andlock specific content of a program or data in a cache.For an application-specific embedded system, cache locking can effectively guarantee the precision of some cache hit/miss behaviors, thus a tighter ACET bound could be obtained. Embedded systems are mostly application-specific, which means that the applicationto be executed on a specific system is known before-hand. This characteristic enables researchers to utilizeJ Sign Process Syst the application’s properties to make some informed 2 Related Workdecisions before the execution. Therefore, in this paper,we utilize instruction cache (I-Cache) locking technique Several previous work has been done regarding theto find an estimable minimized ACET for an embedded cache locking problem in embedded systems. The most system based on the probability profiling information related works to this paper are [6, 7]. Both of theof the specific application running on the system. two works target to eliminate conflict miss rate within In this paper, a Probability Execution Flow Tree a cache set to reduce the ACET. Anand et al. [6 ] (PEFT) is introduced to model an embedded applica- devise a cost-benefit model to discover the memory ad- tion’s program with its probability profile information dresses to be locked in the I-Cache. Their experiments and application-specific information. Two schemes of confirm that cache locking is beneficial in improving cache locking are considered: static and dynamic. In average case performance. However, their cost/benefitthe static locking scheme, cache contents are loaded formulation contains some profile information whichat application start-up and remain unchanged until is hard to be obtained or not accurate. Additionally,the end. In the dynamic locking scheme, locked cache they focus on finding the beneficial blocks which are contents can be changed at specific reloading points mapped to the same cache set. This will lead to anbased on the runtime information. The cache can be unbalance between different sets, because some setsfully locked or partially locked. The I-Cache locking may contain more valuable blocks while others may problem in this paper aims to analyze the application not. Liang et al. in [7 ] introduce temporal reuse profile during its compilation time, and select a set of nodes to model the cost and benefit of locking memory blocksto be locked in the I-Cache statically or sets of nodes to in the cache. They propose an optimal algorithm and abe reloaded and locked in the I-Cache dynamically. The heuristic approach that use the temporal reuse profilegoal is to optimize the ACET of an embedded system. to determine the most beneficial memory blocks. How- The contributions of this paper are as follows: ever, each cache set is also analyzed individually intheir work. When implementing their methods, both1. Propose I-Cache locking techniques to minimizeof the two works use the trampolines [8] approach to the average execution time of embedded applica-introduce the locking instruction to the binary code so tions by exploring applications’ statistical profilethat the mapping addresses of the blocks will not be information and application-specific foreknowingchanged.information.Most other researchers utilize I-Cache locking in2. Prove that the static I-Cache locking problem forreal-time applications to guarantee a tighter estimation ACET reduction is an NP-Hard problem, and pro-of Worst-Case Execution Time (WCET). Puaut et al.pose a fully locking algorithm and a partially lock-propose some heuristic methods about I-Cache locking ing algorithm.on minimization of WCET and Worst-Case Utilization 3. Propose an off-line algorithm for the dynamic I-(WCU) [9, 10 ].Campoy et al. use genetic algorithms Cache locking by exploring runtime branching in-for both static locking [11] and dynamic locking [12]i n formation. The outputs of the algorithm are usedmultitask, preemptive real-time systems. Falk et al. [13 ] during runtime.take the changing of worse-case execution path into The remainder of this paper is organized as fol- consideration and adopt a greedy strategy to choose lows. Section 2 presents related work. Section 3 an- instructions into cache. Liu et al. [14] study the static alyzes the cache architecture and presents the PEFT I-Cache locking problem to minimize WCET for real- model of an application. In Section 4, the static I- time embedded systems. The problem is proved to Cache locking problem is formulated using the in- be NP-Hard and optimal algorithms are proposed for teger linear programming model and proved to be subsets of the general problem with special propertiesNP-Hard. Fully locking and partially locking algo- and patterns.rithms are proposed respectively. For the dynamic Scratchpad memory is an alternative to cache. TheI-Cache locking problem, an off-line algorithm us- allocation of code/data to the scratchpad memory ising the static locking results and branching informa- under software control. Significant effort has beention to obtain the dynamic locking decisions is pro- invested in developing efficient allocation techniques posed in Section 5. Cache conflict problem caused for scratchpad memories. [15 , 16 ] aim at reducing theby cache locking is discussed in Section 6.S ection7 ACET of programs through memory access profiles. shows the experimental results compared with previ- Puaut et al. [17] propose an algorithm for off-line con- ous work. Finally, concluding remarks are presented in tents selection of on-chip memory, supporting both the Section 8.locked cache and scratchpad memory. They find thatJ Sign Process Systthe performance of applications using the two types of memory are very close to each other in most cases.Little previous work has explored the statistical in-formation and the foreknowing information of em-bedded applications for the I-Cache locking problem.Liang et al.[18 ] utilize the probability information ofan application for cache configuration design whichis orthogonal to this paper’s work. In[19], an ap-proach for early branch resolution and subsequent fold-ing is presented. The application-specific informationis captured by the micro-architecture through a low-cost reprogrammable hardware, thus attaining the twin benefits of processor standardization and application-specific customization. Several work has used the fore-knowing information to provide scheduling methodsto improve timing performance for embedded systems [20– 22 ].Although there were a number of previous efforts on the cache locking problem, most of them focus on re-ducing the WCET[9–14 ]. The most related work to this paper primarily targets to eliminate conflict miss ratewithin one cache set to improve the ACET[6][7 ]. The unbalanced and random distribution of the beneficialblocks in different sets may weaken their methods. Inthis paper, we consider the problem from a differentangle. We first target to find the most efficient blockswithin the whole block sets to minimize ACET, then we use compilation techniques, such as padding and codepositioning[26] to avoid conflicts among these selected blocks. As concluded in[17 ] that using locked cacheand scratchpad memory are very close to each other in most cases, the algorithms proposed in this paper canalso be applied to scratchpad memory allocation.3 Cache Architecture and Task ModelThis section introduces the notations used in this paper concerning the cache architecture and task model.3.1 Cache ArchitectureCache locking technique is supported by several com-mercial processors[3 ,4], with different implementation methods. Some processors, for example Intel XScale[23] and MPC603E[5 ], allow developers to lock theentire cache. While others, for example RC64574[24], allow developers to lock only part of the cache. Somep rocessors[4 ,23] insert specific cache locking opera-tions into the application’s code to perform locking,while others[5, 24] use specific lock/freeze bits intheir cache control registers to lock each single cacheline content. In this paper, we assume the processor is equipped with an I-Cache with a total size of S.The proposed work is applied to a general architecture based on the above processors, resulting in a cache architecture with the following characteristics:1)I-Cache locking can be applied to each line of theI-Cache, which implies that the I-Cache can betotally locked or partially locked. This capability isprovided by several commercial processors[5, 24]. 2)The I-Cache can be loaded using a cache-fillinginstruction, which is provided by lots of processors[4 ,23 ]. During system start-up, a small routine isexecuted to pre-load the cache using the cache-filling instruction. After pre-loading the blocks, thecache is locked. Under the static locking scheme,the locked cache content will never change. Whileunder the dynamic locking scheme, the cache con-tent could be changed at specific reloading pointsby invoking these cache-filling instructions.3)The I-Cache can be either direct-mapped or set-associative. The mapping from memory space tothe I-Cache, as well as the possibility of cacheconflict within the locking selection are solved byprevious compilation techniques, such as proce-dure re-ordering[25 ], padding and code position-ing[26 ], as discussed in Section6.4)If the processor addresses an instruction that islocked in the I-Cache, this instruction will beserved from the I-Cache, resulting in fast accesstime (hit). If the processor addresses an instructionthat is not locked in the I-Cache, this instructionwill be served from the main memory, resulting inlonger access time (miss).5)This paper focuses on I-Cache locking. Data cacheis assumed to work in a normal fashion.3.2 PEFTIn this paper, a Probability Execution Flow Tree (PEFT) is used to model an embedded application.PEFT embodies the control flow of the application’scode and the profiling information of the applicationso that we can analyze it to find which part of the code should be selected into the I-Cache.Definition 1 A PEFT= (V, E, B) is a weighted tree, where V represents the set of nodes and E representsthe set of edges. B is the set of basic blocks in a program. Each b∈ B is a context-specific code block associated with three attributes: block_miss(b) is the single processing time when basic block b is not in the cache, block_hit(b) is the single processing time when basic block b is in the cache and block_s(b) is theJ Sign Process Systsize of basic block b . Node v ∈ V represents the real execution of a code block b∈ B under a certain context and therefore has two attributes: name(v) = b where b∈ B representing that basic block b is executed in this node and count(v) representing the average number of times b is executed in the current context. Edge evu ∈ E denotes a program control flow from node v to node u. Each edge has one attribute: edge_ prob(evu) which represents the execution probability of this flow. Forevery node v,u|evu∈E edge_ prob (evu) = 1.To generate a PEFT, an algorithm PEFT_CON isused, as shown in Algorithm 1. An application is firstrun in a profile tool, and the probabilities of edges are obtained and recorded in a probability matrix P[v][u]. Then, algorithm EFT_CON in[14]isusedtocon-struct an Execution Flow Tree (EFT)[14 ] (line 1). Fi-nally, we attach the statistical probability to each edge(line 2–4).A PEFT example is shown in Fig.1. Figure1( a)isa segment of the benchmark “Audio beam former”[28]and Fig.1(b) is the corresponding PEFT.Some important features about PEFT are as follows:1)The framework of PEFT is similar to the frame-work of CFG (Control Flow Graph) used in pre-vious research[10 ]. In Algorithm EFT_CON[14],each code line is scanned and different controlflows are processed accordingly. The sequentialcodes are the simplest and are treated as one ba-sic block. For branches, loops and routine calls,we process their bodies recursively and attach theEFTsub obtained to the main EFT. The differencebetween PEFT and CFG is that PEFT is explic-itly defined as a tree with probability informationand other attributes related to cache behavior. Abasic block can be one or more statements in theprogram depending on the context. For example,statement “exit(1)” in this example forms node 3in Fig.1(b).For simplicity, some of the call proce-if (!data_file) {print_usage();exit(1);}if (search_far_field == 1) {max_energy = search_far_field_angles(max_result, data_file, output_file, hamming);} else if (hill_climb == 1) {search_grid(source_location, data_file, output_file, hamming);max_result = (float*) malloc(ANGLE_ENERGY_WINDOW_SIZE*sizeof(float));} else {calc_single_pos(source_location, mic_locations, hamming, data_file, output_file);}exit(0);exit( )3print_usage( )21if (!data_file)6max_result = return of node 57search_far_field_angles( )8max_energy = return of node 75malloc( )exit( ) 12if (search_far_field == 1)49 if (hill_climb == 1)11 calc_single_pos( )14 exit( )10search_grid( )13exit( )95%5%31%69%73%27%(a) A segment of a benchmark [25].(b) Its PEFT.Figure 1 A segment of a benchmark and its PEFT.dures of the PEFT in Fig.1(b) are not presentedrecursively. For example, node 7 is an abstract pre-sentation of routine “search_far_field_angles()” .Algorithm EFT_CON does recursively process thesubroutines.2)In practical systems, the value of block_miss(b)orblock_hit(b) of a basic block b is not an accu-rate value if we consider timing anomalies, cacheand pipeline effects. It can be a range of values.In this paper, we use the average-case value ofblock_miss(b) orblock_hit(b) to form a modelfor solving the locking problem and comparingwith previous works. We run the benchmark sev-eral times using SimpleScalar[29 ] and obtain theprofiling information. From the cache miss/hit in-formation, we can obtain the estimation value ofblock_miss(b) orblock_hit(b).3)Node v has three additional attributesnode_miss(v), node_hit(v) and node_prob(v).node_miss(v) ornode_hit(v) is the real executiontime of node v and can be calculated asnode_miss(v) = block_miss(name(v)) × count (v)or node_hit(v)= block_hit(name(v)) × count(v),depending on whether name(v) is put inthe cache.node_ prob(v) is the executionJ Sign Process Systprobability of node v and can be calculatedas node_ prob(v)=node_prob(u)×edge_prob(euv),where u is the parent of v. It is easy todeduce that node_ prob(v) = node_prob(v0) ×edge_ prob(ev0 u1 )× edge_prob(eu 1 u2 )× ··· ×edge_ prob(euv) for node v along the path fromroot v0 to node v,wherenode_prob(v0) = 1.4)Algorithm EFT_CON gives the main flow of aloop. For a node v in a loop, the execution timeof its basic block could be different between itsfirst execution and each successive repetitionbecause of cache reusing[30]. The value ofnode_miss(v) can be calculated as node_miss(v) =block_miss(name(v)) + block_hit (name(v)) ×(count(v) − 1) which is its execution time underthe uncontrolled cache. The node_hit(v) is stillnode_hit(v) = block_hit(name(v)) × count(v).5)There is a procedure Duplicate() in AlgorithmEFT_CON. If a node v has an indegree(v) of atleast 2, Duplicate() instantiates the structure start-ing from v by indegree(v) times, which ensures thatthe output is a tree. For example, nodes 12, 13and 14 in Fig.1 (b) are duplicating nodes whichare introduced by the procedure Duplicate(). Eachduplicating substructure represents an invocationof the associated basic blocks (in this example,it is code line “exit(0)”), so they have the samename and count value, thus same node_miss(v) andnode_hit(v). With these duplicated nodes, thePEFT structure is still equivalent to EFG[13]or CFG[10] structure. From the definition andEFT_CON algorithm, we know that every path inan EFG or CFG is enumerated in a PEFT, whileevery path in a PEFT corresponds to one possiblepath in an EFG or CFG.3.3 ACET of a PEFTACET is the expected length of the root-leaf pathin a PEFT. Let Pi= (pi0 pi1 ... pil i )be a root-leaf path, where pi0, pi1,..., pili ∈ V and li is thenumber of edges on path Pi.Eachpath Pi has twoattributes length(Pi) and probability(Pi). length(Pi)is defined as the summation of the weights ofnodes on Pi, which represents the execution timeof this path.Let Wreal(v) = (1 − δ(name(v))) ×node_mi s s(v) + δ(name(v)) × node_hit(v),whereδ(name(v)) = 1 if name(v) is put in the cacheandδ(name(v)) = 0 otherwise. The length(Pi) is calculated as length(Pi) =li j=0 Wreal( pij). The other attributeprobability(Pi) represents the execution probability of this path and is calculated as probability(Pi) =li−1j=0 edge_ prob (epij pij+1 ).Table 1 Notations used in this paper.Notation Descriptionb A basic blockblock_s(b)Size of basic block bblock_miss(b)Execution time of basic block b when bis not in cacheblock_hit(b)Execution time of basic block b when bis in cacheblock_ prob(b)Execution weight of basic block beach_sa ving(b)ACET saving of basic block bv A nodename(v)Basic block in node vcount(v)Execution count of basic block in node v node_ prob(v)Execution probability of node vnode_miss(v)Execution time of node v when name(v)is not in cachenode_hit(v)Execution time of node v when name(v)is in cacheWreal(v)Real execution time of node v,is equal to node_miss(v) ornode_hit(v) evu An edgeedge_ prob(evu)Execution probability of edge evuPi A root-leaf pathlength(Pi)Execution time of path Piprobability(Pi)Execution probability of path PiDenote the total number of the root-leaf paths as|P|, then the ACET of a PEFT can be calculated as:|P|i=1length(Pi) × probability(Pi)(1) The notations are summarized in Table1.4 Static I-Cache LockingAs discussed in Section3.1, first we want to find a most efficient locking selection of memory blocks to mini-mize ACET of the application. In this section, we dis-cuss the static locking scheme, where cache contents are loaded at application start-up and remain unchangeduntil the end. We further consider two different locking strategies: fully locking and partially locking, depend-ing on whether or not the whole I-Cache is locked.4.1 Fully LockingThe fully locking means that the whole I-Cache is usedas the locked cache.J Sign Process Syst 4.1.1 Problem FormulationThe ACET minimization problem using static I-Cachelocking can be defined as follows. Given an I-Cache ofsize S and a PEFT representing a given program, theaim is to put a subset of basic blocks into the I-Cacheso that the total size of the chosen basic blocks doesnot exceed S and the ACET of the PEFT is minimized.With Formula1 discussed in Section3.3,w eformulatethe fully static I-Cache locking problem as an integerlinear programming (ILP) instance as follows:min|P|i=1length(Pi) × probability(Pi)s.t.⎧⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎩length(Pi) =li j=0(1 − δ(name(v))) × node_miss(v)+δ(name(v)) × node_hit(v)probability(Pi) =li−1j=0 edge_ prob (epij pij+1 )b∈Bblock_s(b) × δ(b) ≤ Sδ(b) ∈{0, 1}The variables in this ILP formulation areδ(b) foreach basic block which can only be equal to 0 or 1.The first two groups of equations give the calculationof length(Pi) and probability(Pi). The third inequalityis I-Cache size limitation. Because we use the lock-ing technique with the entire cache, every time weshould maintain this limitation no matter which kindof mapping is used. Otherwise, we will not be ableto put all the selected nodes to the cache. It is truethat some instructions may be mapped to the samecache line. This cache conflicts may happen with both direct-mapped cache and set-associative cache. We can apply some compiling techniques[26] to solve the cache conflict problem after we have decided which nodes to lock, which will be studied in Section6. The goal ofthe problem is to minimize the ACET for the PEFT by determiningδ(b) for each b ∈ B.4.1.2 Problem AnalysisFor each node v in a PEFT, define its set of outgo-ing edges as OutEdgesv ={evtm |e vtm ∈ E, 1 ≤ m ≤ Mv}, whereMv is the out-degree of node v.Let u representthe preceding node of v and ti represent the successive node of v for a path Pi which has v on it. The terms relating to Wreal(v) (node_miss(v) or node_hit(v))in Formula1 can be combined and further transformedas follows:Pi vWreal(v) × probability(Pi)= Wreal(v)×Pi v(edge_prob(epi0 pi1 )×···× edge_prob(euv)prob(evti )×··· × edge_prob(epili−1pili ))= Wreal(v) × (edge_prob(epi0 pi1 )×···×edge_ prob (eu v)×Pi v&ti=tm1≤m≤Mv(edge_prob(evtm )×···×edge_prob(epili−1pili )))= Wreal(v) × (edge_prob(epi0 pi1 )×··· × edge_prob(euv))= Wreal(v) × node_prob(v)As can be seen from the above, for every node v, the corresponding portion in Formula1 is Wreal(v) ×node_ prob(v).Formula1 can be expressed with regardto node v as:v∈VWreal(v) × node_prob(v)(2)In a PEFT, one basic block can be called by different nodes. In other words, name(u) could be equal toname(v) even when u = v. This scenario is denoted asreusing in this paper. Considering reusing, Formula2can be further transformed into:v∈VWreal(v) × node_prob(v)=v∈V((1 − δ(name(v))) × block_miss(name(v))+ δ(name(v))block_hit(name(v)))× count(v) × node_prob(v)=b∈B(((1 − δ(b)) × block_miss(b) + δ(b)× block_hit(b))v∈V& name(v)=b(count(v)× node_prob(v)))Let block_ prob(b) =v∈V& name(v)=b (count(v) ×node_ prob(v)). It is a constant when a PEFT is given.It represents the execution weight of basic block bappearing on different nodes in a PEFT. It may scaleJ Sign Process Systbigger than 1, so we do not say it is a probability.Finally, Formula1 is reduced to:b∈B((1 − δ(b)) × block_miss(b) + δ(b)× block_hit(b)) × block_prob(b)(3)Define each_sa ving(b) = (block_miss(b) − block_hit(b)) × block_prob(b) which is the ACET saving foran individual b∈ B. The static I-Cache locking prob-lem can be proved to be an NP-Hard problem.Theorem 1 The static I-Cache locking for ACET mini-mization is NP-Hard.Proof We prove that this problem is NP-Hard by areduction from the 0/1 knapsack problem. Given a0/1 knapsack instance, we have the finite set A withweight weight(a) and value value(a) for each a ∈ A,a value threshold K and a total weight limit W.Thestatic I-Cache locking problem is constructed as fol-lows. For each a∈ A,wecreateabasic block ba ∈B with each_sa ving(ba) = value(a) and block_s(ba) = weight(a). This instance can be constructed in polyno-mial time from the 0/1 knapsack instance.Define Total_time_unlock= b a∈B block_miss(b a)×block_ prob(ba).Formula3 can be transformed asTotal_time_unlock− b a∈B δ(b a) × each_saving(b a), whereδ(ba) = 1/0 means whether ba is put intocache or not. The deterministic version of staticI-Cache locking problem is to find whether there is aδ(ba) = 0/1 for every ba ∈ B whichcan achieve:Total_time_unlock− b a∈B δ(b a) ×each_sa ving(ba) ≤ Total_time_unlock − K and b a∈F block_s(b a) × δ(b a) ≤ S.This can be done if and only if there is aδ(a) = 0/1 for every a∈ A such that a∈A δ(a) × value(a) ≥ K and a∈A weight(a) × δ(a) ≤ W. Thus the desired δ(a)for every a∈ A exists for the instance of 0/1 knapsackif and only if aδ(ba) for every ba ∈ B exists for the cor-responding instance of static I-Cache locking problem.4.1.3 AlgorithmWhen we consider to lock all the I-Cache of size S,a dynamic programming method can be used to solvethe 0/1 knapsack problem optimally within pseudo-polynomial time[31]. In the static I-Cache locking problem, the transformed objective shown in Formula3 is not related to the PEFT’s structure. Therefore,we can treat basic blocks as items in the 0/1 knapsack problem and carry out dynamic programming similarly. The Algorithm SICL (Static I-Cache Locking for a PEFT) is shown in Algorithm 2.In Algorithm SICL,CalcFunProb(PEFT)isa procedure to calculate block_ prob(bi) and each_sa ving(bi) for each bi ∈ B (line1). Thechoice made under each circumstance is kept using anarray structure OPT[|B|][S + 1] (line 2). Each OPT[i][s] keeps the optimal solution for basicblock subset{b1, ··· bi} under cache size s withtwo variables: Sa ving and Cachable (lines 7–8, 11–12), which respectively represent the maximizedACET saving for this subset and whether or。

学年论文

泉州师范学院学年论文题目嵌入式系统与应用物理与信息工程学院通信工程专业 07级（2）班学生姓名张静学号 070307068 指导教师陈丹老师职称高级工程师完成日期 2010年08月25日教务处制嵌入式系统与应用【摘要】：基于嵌入式系统的概念，首先，分析嵌入式系统的技术特点以及嵌入式系统的支撑学科与平台；再着重说明嵌入式操作系统的特点；接着，介绍目前嵌入式系统一些流行的应用。

【关键词】：嵌入式系统；技术特点；开发技巧；嵌入式浏览器；学科体系【abstract】: Based on embedded system's concept ,firstly,Analysis of the technical characteristics of embedded systems and embedded systemplatform supporting disciplines .Secondly emphasizes the embeddedoperating system's characteristic .Finally, Describes some of thepopular embedded system applications.【keyword】: embedded system , technical features , Struts , Based on the embedded browser , accounting science system .目录第一章引言 (4)第二章嵌入式系统简介 (4)2.1嵌入式系统的定义 (4)2.2嵌入式系统的产生 (4)2.3嵌入式系统的组成 (5)2.3.1硬件层 (5)2.3.2中间层 (5)2.3.3系统软件层 (5)2.4嵌入式系统的特点 (6)2.5嵌入式操作系统的特点 (6)第三章嵌入式系统开发模式与流程 (7)3.1嵌入式系统开发模式 (7)3.2嵌入式系统开发流程 (7)第四章嵌入式系统应用及其应用实例（嵌入式浏览器） (8)4.1嵌入式系统的应用领域 (8)4.2嵌入式浏览器 (8)4.2.1桌面浏览器简介及其与嵌入式浏览器的区别： (8)4.2.2常见嵌入式浏览器 (8)4.2.3嵌入式浏览器的应用领域 (9)第五章嵌入式系统的发展前景 (9)5.1嵌入式系统的应用前景 (10)5.2网络互联成为必然趋势 (10)5.2精简系统内核、算法，降低功耗和软硬件成本 (11)5.3提供友好的多媒体人机界面 (11)第六章嵌入式系统学习 (11)6.1嵌入式系统的四个支柱学科 (11)6.1.1四个支柱学科的关系 (11)6.1.2领衔的微电子学科 (12)6.1.3为平台服务的计算机学科 (12)6.1.4广泛服务的电子技术学科 (12)6.1.5对象学科的最终出路 (12)6.2平台模式下的学科 (12)6.2.1平台的由来 (12)6.2.2嵌入式系统的平台模式 (12)6.2.3平台模式下的学科定位与分工 (13)参考文献 (13)第一章引言据估计，全球目前嵌入式软件市场的规模超过1000 亿美元，而且每年以超过30%的速度在增长。

走马灯实验设计论文(ARM)

广东岭南职业技术学院课程设计课题：走马灯实验论文--《嵌入式系统技术》指导教师：陈**广东岭南职业技术学院Guangdong Lingnan Institute of Technology姓名： Lee.Hm专业：08电子信息工程技术走马灯实验论文--《嵌入式系统技术》1、实验目的z熟悉A DS 开发环境调试环境。

z掌握简单的A RM 汇编指令的使用方法。

z掌握S3C2440A 的I/O 控制寄存器的配置。

z掌握A RM 汇编指令和C语言相互调用的方法2、实验设备z PC 机、ARM 仿真器、2440 实验箱、串口线。

3、实验内容z熟悉A RM 开发环境的建立。

z使用A RM 汇编和C语言设置G PIO 口的相应寄存器。

z编写跑马灯程序。

4、实验原理C 程序与汇编程序相互调用规则为了使单独编译的C 语言程序和汇编程序之间能够相互调用，必须为子程序间的调用规定一定的规则。

ATPCS ，即ARM ，Thumb 过程调用标准(ARM/Thumb Procedure Call Standard)，是A RM 程序和T humb 程序中子程序调用的基本规则，它规定了一些子程序间调用的基本规则，如子程序调用过程中的寄存器的使用规则，堆栈的使用规则，参数的传递规则等。

下面结合实际介绍几种A TPCS 规则，如果读者想了解更多的规则，可以查看相关的书籍。

1．基本A TPCS基本A TPCS 规定了在子程序调用时的一些基本规则，包括下面3方面的内容：(1)各寄存器的使用规则及其相应的名称。

(2)数据栈的使用规则。

(3)参数传递的规则。

相对于其它类型的A TPCS，满足基本A TPCS 的程序的执行速度更快，所占用的内存更少。

但是它不能提供以下的支持：ARM 程序和T humb 程序相互调用，数据以及代码的位置无关的支持，子程序的可重入性，数据栈检查的支持。

而派生的其他几种特定的ATPCS 就是在基本ATPCS 的基础上再添加其他的规则而形成的。

毕业设计(论文)样例-嵌入式专业本科

封面（在学校统一印制的封皮上打印相应的内容，以下为填写举例）论文题目简化的姓名刘刚学院东北大学东软信息学院专业指导教师张三备注2011年——作者指导教师：张三教授李四单位名称：嵌入式系统工程系专业名称：电子信息工程东北大学东软信息学院2011年6月Northeastern University Neusoft Institute of InformationJune 2011Supervisor:Professor Liu Hongyi Associate Supervisor:毕业设计（论文）任务书………………………。

-Ⅱ-东北大学东软信息学院毕业设计（论文） Abstract-Ⅲ-computer network for a long time.This article mainly discusses the QoS architecture, the principle of V oIP and the two related protocols: H.323, SIP. And then, introduce some QoS control mechanisms: packet classification, admission control, QoS route and queue management.………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………….Key words: V oIP QoS, H.323 SIP RSVP Diffserv RTCP, dynamic control admission-1-任务书 .......................................................................................................... I 摘要 .........................................................................................................II .. (III)第1章 ...................... 1 1.1 .. (1)1.2 (1)第2章关键技术介绍 (2)2.1 简 ......................................2 2.2 .. (2)第3章 (3)3.1 (3)3.1.1 软件功能构架 ···············································3.1.2 硬件功能框图 ··············································· 3.2 系统开发环境3.3 ·3.3.1 (4)3.3.2 (4)第4章系统设计 (6)4.1 设计指导思想和原则 (6)4.1.1 指导思想 ................................................................................................................ 6 4.1.2 设计原则 . (6)4.2 系统概述 (6)东北大学东软信息学院毕业设计（论文）目录4.3系统功能结构设计 (6)4.3.1实现单片机与外围存储器的技术连接 (6)4.3.2LED数码管的电路设计 (6)4.3.3rs232串行接口电路设计 (6)4.3.4键盘接口电路设计 (6)4.4系统UI界面设计 (6)4.5系统控制流程 (6)第5章系统实现 (7)5.1系统软件的实现 (7)5.1.1系统软件框图 (7)5.1.2系统程序流程图 (10)第6章系统测试 (12)6.1测试方案及测试用例 (12)6.1.1LED显示 (12)6.1.2键盘响应 (12)6.1.3串口收发 (12)6.1.3UI界面测试 (12)第7章结论 (13)附录1原理图 (14)附录2PCB图 (15)附录3实物图 (16)参考文献 (17)致谢 (18)-2-1章绪论说明：在绪论中简要说明设计（论文）工作的目的、意义、范围、研究设想、方法、选题依据等。

基于嵌入式GIS电力巡检系统设计[论文]

基于嵌入式GIS的电力巡检系统的设计【摘要】本文研究主要是基于嵌入式gis技术开发电力巡检系统。

经过认真的比较和实验,将windows mobile 5.0 作为便携式电力巡检仪的操作平台,它最大的优点就是人机界面操作以及应用软件开发都比较简单。

使用户在离开台式电脑时能够得到更高的工作效率。

因此,本文软件是基于windows mobile5.0平台,采用microsoft·net framework c#和esupermap开发,涉及到嵌入式技术、gis的数据模型与数据结构、数字地图可视化、gps的定位与导航等技术。

系统可实现采集管理空间数据,定位、导航和地理信息查询等功能,为实现电力巡检提供有效的技术途径。

【关键词】嵌入式gis电力巡检gpswindows mobile 5.0伴随着现代经济的迅速发展,目前国内输电线路出现了电压等级多、输电线路长、地域分布广的特点;因此,给工作人员在管理和排除故障等方面带来了许多困难。

及时发现线路和设备存在的问题并进行修理,是保障人们生活安居乐业,企业生产正常运行的重要环节,是工作人员工作的重中之重,所以电力线路的巡检工作是必不可少的,并且是非常重要的。

通过巡视检查可以随时发现设备缺陷,线路的安全与否和存在的隐患。

与城市电网相比较,农村电网具有地理环境复杂、点多面广、负荷分散、供电线路长等特点,给工作人员在线路管理和修理、维护方面带来更大的困难,因此,利用比较合理的技术方法,改善农村地区配电网线路巡检的手段,对于提高农村配电网络的可靠性和安全性具有重要的现实意义。

在以往的巡检系统中,对于输电线路的故障检测是由线路巡检人员通过现场进行排查,在排查的同时对于有问题的线路进行记录,待巡检结束后,对于排查出的故障线路或设备上报到上一级,以便上级管理人员分派人员进行特定范围内的检修,但是由于是人工的现场排查线路或设备故障,就有可能造成错检、漏检或者是对于排查出的故障因为某种原因而不能及时的上报到上一级而延误了故障的维修与维护;还有可能的情况是在线路出现了故障以后,才会有人去检测,检测完毕后,提交报告,上级才会派人进行维修,这样,巡检人员的工作量是非常大的并且他们的工作效率也是非常低的。

Cortex-M3论文：Cortex-M3嵌入式系统自调节差值脉冲编码调制(ADPCM)语音播报

Cortex-M3论文：Cortex-M3 嵌入式系统自调节差值脉冲编码调制(ADPCM) 语音播报【中文摘要】本文主要从硬件和软件方面阐述了基于ARM Cortex-M3的嵌入式系统的设计与实现。

首先阐述了系统的总体需求和设计指标,接着具体描述了硬件设计方案：包括总体硬件框架、MCU 最小系统模块、USB模块、温度检测模块、音频模块等的设计及系统的PCB实现；之后分析了系统的软件框架结构,包括在Cortex架构的硬件平台上配置uCOS-Ⅱ操作系统的过程、介绍ADPCM算法并设计其在本应用中的压缩与解压函数、设计语音播报应用程序等内容。

本文通过一个从底向上的实例的设计,介绍了基于ARM Cortex内核系统的设计方法。

经验证,软硬件系统运行稳定,语音播报顺利。

【英文摘要】In this paper, design and implementation of embedded system based on ARM Cortex-M3 is elaborated from two aspects:hardware system design and software program design. Firstly, the paper analyses the requirement and the designing principle of this system. Then follow the hardware’smain-framework structure and designing details, including the scheme of MCU minimum system、USB、temperature testing module and audio module. The author also shows the PCB realization in the same chapter. Secondly, the paper gives th...【关键词】Cortex-M3 嵌入式系统自调节差值脉冲编码调制(ADPCM) 语音播报【采买全文】1.3.9.9.38.8.4.8 1.3.8.1.13.7.2.1同时提供论文写作定制和论文发表服务.保过包发.【说明】本文仅为中国学术文献总库合作提供，无涉版权。

基于ARM嵌入式图像处理系统设计与实现论文

目录摘要 (2)1 引言 (1)1.1 课程设计的意义 (1)1.2 课程设计的目的 (1)2 系统设计原理 (2)2.1图像处理技术原理和成像原理 (2)2.2 BMP文件格式简介 (2)2.3 图像显示原理 (3)3 开发环境简介及搭建 (5)3.1 硬件平台 (5)3.2 系统软件平台构建 (5)3.3 LCD显示模块 (5)4 系统设计的与具体实现 (7)4.1 BMP文件的读入 (7)4.2 图像增强算法设计 (7)4.3 图像分割算法设计 (8)4.4 图像平滑 (8)4.5 图像缩放（平移以及转置） (10)5 程序主要源代码分析 (12)5.1 图像数据存储的主程序如下: (12)5.3 图像平移主要代码 (15)5.4 图像缩放主要代码 (18)5.5 转置图像主要代码 (21)6 运行测试结果 (23)6.1图像平移效果 (23)6.2图像转置效果 (24)6.3图像的缩放效果 (24)7 总结 (25)参考文献 (26)基于ARM嵌入式图像处理系统设计与实现学生姓名：王涛指导老师：蔡烁摘要针对现在的过程检测的实时需求，设计出一种成本低，功能始终的图像处理采集系统。

该系统以ARM7（S3C44BOX）为核心并配上外围电路实现图像处理功能，在加上多种通讯接口设计的图像传输通道，然后加入SD卡接口用于提取图像数据。

最后基于uC/OS-Ⅱ嵌入式操作系统设计了一种图像处理方法，在系统中实现了图像增强、图像分割和目标定个位。

实验表明，该系统能够很好地解决在线处理功能的实时问题，图像处理的准确率也满足了过程检测系统的要求，而且实现简单，成本比较低，特别适合对于功耗、体积要求较严格的过程检测系统。

关键词ARM；图像处理系统；图像增强；目标定位1 引言1.1 课程设计的意义图像处理技术在工业自动化、仪表检测安全、以及安全、消费电子、医学中被越来越广泛的应用。

在现代战争中，利用图像进行精确制导、火控、无人飞机的电视导航等，在国防中也受到了高度的重视。

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嵌入式系统论文 Company number：【0089WT-8898YT-W8CCB-BUUT-202108】嵌入式系统论文

专业班级：学生姓名：学号：一个嵌入式系统装置一般都由嵌入式计算机系统和执行装置组成嵌入式计算机系统是整个嵌入式系统的核心，由硬件层、中间层、系统软件层和应用软件层组成。执行装置也称为被控对象，它可以接受嵌入式计算机系统发出的控制命令，执行所规定的操作或任务。执行装置可以很简单，如手机上的一个微小型的电机，当手机处于震动接收状态时打开；也可以很复杂，如ＳＯＮＹ智能机器狗，上面集成了多个微上控制电机和多种传感器，从而可以执行各种复杂的动作和感受种状态信息。下面对嵌入式计算机系统的组成进行介绍。一、硬件层硬件层中包含嵌入式微处理器、存储器（SDRAM、ROM、Flash等）、通用设备接口和I/O接口（A/D、D/A、I/O等）。在一嵌入式处理器基础上添加电源电路、时钟电路和存储器电路，就构成了一个嵌入式核心控制模块。其中操作系统和应用程序都可以固化在ＲＯＭ中。二、中间层硬件层与软件层之间为中间层，也称为硬件抽象层（Hardware Abstract Layer,HAL）或者板级支持包（Board Support Package,BSP），它半系统上层软件与底层硬件分离开来，使系统的底层驱动程序与硬件无关，上层软件开发人员无需关心底层硬件的具体情况，根据BSP层提供的接口即可进行开发。该层一般包含相关底层硬件的初始化、数据的输入/输出操作和硬件设备的配置功能。实际上,BSP是一个介于操作系统和底层硬件之间的软件层次，包括了系统中大部分与硬件联系紧密的软件模块。设计一个完整的BSP需要完成两部分工作：嵌入工系统的硬件初始化的BSP功能，设计硬件相关的设备驱动。三、系统软件层系统软件层由实时多任务操作系统（Real-time Operation System,RTOS）、文件系统、图形用户接口(Graphic User Interface,GUI)、网络系统及通用组件模块组成。RTOS是嵌入式应用软件的基础和开发平台。

嵌入式系统的主要应用嵌入式系统技术具有非常广阔的应用前景，其应用领域可以包括：工业控制、交通管理、信息家电、家庭智能系统、POS网络及电子商务、环境工程与自然、机器人。这些应用中，可以着重于在控制方面的应用。就远程家电控制而言，除了开发出支持TCP/IP的嵌入系统之外，家电产品控制协议也需要制订和统一，这需要家电生产厂家来做。同样的道理，所有基于网络的远程控制协议也需要与嵌入式系统之间实现接口，然后再由嵌入式系统来控制并通过网络实现控制。所以，开发和探试嵌入式系统有着十分重要的意义。相对于其他的领域，机电产品可以说是嵌入式系统应用最典型最广泛的领域之一。从最初的单片机以现在的工控机、SOC在种机电产品中均有着巨大的市场。工业设备是机电产品中最大的一类，在目前的工业控制设备中，工控机的使用非常广泛，这些工控机一般采用的是工业级的处理器和各种设备，其中以X86的MPU最多。家电行业是嵌入式应用的另一大行业，我们传统的电视，电冰箱当然其中也嵌有处理器，但是这些处理器只是在控制方面应用。而现在只有按钮、开关的电器显然已经不能满足人们的日常需求，具有用户界面，能远程控制，智能管理的电器是未来的发展趋势。到我们身边。

嵌入式微处理器的的种类嵌入式微处理器的核心是嵌入微处理器，嵌入式微处理器与通用CPU最大的不同在于嵌入式微处理器大多工作在为特定用户群所专用设计的系统中，它将通用CPU许多由板卡完成的任务集成在芯片内部，从而有利于嵌入式系统在设计时趋于小型化，同时还具有很高的效率和可靠性。嵌入式微处理器的体系结构可以采用冯.诺依曼体系或哈佛体系结构；指令系统可以选用精简指令系统（Redyced Instryction Set Computer,RISC）和复杂指令系统CISC (Complex instruction Set Computer,CISC)。RSIC计算机在通道中只包含最有用的指令。确保数据通道快速执行每一条指令，从而提高了执行效率并使用CPU硬件结构设计变得更为简单。嵌入式微处理器有各种不同的体系统，即使在同一体系中也可能具有不同的时钟频率和数据总宽度，或集成了不同的外设和接口。据不完全统计，目前全世界嵌入式微处理器已经超过1000多种，体系结构有30多个系列，其中主流的体系有ARM、MIPS、PowerPC、X86和SH等。但与全球PC市场不同的是，没有一种嵌入式微处理器可以主导市场，仅以32位的产品而言，就有100种以的嵌入式微处理器。嵌入式微处理器的选择是根据具体的应用而决定的。嵌入式系统的发展现状和发展趋势随着信息化，智能化，网络化发展，嵌入式系统技术也将获得广阔发展空间。美国着名未来学家尼葛洛庞帝99年1月访华时预言，4~5年后嵌入式智能（电脑）工具将是PC和因特网之后最伟大的发明。我国着名嵌入式系统专家沈绪榜院士98年11月在武汉全国第11次微机学术交流会发表的《计算机的发展与技术》一文中，对未来10年以嵌入式芯片为基础的计算机工业进行了科学的阐述和展望。1999年世界电子产品产值已超过12000亿美元，2000年达到13000亿美元。信息时代，数字时代使得嵌入式产品获得了巨大的发展契机，为嵌入式市场展现了美好的前景，同时也地嵌入式生产厂商提出了新的挑战，从中我们可以看出未来嵌入式系统的几大发展趋势；一、嵌入式开发是一项系统工程，因此要求嵌入式系统厂商不仅要提供嵌入式软硬件系统本身，同时还需要提供强大的硬件开发工具和软件包支持。二、网络化、信息化的要求随着因特网技术的成熟、带宽的提高日益提高，使得以往单一功能的设备如电话、手机、冰箱、微波炉等功能不再单一，结构更加复杂三、网络互联成为必然趋势。未来的嵌入式设备为了适应网络发展的要求，必然要求硬件上提供各种网络通信接口。四、精简系统内核，算法，降低功耗和软硬件成本。五、提供友好的多媒体人机界面。嵌入式设备能与用户亲密接触，最重要的因素就是它能提供非常友好的用户界面。嵌入式系统的分类、特点和作用由于嵌入系统由硬件和软件两大部分组，所以其分类也可以从硬件和软件进行划分。从硬件方面来讲，各式各样的嵌入式处理器是嵌入式系统硬件中的最核心的部分，而目前世界上具有嵌入式功能特点的处理器已经超过1000种，流行体系结构包括MCU，MPU等30多个系列。鉴于嵌入式系统广阔的发展前景，很多半导体制造商都大规模生产嵌入式处理器，并且公司自主设计处理器也已经成为了未来嵌入式领域的一大趋势，其中从单片机、DSP到FPGA有若各式各样的品种上，速度越来越快，性能越来越强，价格也越来越低。目前嵌入式处理的寻址空间可以从64KB到16MB，处理速度最快可以达到2000MIPS,封装从８个引脚到144个引脚个不等。从软件方面划分，主要可以依据操作系统的类型。目前嵌入式系统的软件主要有两大类：实时系统和分时系统。其中实时系统又分为两类：硬实时系统和软实时系统。实时嵌入系统是为执行特定功能而设计的，可以来严格的按时序执行功能。其最大的特征就是程序的执行具有确定性。在实时系统中，如果系统在指定的时间内未能实现某个确定的任务，会导致系统的全面失败，则系统被称为硬实时系统。而在软实时系统中，虽然响应时间同样重要，但是超时却不会导致致命错误。一个硬实时系统往往在硬件上需要添加专门用于时间和优先级管理的控制芯片，而软实时系统则主要在软件方面通过编程实现时限的管理。比如Windows CE就是一个多任备置分时系统，而Ucos-II则是典型的实时操作系统。当然，除了上述分类之外，还有许多其他分类方法，比如从应用方面分为工业应用和消费电子等，在这里就不一一累述了。嵌入式系统的核心是嵌入式微处理器。嵌入式微处理器一般就具备以下4个特点；一、对实时任务有很强的支持能力，能完成多任务并且有较短的中断响应时间，从而使内部的代码和实时内核心的执行时间减少到最低限度。二、具有功能很强的存储区保护功能。这是由于嵌入式系统的软件结构已模块化，而为了避免在软件模块之间出现错误的交叉作用，需要设计强大存储区保护功能，同时也有利于软件诊断。三、可扩展的处理器结构，以能最迅速地开发出满足应用的最高性能的嵌入式微处理器。四、嵌入式微处理器必须功耗很低，尤其是用于便携式的无线及移动的计算和通信设备中靠电池的嵌入式系统更是如此，如需要功耗只有nW甚至uW级。而嵌入式系统的重要特征则是如下：一、系统内核小。由于嵌入式系统一般是应用于小型电子装置的，系统资源相对有限，所以内核较之传统的操作系统要小得多。比如Enea公司的OSE分布式系统，内核只有5K，而Windows的内核简直没有可比性。二、专用性强。嵌入式系统的个性化很强，其中的软件系统和硬件的结合非常紧密，一般要针对硬件进行系统的移植，即使在同一品牌、同一系列的产品中也需要根据系统硬件的变化和增减不断进行修改。同时针对不同的任务，往往需要对系统进行较大更改，程序的编译下载要和系统相结合，这种修改和通用软件的“升级”是完全两个概念。三、系统精简。嵌入式系统一般没有系统软件和应软件的明显区分，不要求其功能设计及实现上过于复杂，这样一方面利于控制系统成本，同时也利于实现系统安全。四、高实时性的系统软件（OS）是嵌入式软件的基本要求。而且软件要求固态存领教，以提高速度；软件代码要求高质量和高可靠性。