Multistage Interconnection Networks Reliability

合集下载

G.703(数字系列接口物理电气特性)

INTERNATIONAL TELECOMMUNICATION UNIONCCITT G.703 THE INTERNATIONALTELEGRAPH AND TELEPHONECONSULTATIVE COMMITTEEGENERAL ASPECTS OF DIGITALTRANSMISSION SYSTEMSTERMINAL EQUIPMENTSPHYSICAL/ELECTRICAL CHARACTERISTICS OF HIERARCHICAL DIGITAL INTERFACES Recommendation G.703Geneva, 1991FOREWORDThe CCITT (the International Telegraph and Telephone Consultative Committee) is the permanent organ of the International Telecommunication Union (ITU). CCITT is responsible for studying technical, operating and tariff questions and issuing Recommendations on them with a view to standardizing telecommunications on a worldwide basis.The Plenary Assembly of CCITT which meets every four years, establishes the topics for study and approves Recommendations prepared by its Study Groups. The approval of Recommendations by the members of CCITT between Plenary Assemblies is covered by the procedure laid down in CCITT Resolution No. 2 (Melbourne, 1988).Recommendation G.703 was prepared by Study Group XVIII and was approved under the Resolution No. 2 procedure on the 5th of April 1991.___________________CCITT NOTES1) In this Recommendation, the expression “Administration” is used for conciseness to indicate both a telecommunication Administration and a recognized private operating agency.2) A list of abbreviations used in this Recommendation can be found in Annex C.ITU 1991All rights reserved. No part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the ITU.Recommendation G.703PHYSICAL/ELECTRICAL CHARACTERISTICS OF HIERARCHICAL DIGITAL INTERFACES(Geneva, 1972; further amended)The CCITT,consideringthat interface specifications are necessary to enable the interconnection of digital network components (digital sections, multiplex equipment, exchanges) to form an international digital link or connection;that Recommendation G.702 defines the hierarchical levels;that Recommendation G.704 deals with the functional characteristics of interfaces associated with network nodes;that I.430-Series Recommendations deal with the layer 1 characteristics for ISDN user-network interfaces, recommendsthat physical and electrical characteristics of the interfaces at hierarchical bit rates be as described in this Recommendation.Note 1– The characteristics of interfaces at non-hierarchical bit rates, except n⨯ 64 kbit/s interfaces conveyed by 1544 kbit/s or 2048 kbit/s interfaces, are specified in the respective equipment Recommendations.Note 2– The jitter specifications contained in the following §§6, 7, 8 and 9 are intended to be imposed at international interconnection points.Note 3– The interfaces described in §§ 2 to 9 correspond to the ports T (output port) and T' (input port) as recommended for interconnection in CCIR Recommendation AC/9 with reference to Report AH/9 of CCIR Study Group 9. (This Report defines the points T and T'.)Note 4–For signals with bit rates of n⨯64 kbit/s (n= 2 to 31) which are routed through multiplexing equipment specified for the 2048 kbit/s hierarchy, the interface shall have the same physical/electrical characteristics as those for the 2048 kbit/s interface specified in § 6. For signals with bit rates of n⨯64 kbit/s (n= 2 to 23) which are routed through multiplexing equipment specified for the 1544 kbit/s hierarchy, the interface shall have the same physical/electrical characteristics as those for the 1544 kbit/s interface specified in § 2.1 Interface at 64 kbit/s1.1 Functional requirements1.1.1 The following basic requirements for the design of the interface are recommended:1.1.2 In both directions of transmission, three signals can be carried across the interface:–64 kbit/s information signal,–64 kHz timing signal,–8 kHz timing signal.Recommendation G.703 1Note 1– The 64 kbit/s information signal and the 64 kHz timing signal are mandatory. However, although an 8 kHz timing must be generated by the controlling equipment (e.g. PCM multiplex or time slot access equipment), it should not be mandatory for the subordinate equipment on the other side of the interface to either utilize the 8 kHz timing signal from the controlling equipment or to supply an 8 kHz timing signal.Note 2– The detection of an upstream fault can be transmitted across the 64 kbit/s interface by transmitting an alarm indication signal (AIS) towards the subordinate equipment.1.1.3 The interface should be bit sequence independent at 64 kbit/s.Note 1– An unrestricted 64 kbit/s signal can be transmitted across the interface. However, this does not imply that unrestricted 64 kbit/s paths are realizable on a global basis. This is because some Administrations presently have or are continuing to install extensive networks composed of digital line sections whose characteristics do not permit the transmission of long sequences of 0s. (Recommendation G.733 provides for PCM multiplexes with characteristics appropriate for such digital line sections.) Specifically for octet timed sources, in 1544 kbit/s digital networks it is required that at least one binary 1 should be contained in any octet of a 64 kbit/s digital signal. For a bit stream which is not octet timed no more than 7 consecutive 0s should appear in the 64 kbit/s signal.Note 2– Although the interface is bit sequence independent, the use of the AIS (all 1s bit pattern) may result in some minor restrictions for the 64 kbit/s source. For example, an all 1s alignment signal could result in problems.1.1.4 Three types of envisaged interfaces1.1.4.1 Codirectional interfaceThe term codirectional is used to describe an interface across which the information and its associated timing signal are transmitted in the same direction (see Figure 1/G.703).T1818700-92 Information signalTiming signal EquipmentEquipmentFIGURE 1/G.703Codirectional interface1.1.4.2 Centralized clock interfaceThe term centralized clock is used to describe an interface wherein for both directions of transmission of the information signal, the associated timing signals are supplied from a centralized clock, which may be derived for example from certain incoming line signals (see Figure 2/G.703).Note– The codirectional interface or centralized clock interface should be used for synchronized networks and for plesiochronous networks having clocks of the stability required (see Recommendation G.811) to ensure an adequate interval between the occurrence of slips.2 Recommendation G.703T1818710-92 Information signalTiming signal EquipmentEquipmentFIGURE 2/G.703Centralized clock interface1.1.4.3 Contradirectional interfaceThe term contradirectional is used to describe an interface across which the timing signals associated with both directions of transmission are directed towards the subordinate equipment (see Figure 3/G.703).T1818720-92 Information signalTiming signal Controlling equipmentSubordinateequipmentFIGURE 3/G.703Contradirectional interface1.2 Electrical characteristics1.2.1 Electrical characteristics of 64 kbit/s codirectional interface1.2.1.1 General1.2.1.1.1 Nominal bit rate: 64 kbit/s.1.2.1.1.2 Maximum tolerance of signals to be transmitted through the interface: 100 ppm.1.2.1.1.3 64 Hz and 8 kHz timing signal to be transmitted in a codirectional way with the information signal.1.2.1.1.4 One balanced pair for each direction of transmission; the use of transformers is recommended.Recommendation G.703 34 Recommendation G.7031.2.1.1.5 Code conversion rulesStep 1 – A 64 kbit/s bit period is divided into four unit intervals.Step 2 – A binary one is coded as a block of the following four bits:1 1 0 0Step 3 – A binary zero is coded as a block of the following four bits:1 0 1 0Step 4 – The binary signal is converted into a three-level signal by alternating the polarity of consecutive blocks.Step 5 – The alternation in polarity of the blocks is violated every 8th block. The violation block marks the last bit in an octet.These conversion rules are illustrated in Figure 4/G.703.718013451617180110201T1818730-92FIGURE 4/G.703Illustration of the conversion rulesOctet timingStep 5Step 4Steps 1 - 364 kbit/s dataBit number Violation Violation1.2.1.1.6 Overvoltage protection requirementSee Annex B.1.2.1.2 Specifications at the output portsSee Table 1/G.703.1.2.1.3 Specifications at the input portsThe digital signal presented at the input port shall be as defined above but modified by the characteristics of the interconnecting pairs. The attenuation of these pairs at a frequency of 128 kHz should be in the range 0 to 3 dB. This attenuation should take into account any losses incurred by the presence of a digital distribution frame between the equipments.The return loss at the input ports should have the following minimum values:To provide nominal immunity against interference, input ports are required to meet the following requirements:A nominal aggregate signal, encoded as a 64 kbit/s codirectional signal and having a pulse shape as defined in the pulse mask, shall have added to it an interfering signal with the same pulse shape as the wanted signal. The interfering signal should have a bit rate within the limits specified in this Recommendation, but should not be synchronous with the wanted signal. The interfering signal shall be combined with the wanted signal in a combining network, with an overall zero loss in the signal path and with the nominal impedance 120 ohms to give a signal-to-interference ratio of 20 dB. The binary content of the interfering signal should comply with Recommendation O.152 (211– 1 bit period). No errors shall result when the combined signal, attenuated by up to the maximum specified interconnecting cable loss, is applied to the input port.Note– If the symmetrical pair is screened, the screen shall be connected to the earth at the output port, and provision shall be made for connecting the screen of the symmetrical pair to earth, if required, at the input port.1.2.2 Electrical characteristics of the 64 kbit/s centralized clock interface1.2.2.1 General1.2.2.1.1 Nominal bit rate: 64 kbit/s. The tolerance is determined by the network clock stability (see Recommendation G.811).1.2.2.1.2 For each direction of transmission there should be one symmetrical pair carrying the data signal. In addition, there should be symmetrical pairs carrying the composite timing signal (64 kHz and 8 kHz) from the central clock source to the office terminal equipment. The use of transformers is recommended.1.2.2.1.3 Overvoltage protection requirementSee Annex B.Recommendation G.703 56 Recommendation G.703TABLE 1/G.703Note– For the time being these values are valid only for equipments of the 2 Mbit/s hierarchy.1.2.2.1.4 Code conversion rulesThe data signals are coded in AMI code with a 100% duty ratio. The composite timing signals convey the 64 kHz bit-timing information using AMI code with a 50% to 70% duty ratio and the 8 kHz octet-phase information by introducing violations of the code rule. The structure of the signals and their nominal phase relationships are shown in Figure 6/G.703.The data stream at the output ports should be timed by the leading edge of the timing pulse and the detection instant at the input ports should be timed by the trailing edge of each timing pulse.1.2.2.2 Characteristics at the output portsSee Table 2/G.703.Recommendation G.703 78Recommendation G.7036781234567812T1818750-92FIGURE 6/G.703Signal structures of the 64-kbit/s central clock interface at office terminal output ports Octet startOctet startBit number DataTimingTABLE 2/G.703Note 1 – The choice between the set of parameters a) and b) allows for different office noiseenvironments and different maximum cable lengths between the three involved office equipments. Note 2 – For the time being these values are valid only for equipments of the 2 Mbit/s hierarchy.1.2.2.3 Characteristics at the input portsThe digital signals presented at the input ports should be as defined above but modified by the characteristics of the interconnecting pairs. The varying parameters in Table 2/G.703 will allow typical maximum interconnecting distances of 350 to 450 m. 1.2.2.4 Cable characteristicsThe transmission characteristics of the cable to be used are subject to further study. 1.2.3 Electrical characteristics of 64 kbit/s contradirectional interface 1.2.3.1General1.2.3.1.1 Bit rate: 64 kbit/s.1.2.3.1.2 Maximum tolerance for signals to be transmitted through the interface: 100 ppm.1.2.3.1.3 For each direction of transmission there should be two symmetrical pairs of wires, one pair carrying the data signal and the other carrying a composite timing signal (64 kHz and 8 kHz). The use of transformers is recommended. Note – If there is a national requirement to provide a separate alarm signal across the interface, this can be done by cutting the 8 kHz timing signal for the transmission direction concerned, i.e., by inhibiting the code violations introduced in the corresponding composite timing signal (see below). 1.2.3.1.4Code conversion rulesThe data signals are coded in AMI code with a 100% duty ratio. The composite timing signals convey the 64 kHz bit-timing information using AMI code with a 50% duty ratio and the 8 kHz octet-phase information by introducing violations of the code rule. The structures of the signals and their phase relationships at data output ports are shown in Figure 7/G.703.6781234567812T1818760-92FIGURE 7/G.703Signal structures of the 64-kbit/s contradirectional interface at data output ports Octet startOctet startBit number DataTimingThe data pulses received from the service (e.g. data or signalling) side of the interface will be somewhat delayed in relation to the corresponding timing pulses. The detection instant for a received data pulse on the line side(e.g. PCM) of the interface should therefore be at the leading edge of the next timing pulse.1.2.3.1.5 Specifications at the output portsSee Table 3/G.703.TABLE 3/G.703Note– For the time being these values are valid only for equipments of the 2 Mbit/s.V1,00,5FIGURE 8/G.703Mask of the data pulse of the 64-kbit/s contradirectional interfaceNote 1 – When one pulse is immediately followed by another pulse of the opposite polarity, the time limits at the zero-crossing between the pulses should be ± 0.8 μs.Note 2 – The time instants at which a transition from one state to another in the data signal may occur are determined by the timing signal. On the service (e.g. data or signalling) side of the interface it is essential that these transitions are not initiated in advance of the timing instants given by the received timing signal.0,51,0FIGURE 9/G.703Mask of the timing pulse of the 64-kbit/s contradirectional interface V0.51.01.2.3.1.6 Specifications at the input portsThe digital signals presented at the input ports should be as defined above but modified by the characteristics of the interconnecting pairs. The attenuation of these pairs at a frequency of 32 kHz should be in the range 0 to 3 dB. This attenuation should take into account any losses incurred by the presence of a digital distribution frame between the equipments.The return loss at the input ports should have the following minimum values:To provide nominal immunity against interference, input ports are required to meet the following requirement:A nominal aggregate signal, encoded as a 64 kbit/s contra-directional signal and having a pulse shape as defined in the pulse mask, shall have added to it an intefering signal with the same pulse shape as the wanted signal. The interfering signal should have a bit rate within the limits specified in this Recommendation, but should not be synchronous with the wanted signal. The interfering signal shall be combined with the wanted signal in a combining network, with an overall zero loss in the signal path and with the nominal impedance 120 ohms to give a signal-to-interference ratio of 20 dB. The binary content of the interfering signal should comply with Recommendation O.152 (211– 1 bit period). No errors shall result when the combined signal, attenuated by up to the maximum specified interconnecting cable loss, is applied to the input port.Note 1– The return loss specification for both the data signal and the composite timing signal input ports.Note 2– If the symmetrical pairs are screened, the screens shall be connected to the earth at the output port, and provision shall be made for connecting the screens of the symmetrical pairs to earth, if required, at the input port.1.2.3.1.7 Overvoltage protection requirementSee Annex B.2 Interface at 1544 kbit/s2.1 Interconnection of 1544 kbit/s signals for transmission purposes is accomplished at a digital distribution frame.2.2 The signal shall have a bit rate of 1544 kbit/s ± 50 parts per million (ppm).2.3 One symmetrical pair shall be used for each direction of transmission.2.4 Test load impedance shall be 100 ohms, resistive.2.5 An AMI (bipolar) code or B8ZS code shall be used. Connecting line systems require suitable signal content to guarantee adequate timing information. This can be accomplished either by use of B8ZS code, scrambling or by permitting not more than 15 spaces between successive marks and having an average mark density of at least 1 in 8.2.6 The shape for an isolated pulse measured at the distribution frame shall fall within the mask in Figure 10/G.703 and meet the other requirements of Table 4/G.703. For pulse shapes within the mask, the peak undershoot should not exceed 40% of the peak pulse (mark).2.7 The voltage within a time slot containing a zero (space) shall be no greater than either the value produced in that time slot by other pulses (marks) within the mask of Figure 10/G.703 or ± 0.1 of the peak pulse (mark) amplitude, whichever is greater in magnitude.3 Interface at 6312 kbit/s3.1 Interconnection of 6312 kbit/s signals for transmission purposes is accomplished at a digital distribution frame.3.2 The signal shall have a bit rate of 6312 kbit/s ± 30 ppm.3.3 One symmetrical pair of characteristic impedance of 110 ohms, or one coaxial pair of characteristic impedance of 75 ohms shall be used for each direction of transmission.3.4 Test load impedance shall be 110 ohms resistive or 75 ohms resistive as appropriate.3.5 A pseudo-ternary code shall be used as indicated in Table 5/G.703.3.6 The shape for an isolated pulse measured at the distribution frame shall fall within the mask either of Figure 11/G.703 or of Figure 12/G.703 and meet the other requirements of Table 5/G.703.3.7 The voltage within a time slot containing a zero (space) shall be no greater than either the value produced in that time slot by other pulses (marks) within the mask of Figure 11/G.703, or ± 0.1 of the peak pulse (mark) amplitude, whichever is greater in magnitude.– —8– —484 —2— — —80VT1818790-92FIGURE 10/G.703Pulse mask for interface at 1544 kbit/sT Time-slot widthTimeP u l s e a m p l i t u d eTABLE 4/G.703Digital interface at 1544 kbits a)a) The pulse mask for 1st order digital interface is shown in Figure 10/G.703 b) See § 2.5 in the text. c) See Annex A.d)The signal level is the power level measured in a 3 kHz bandwidth at the point where the signal arrives at the distribution frame for an all 1s pattern transmitted.TABLE 5/G.703Digital interface at 6312 kbit/s a)a) The pulse mask for 2nd order digital interface is shown in Figures 1/G.703 and 12/G.703.b) See Annex A.4 Interface at 32 064 kbit/s4.1 Interconnection of 32 064 kbit/s signals for transmission purposes is accomplished at a digital distribution frame.4.2 The signal shall have a bit rate of 32 064 kbit/s ± 10 ppm.4.3 One coaxial pair shall be used for each direction of transmission.4.4 The test load impedance shall be 75 ohms ± 5 per cent resistive and the test method shall be direct.00T1818800-92FIGURE 11/G.703Pulse mask for the symmetric pair interface at 6312 kbit/sP u l s e a m p l i t u d eP e a k p u l s e a m p l i t u d e– 1.0– 0.50.5 1.0 1.5 2.0 2.50.20.40.60.81.0Time slots relative to peak location (T)V 2V4423TT1818810-92FIGURE 12/G.703Pulse mask for the coaxial pair interface at 6312 kbit/sP u l s e a m p l i t u d eT Time-slot widthTime4.5 A scrambled AMI code shall be used.4.6 The shape for an isolated pulse measured at the point where the signal arrives at the distribution frame shall fall within the mask in the Figure 13/G.703.4.7 The voltage within a time slot containing a zero (space) shall be no greater than either the value produced in that time slot by other pulses (marks) within the mask of Figure 13/G.703 or ± 0.1 of the peak pulse (mark) amplitude, whichever is greater in magnitude.T1818820-92Time slots relative to peak location (T)FIGURE 13/G.703Pulse mask for the coaxial pair interface at 32 064 kbit/sP u l s e a m p l i t u d eP e a k p u l s e a m p l i t u d e– 1.000.20.40.60.81.0– 0.50.51.01.52.04.8 For an all 1s pattern transmitted, the power measured in a 3 kHz bandwidth at the point where the signal arrives at the distribution frame shall be as follows:16 032 kHz: +5 dBm to +12 dBm32 064 kHz: at least 20 dB below the power at 16 032 kHz.4.9 The connectors and coaxial cable pairs in the distribution frame shall be 75 ohms ± 5 per cent.5Interface at 44 736 kbit/s5.1 Interconnection of 44 736 kbit/s signals for transmission purposes is accomplished at a digital distribution frame.5.2 The signal shall have a bit rate of 44 736 kbit/s ± 20 ppm.The signal shall have a frame structure consistent with Recommendation G.752. Specifically, it shall contain the frame alignment bits F0, F11, F12 and the multi-frame alignment bits M1 to M7, as defined in Table 2/G.752.5.3 One coaxial pair shall be used for each direction of transmission.5.4 Test load impedance shall be 75 ohms ± 5 per cent resistive, and the test method shall be direct.5.5 The B3ZS code shall be used. This code is defined in Annex A.5.6 The transmitted pulses have a nominal 50% duty cycle.The shape for an isolated pulse measured at the point where the signal arrives at the distribution frame shall fall within the mask in Figure 14/G.703.5.7 The voltage within a time slot containing a zero (space) shall be no greater than either the value produced in that time slot by other pulses (marks) within the mask of Figure 14/G.703, or ±0.05 of the peak pulse (mark) amplitude, whichever is greater in magnitude.5.8 For an all 1s pattern transmitted, the power measured in a 3 kHz bandwidth at the point where the signal arrives at the distribution frame shall be as follows:22 368 kHz: -1.8 to +5.7 dBm44 736 kHz: at least 20 dB below the power at 22 368 kHz.5.9 The digital distribution frame for 44 736 kbit/s signals shall have the characteristics specified in §§5.9.1 and 5.9.2 below.5.9.1 The loss between the points where the signal arrives and leaves at the distribution frame shall be as follows:0.60 ± 0.55 dB at 22 368 kHz(comprised of any combination of flat and shaped losses).5.9.2 The connectors and coaxial pair cables in the distribution frame shall be 75 ohms ± 5 per cent.6 Interface at 2048 kbit/s6.1 General characteristicsBit rate: 2048 kbit/s ± 50 ppmCode: High density bipoler of order 3 (HDB3) (a description of this code can be found in Annex A).Overvoltage protection requirement: see Annex B.6.2 Specifications at the output ports See Table 6/G.703.6.3Specifications at the input ports6.3.1 The digital signal presented at the input port shall be as defined above but modified by the characteristic of the interconnecting pair. The attenuation of this pair shall be assumed to follow a f law and the loss at a frequency of 1024 kHz shall be in the range 0 to 6 dB. This attenuation should take into account any losses incurred by the presence of a digital distribution frame between the equipments. 6.3.2For the jitter to be tolerated at the input port, refer to § 3 of Recommendation G.823.T1818830-92Time slots relative to peak location (T)FIGURE 14/G.703Pulse mask for the coaxial pair interface at 44 736 kbit/sP u l s e a m p l i t u d eP e a k p u l s e a m p l i t u d e– 1.0– 0.500.5 1.0 1.5 2.00.20.40.60.81.0TABLE 6/G.7036.3.3 The return loss at the input port should have the following provisional minimum values:6.3.4 To ensure adequate immunity against signal reflections that can arise at the interface due to impedance irregularities at digital distribution frames and at digital output ports, input ports are required to meet the following requirement:A nominal aggregate signal, encoded into HDB3 and having a pulse shape as defined in the pulse mask, shall have added to it an interfering signal with the same pulse shape as the wanted signal. The interfering signal should have a bit rate within the limits specified in this Recommendation, but should not be synchronous with the wanted signal. The interfering signal shall be combined with the wanted signal in a combining network, with an overall zero loss in the signal path and with the nominal impedance 75 ohms (in the case of coaxial-pair interface) or 120 ohms (inthe case of symmetrical-pair interface), to give a signal-to-interference ratio of 18 dB. The binary content of the interfering signal should comply with Recommendation O.151 (215 – 1 bit period). No errors shall result when the combined signal, attenuated by up to the maximum specified interconnecting cable loss, is applied to the input port. Note – A receiver implementation providing an adaptive rather than a fixed threshold is considered to be more robust against reflections and should therefore be preferred.0%50%V = 100%T1818840-92Note – V corresponds to the nominal peak value.FIGURE 15/G.703Mask of the pulse at the 2048 kbit/s interface6.4 Earthing of outer conductor or screenThe outer conductor of the coaxial pair or the screen of the symmetrical pair shall be connected to the earth at the output port and provision shall be made for connecting the outer conductor of the coaxial pair or the screen of the symmetrical pair to earth if required, at the input port.7 Interface at 8448 kbit/s 7.1 General characteristics Bit rate: 8448 kbit/s 30 ppmCode: HDB3 (a description of this code can be found in Annex A). Overvoltage protection requirement: see Annex B.7.2 Specification at the output portsSee Table 7/G.703.TABLE 7/G.7037.3 Specifications at the input ports7.3.1 The digital signal presented at the input port shall be as defined above but modified by the characteristics of the interconnecting pairs. The attenuation of this pair shall be assumed to follow a f law and the loss at a frequency of 4224 kHz shall be in the range 0 to 6 dB. This attenuation should take into account any losses incurred by the presence ofa digital distribution frame between the equipments.7.3.2 For the jitter to be tolerated at the input port, refer to § 3 of Recommendation G.823.7.3.3 The return loss at the input port should have the following provisional minimum values:。

IEEE 1547 Interconnection Standards

Thermally Activated Technologies
Microturbines
6Байду номын сангаас
DER Grid Interconnection
Potential Consumer Benefits
• Clean energy • Lower cost electricity • Reduced price volatility • Greater reliability and power quality • Energy and load management • Combined Heat and Power
Potential Supplier Benefits
• Reduced electric line loss • Reduced T&D congestion • Grid investment deferment and improved grid asset utilization • Improved grid reliability • Ancillary services, e.g., voltage support and stability, VARs, contingency reserves, and black start capability
11
IEC TC8 System Aspects for Electrical Energy Supply
(International Electro-technical Commission Technical Committee 8) TC8 Scope – To prepare the necessary standards framework and co-ordinate the development, in co-operation with other TC/SCs, of the international standards needed to facilitate the functioning of electricity supply systems in open markets. (former scope – standardize voltages, current ratings, and frequencies). TC8 Focus Areas – electrical system adequacy (availability of supply), connection practices, operations, network responsibility, Measurement and monitoring, data exchange, communication, security, terminology. Interface with other TC’ s ( 1,9,13,17,22,28,57,64,65,73,77,82,88,95,99,105), and SC17C, SC77, ACENELEC, CIGRE, CIRED EURELECTRIC, IEEE, IEEJ, NERC, ORGAIM, NAESB, etc.

Operational reliability objective or constraint

or t>li+di +di
for si It<si
for ei 2 t I li
3.seasonallimitations 4. desirable schedule (ii)
vt vt vt vt
vt
(iii) (iv) (VI (vi) (vii)
(1)
If 152 f(P)
E
626
In a vertically integrated utility, (1) is solved as a single set of equations and the last equation in (1) shows the expected energy not supplied (EENS) which is the reliability constraint. In restructured electric power systems, the system equations (2) will be handled by the IS0 since GENCOs have virtually no control over power system flows. In this case, the ISO’s objective is to minimize flow violations stated as EENS. So, EENS, which was a constraint in a vertically integrated utility model, has turned out to be the ISO’s objective in restructure power systems. Figure 2 depicts the decomposition for the solution of the maintenance problem in which the SPl subproblem depicts the system constrains handled by the ISO.

不同网络结构及可靠性要求环境下FTU的最优配置

不同网络结构及可靠性要求环境下FTU的最优配置郑玲玲;王铮;杨丽徙【期刊名称】《电力系统保护与控制》【年(卷),期】2015(000)024【摘要】To optimize the allocation of remote terminal unit of distribution automation system, which meets the requirement of different network structures and different power supply reliability, the sensitivity between power supply reliability and the number of feeder terminal units (FTUs) is analyzed. The method of middle voltage distribution network FTUs optimal configuration are proposed based on the consequences of failure mode and effect analysis. On the basis of considering technical, economic and scalability factors, line failure outage time and average service available index (ASAI) are analyzed in three cases:line without configuration of terminal unit, line with configuration of monitoring terminal unit only and line with mixed configuration of monitoring terminal unit and controlling terminal unit. The generic expression of ASAI is deduced, as well as the number of FTUs. Example demonstrates the rationality and practicality of research methods.%为了解决配电网馈线自动化中不同网络结构、不同供电可靠性需求下配电终端的优化配置问题，对配网供电可靠性与馈线自动化终端配置的敏感性进行了分析。

配电网多端柔性互联协调控制策略

ELECTRIC DRIVE2024Vol.54No.4电气传动2024年第54卷第4期配电网多端柔性互联协调控制策略陶艳，王晨清，郑明忠，袁宇波，孔祥平，林金娇（江苏省电力试验研究院有限公司，江苏南京211100）摘要：随着社会经济的快速发展和新型电力系统建设的加快推进，柔性互联逐渐成为配电网网架升级和灵活调控能力提升的重要技术手段。

针对多端柔性互联系统的功率控制需求，提出了一种面向工程应用的功率协调控制策略，包括在部分馈线重载时合理分配功率的重载限制控制，以及在所有馈线重载时优化潮流分布的功率均衡控制。

基于所提策略开发了柔性互联协调控制装置并应用于实际工程。

基于电网真实数据的案例分析和工程实测数据验证了所提策略能够应对不同负荷/电源特性的配电网柔性互联场景，有效解决配电网中馈线重载和光伏倒送的问题，提高配电网的供电效率和安全性。

关键词：配电网；柔性互联；协调控制；重载限制；功率均衡中图分类号：TM732文献标识码：A DOI：10.19457/j.1001-2095.dqcd25269Coordinated Control Strategy for Multi-terminal Flexible Interconnection System in Distribution Network TAO Yan，WANG Chenqing，ZHENG Mingzhong，YUAN Yubo，KONG Xiangping，LIN Jinjiao（Jiangsu Electric Power Test Research Institute Co.，Ltd.，Nanjing211100，Jiangsu，China）Abstract：With the rapid development of the society and economy and the accelerated construction of new power systems，flexible interconnection has gradually become an important technical means for upgrading the structure and enhancing the flexible regulation ability of distribution network.A power coordinated control strategy for engineering applications was proposed to address the power control requirements of multi-terminal flexible interconnection systems，including heavy-load limiting control for the rational power distribution when some feeder lines were heavy-loaded，and power balance control for power flow optimization distribution when all feeders were heavy-loaded.A flexible interconnection coordinated control device was developed based on the proposed strategy and applied to practical engineering.The case analysis based on the real load data and the measured data of the project verify that the proposed strategy can deal with different flexible interconnection scenarios with different load/power characteristics，effectively solve the problems of unbalanced feeder load and reverse PV power flow in the distribution network，and improve the power supply efficiency and security.Key words：distribution network；flexible interconnection；coordinated control；heavy-load limiting；power balance在以新能源为主体的新型电力系统建设背景下，配电网用电需求增长与网络结构不合理的矛盾和分布式能源广泛接入与电网消纳能力有限的矛盾时空交织，造成现有配电网负荷分布严重不均衡，影响电网安全稳定运行[1-2]。

SOPA： Source Routing Based PacketLevel MultiPath Routing in Data Center Networks

SOPA：Source Routing Based PacketLevel MultiPath Routingin Data Center NetworksMany “rich?connected”topologies with multiple parallel paths between servers have been proposed for data center networks recently to provide high bisection bandwidth，but it remains challenging to fully utilize the high network capacity by appropriate multi?path routing algorithms. As flow?level path splitting may lead to traffic imbalance between paths due to flow size difference，packet?level path splitting attracts more attention lately，which spreads packets from flows into multiple available paths and significantly improves link utilizations. However，it may cause packet reordering，confusing the TCP congestion control algorithm and lowering the throughput of flows. In this paper，we design a novel packet?level multi?path routing scheme called SOPA，which leverages OpenFlow to perform packet?level path splitting in a round?robin fashion，and hence significantly mitigates the packet reordering problem and improves the network throughput. Moreover，SOPA leverages the topological feature of data center networks to encode a very small number of switches along the path into the packet header，resulting in very lightoverhead. Compared with random packet spraying （RPS），Hedera and equal?cost multi?path routing （ECMP），our simulations demonstrate that SOPA achieves 29.87%，50.41% and 77.74% higher network throughput respectively under permutation workload，and reduces average data transfer completion time by 53.65%，343.31% and 348.25% respectively under production workload.data center networks；multi?path routing；path splitting Keywords1 Introductionata center networks connect hundred of thousands of servers to support cloud computing，including both front?end online services （e.g.，web search and gaming）and back?end distributed computations （e.g.，distributed file system [1] and distributed data processing engine [2]，[3]）. Recognizing that the traditional tree?based topology cannot well embrace the bandwidth?hungry cloud services，in recent years many “rich?connected”data center network topologies have been proposed，such as Fat?Tree [4]，VL2 [5]，BCube [6] and FiConn [7]. These new topologies provide multiple paths between any pair of servers，and greatly increase the network bisection bandwidth. For instance，in a Fat?Tree network，there are x equal paths between two servers from different pods，where x is the number of core switches in the network；while in a [BCuben，k] network，[k+1]non?disjoint paths exist between any two servers，not to mention the paths with overlapping links. Although the advanced data center networks enjoy high network capacity，it remains challenging how to fully utilize the capacity and provide high network throughput to upper?layer applications. Multi?path routing is necessary to exploit the abundant paths between servers. The existing multi?path routing schemes can be divided into two categories，namely，flow?level path splitting and packet?level path splitting. In flow?level path splitting solutions，traffic between two servers is split into different paths at the flow granularity.All the packets belonging to a 5?tuple flow traverse the same path，so as to avoid out?of?order delivery. For examples，equal?cost multi?path routing （ECMP）uses 5?tuple hashing to choose the path for a flow from the multiple candidates，with the possibility of hash collision and unequal utilization of the paths；in order to avoid the hash collision between large flows，Hedera [8] explores a centralized way to schedule the flows by spreading large flows into different paths. However，the flow sizes and packet sizes of different flows are usually diversified，which can also lead to traffic imbalance among different paths.Packet?level path splitting，on the other hand，splits traffic in the packet granularity，i.e.，packets from a flow can be put to different paths. Since packets of the same flow are usually of similar sizes，packet?level path splitting achieves desirable traffic balance among multiple candidate paths. However，a major concern of packet?level path splitting is that it may cause packet reordering for TCP flows. Although recent studies showed that the path equivalence in modern data center networks can help mitigate the packet reordering problem，random next?hop selection in random packet spraying （RPS）[9] still results in considerable packet reordering and unsatisfactory flow throughputs，which is worsen when link fails and network symmetry is broken [9]. DRB [10] employs IP?in?IP encapsulation/decapsulation [11] to select the core level switch and uses re?sequencing buffer at the receiver to absorb reordered packets，which not only introduces much traffic overhead，but also causes considerable re?sequencing delay [10].In this paper we design SOPA，a new packet?level path splitting scheme to carry on multi?path routing in data center networks. SOPA advances the state of art by two technicalinnovations.First，rather than introducing an additional buffer at the receiver，SOPA increases the fast retransmit （FR）threshold （i.e.，the number of duplicate ACKs received at the sender that acknowledge the same sequence number）used in TCP to trigger FR，so as to mitigate the impact of packet reordering on reducing flow’s throughput. In the current TCP congestion control algorithm，packet reordering is regarded as an indicator of packet loss，hence three duplicate ACKs will cause packet retransmit at the sender without waiting for the timeouts. Although it works well in single?path routing，in multi?path routing paradigm it misleads the congestion control algorithm，since in most cases packet reordering does not come from packet loss. By increasing the FR threshold，say，to 10，SOPA significantly reduces the number of unnecessary packet retransmits，which accordingly improves the effective throughput for a flow. Fig. 11 shows the Cumulative Distribution Function （CDF）of all the flows’throughput. We can see that SOPA significantly outperforms the other three multi?path routing schemes. The average throughput of SOPA is 925.13 Mbit/s，and all the flows’throughputs are above 910 Mbit/s. Compared with SOPA，the average throughput of theflows drops by 47.47% in RPS. The fundamental reason is as explained above：RPS cannot evenly split the traffic across candidate paths，and unequal queue lengths will be built. So the receivers will receive more reordered packets，and unnecessary FRs will be triggered at the senders. As flow?based path splitting solutions，Hedera and ECMP expose even lower performance than RPS. Compared with SOPA，the average throughput drops by 75.21% and 76.48%，respectively. The basic reason is that the flow?based multi?path routing cannot fully utilize the rich link resource in the Fat?Tree network. ECMP achieves the lowest throughput because the hashing results of some flows may collide and be scheduled to the same path，which can be avoided by centralized negotiation in Hedera.4.4 Production WorkloadWe next study the performance under a more realistic workloads from a production data center [5]：95% flows are less than 1 MB，and only less than 2% flows exceeds 10 MB. Different from the permutation workload，in this simulation the data is transmitted by multiple flows instead of a single one. The flows are issued sequentially，and each flow randomly picks a destination server. All the servers start data transmission at thesame time，and we measure the average throughput of the data transmission under this workload.In our simulation，the average throughput for SOPA，RPS，Hedera，and ECMP are 465.5 Mbit/s，302.96 Mbit/s，105.005 Mbit/s，and 103.849 Mbit/s，respectively. ECMP gets the lowest throughput，since it neither evenly spreads the flows into multiple paths nor considers traffic sizes in splitting. Hedera performs a little better than ECMP，but the gap is marginal （less than 2 Mbit/s）. It is because Hedera targets at scheduling large flows but in this workload 95% flows are small ones （with data size less than 1 MB）. Both RPS and SOPA can achieve much higher throughput，due to the fine?grained link utilization by packet?level path splitting. Compared with RPS，SOPA can even improve the throughput by 53.65%，since it explicitly spreads the traffic into the multiple paths in a more balanced way. The result is consistent with that in previous simulations. 4.5 Link FailuresWe then evaluate the performance of SOPA when failure occurs. Since failure brings more negative effect forpacket?level traffic splitting （introducing more aggravated packet reordering），we only compare SOPA with RPS in this group of simulations. We use production workload to conductsimulation in the same topology as that in the previous simulation. We let the leftmost aggregation switch in the first Pod break down. Fig. 12 shows the result. In order to showcase the effect of failure，the performance without failure is also plotted.The x?axis of Fig. 12 denotes both multi?path routing schemes under different settings，wherein “NF”in parenthesis means no failure，and “F”in parenthesis denotes failures. The y?axis shows the throughput of flows. Similarly，for each candlestick in the figure，the top and bottom of the straight line represent the maximum and minimum values of the flow’s throughput，respectively. The top and bottom of the rectangle denote the 5th and 99th percentile of average throughput，respectively. The short black line is the average throughput of all flows.The performance of SOPA is almost not affected by the link failure at all，and only the minimum throughput decreases from 244 Mbit/s to 188.17 Mbit/s. This mild performance degradation is attributed to the high FR threshold of SOPA，which can absorb the more reordered packets introduced by the failure. However，failure brings more negative effects to RPS，and both the maximum and minimum throughput of RPS aredropped. When there is no failure，the maximum and minimum throughput are 865.41 Mbit/s and 214.54 Mbit/s，respectively. But in the failure case，their values drop to 672.25 Mbit/s and 26.17 Mbit/s，respectively. This performance degradation is primarily caused by timeouts of the retransmission timers. Trace data shows that when failure occurs，RPS experiences 67 times of timeout and 12000 packets have been dropped （as a contract，there is no packet loss when no failure）. The packet losses are caused by traffic congestion，since RPS cannot achieve balanced traffic splitting and the failure aggravates this situation. However，benefiting from balanced traffic splitting，SOPA does not cause packet loss，and there is not a single timeout in the simulation，with or without failures.5 ConclusionMany “rich?connected”topologies have been proposed for data centers in recently years，such as Fat?Tree，to provide full bisection bandwidth. To achieve high aggregate bandwidth，the flows need to dynamically choose a path or simultaneously transmit data on multiple paths. Existing flow?level multipath routing solutions do not consider the data size，and may lead to traffic imbalance. While the packet?level multipath routing scheme may create large queue length differential betweencandidate paths，aggravating packet reordering at receivers and thus triggering FR at the senders. In this paper we design SOPA to efficiently utilize the high network capacity. SOPA adopts source routing to explicitly split data to candidate routing paths in a round robin fashion，which can significantly mitigate packet reordering and thus improve the network throughput. By leveraging the topological feature of data center networks，SOPA encodes a very small number of switches into the packet header，introducing a very light overhead. SOPA also immediately throttles the transmission rate of the affected flow as soon as the failures are detected to promptly mitigate the negative affect of failures. NS?3 based simulations show SOPA can efficiently increase the network throughput，and outperform other schemes under different settings，irrespective of the network size. Reference[1] S. Ghemawat，H. Gobioff，and S.?T. Leung，“The google file system，”in Proc. 19th ACM Symposium on Operating Systems Principles，New York，USA，2003，pp. 29-43.[2] J. Dean and S. Ghemawat，“MapReduce：simplified data processing on large clusters，”in Proc. 6th Symposium on Operating Systems Design and Implementation，Berkeley，USA，2004，pp. 137-149.[3] M. Isard，M. Budiu，Y. Yu， A. Birrell，and D. Fetterly，“Dryad：distributed data?parallel programs from sequential building blocks，”in Proc. 2nd ACMSIGOPS/EuroSys European Conference on Computer Systems，New York，USA，2007，pp. 59-72. doi：10.1145/1272998.1273005.[4] M. Al?Fares，A. Loukissas，and A. Vahdat，“A scalable，commodity data center network architecture，”in Proc. ACM SIGCOMM 2008 Conference on Data Communication，Seattle，USA，2008，pp. 63-74. doi：10.1145/1402958. 1402967.[5] A. Greenberg，J. R. Hamilton，N. Jain，et al.，“VL2：a scalable and flexible data center network，”in Proc. ACM SIGCOMM 2009 Conference on Data Communication，Barcelona，Spain，2009，pp. 51-62. doi：10.1145/1592568. 1592576.[6] C. Guo，G. Lu，D. Li，et al.，“BCube：a high performance，server?centric network architecture for modular data centers，”in Proc. ACM SIGCOMM，Barcelona，Spain，2009，pp. 63-74.[7] D. Li， C. Guo，H. Wu，et al.，“Scalable andcost?effective interconnection of data?center servers using dual server ports，”IEEE/ACM Transactions on Networking，vol. 19，no. 1，pp. 102-114，Feb. 2011. doi：10.1109/TNET.2010.2053718.[8] M. Al?Fares，S. Radhakrishnan，B. Raghavan，N. Huang，and A. Vahdat，“Hedera：Dynamic flow scheduling for data center networks，”in Proc. 7th USENIX Symposium on Networked Systems Design and Implementation，San Jose，USA，2010，pp. 1-15.[9] A. Dixit，P. Prakash，Y. Hu，and R. Kompella，“On the impact of packet spraying in data center networks，”in Proc. IEEE INFOCOM，Turin，Italy，2013，pp. 2130-2138. doi：10.1109/INFCOM.2013.6567015.[10] J. Cao，R. Xia，P. Yang，et al.，“Per?packet load?balanced，low?latency routing for clos?based data center networks，”in Proc. Ninth ACM Conference on Emerging Networking Experiments and Technologies，Santa Barbara，USA，2013，pp. 49-60. doi：10.1145/2535372.2535375.[11] IETF. （2013，Mar. 2）. IP encapsulation within IP [Online]. Available：https：///doc/rfc2003[12] C. Guo，G. Lu，H. J. Wang，et al.，“Secondnet：a data center network virtualization architecture with bandwidthguarantees，”in Proc. 6th International Conference on Emerging Networking Experiments and Technologies，Philadelphia，USA，2010. doi：10.1145/1921168.1921188.[13] ONF. （2017，Apr. 1）. Open networking foundation [Online]. Available：https：//[14] A. Curtis，W. Kim，and P. Yalagandula，“Mahout：Low?overhead datacenter traffic management usingend?host?based elephant detection，”in Proc. IEEE INFOCOM，Shanghai，China，2011，pp. 1629-1637. doi：10.1109/INFCOM. 2011.5934956.[15] C. Raiciu，S. Barre，C. Pluntke，et al.，“Improving datacenter performance and robustness with multipath TCP，”in Proc. ACM SIGCOMM，Toronto，Canada，2011，pp. 266-277. doi：10.1145/2018436.2018467.[16] C. Raiciu，C. Paasch，S. Barr，et al.，“How hard can it be？Designing and implementing a deployable multipath TCP，”in USENIX Symposium of Networked Systems Design and Implementation，San Jose，USA，2012，pp. 29-29.[17] D. Wischik，C. Raiciu， A. Greenhalgh，and M. Handley，“Design，implementation and evaluation of congestion control for multipath TCP，”in Proc. 8th USENIX Conference on Networked Systems Design andImplementation，Boston，USA，2011，pp. 99-112.[18] M. Alizadeh，A. Greenberg，D. A. Maltz，et al.，“Data center TCP （DCTCP），”in Proc. ACM SIGCOMM，New York，USA，2010，pp. 63-74. doi：10.1145/1851182.1851192.[19] R. Niranjan Mysore， A. Pamboris，N. Farrington，et al.，“PortLand：a scalable fault?tolerant layer 2 data center network fabric，”in Proc. ACM SIGCOMM，Barcelona，Spain，2009，pp. 39-50. doi：10.1145/1594977.1592575.[20] NS?3 [Online]. Available：http：//Manuscript received：2017?03?22BiographiesLI Dan （tolidan@）received the M.E. degree and Ph.D. from Tsinghua University，China in 2005 and 2007 respectively，both in computer science. Before that，he spent four undergraduate years in Beijing Normal University，China and got a B.S. degree in 2003，also in computer science. He joined Microsoft Research Asia in Jan. 2008，where he worked as an associate researcher in Wireless and Networking Group until Feb. 2010. He joined the faculty of Tsinghua University in Mar. 2010，where he is now an associate professor at Computer Science Department. His researchinterests include Internet architecture and protocol design，data center network，and software defined networking.LIN Du （lindu1992@）received the B.S. degree from Tsinghua University，China in 2015. Now，he is a master candidate at the Department of Computer Science and Technology，Tsinghua University. His research interests include Internet architecture，data center network，and high?performance network system.JIANG Changlin（jiangchanglin@）received the B.S. and M.S. degrees from the Institute of Communication Engineering，PLA University of Science and Technology，China in 2001 and 2004 respectively. Now，he is a Ph.D. candidate at the Department of Computer Science and Technology，Tsinghua University，China. His research interests include Internet architecture，data center network，and network routing.WANG Lingqiang （wang.lingqiang@）received the B.S. degree from Department of Industrial Automation，Zhengzhou University，China in 1999. He is a system architect of ZTE Corporation. He focuses on technical planning and pre?research work in IP direction. His researchinterests include smart pipes，next generation broadband technology，and programmable networks.。

ASON中RSVP—TE可靠性和生存性机制研究

江丽君。石磊。雪鹏。李贾鹏，李健。畹仪顾
（京邮电大学光通信与光波技术教育部重点实验室，北北京１０７）０８６摘要：于流量工程扩展的资源预留协议（Ｓ－Ｅ作为自动交换光网络（ＯＮ）最重要的信令协议之一被广泛应用。基ＲＶＰＴ）ＡＳ中
恢复机制。
关键词：自动交换光网络；于流量工程扩展的资源预留协议；靠性；基可生存性中图分类号：ＴＮ９５１文献标志码：Ａ文章编号：０５８８（０７０—０１３１０ —７８２０）３００－０
自动交换光网络（ＯＮ）ＡＳ与传统的光传送网相比，突破性地引入了智能化的控制平面，而使光网从络能够在信令的控制下完成网络连接的自动拆建及保护恢复。信令作为ＡＳＯＮ控制平面的核心技术，它的可靠性和生存性机制会直接影响网络的可靠性
和服务质量。基于流量工程扩展的资源预留协议
据报协议（Ｐ包பைடு நூலகம் 行传输。Ｉ和ＵＤＰ包都是ＵＤ）Ｐ包面向无连接的，不保证消息的可靠传输。为了保证ＲＳ — ＶＰＴＥ消息的传送可靠性，ＲＳ — 在ＶＰＴＥ消息中
维普资讯
２０年０７
第３期
光通信研究
ＳＴＵＤＹ０ＮＯＰＴＩＣＡＬＣＯＭＭＵＮＩＣＡＴＩＯＮＳ

The Decision Reliability of MAP, Log-MAP,

The Decision Reliability of MAP, Log-MAP, Max-Log-MAP and SOV A Algorithmsfor Turbo CodesAbstract —In this paper, we study the reliability of decisions ofe Codes, Channel Reliability,e N comm llular, satellite and we also consider two improved versions, named Log-MAP two different or identicalRecursi s, connectedin pFig. 1. The turbo encoder with rate 1/3.The first encoder operat ed b e u , i ond encoderp Lucian Andrei Peri şoar ă, and Rodica Stoianth MAP, Log-MAP, Max-Log-MAP and SOVA decoding algorithms for turbo codes, in terms of the a priori information, a posteriori information, extrinsic information and channel reliability. We also analyze how important an accurate estimate of channel reliability factor is to the good performances of the iterative turbo decoder. The simulations are made for parallel concatenation of two recursive systematic convolutional codes with a block interleaver at the transmitter, AWGN channel and iterative decoding with mentioned algorithms at the receiver.Keywords —Convolutional Turbo D cision Reliability, Extrinsic Information, Iterative Decoding.I. I NTRODUCTIONunication systems, like ce computer fields, the information is represented as a sequence of binary digits. The binary message is modulated to an analog signal and transmitted over a communication channel affected by noise that corrupt the transmitted signal.The channel coding is used to protect the information fromnoise and to reduce the number of error bits.One of the most used channel codes are convolutional codes, with the decoding strategy based on the Viterbialgorithm. The advantages of convolutional codes are used inTurbo Codes (TC), which can achieve performances within a2 dB of channel capacity [1]. These codes are parallelconcatenation of two Recursive Systematic Convolutional (RSC) codes separated by an interleaver. The performances of the turbo codes are due to parallel concatenation ofcomponent codes, the interleaver schemes and the iterative decoding using the Soft Input Soft Output (SISO) algorithms [2], [3].In this paper we study the decision reliability problem for turbo coding schemes in the case of two different decodingstrategies: Maximum A Posteriori (MAP) algorithm and Soft Output Viterbi Algorithm (SOVA). For the MAP algorithmand Max-Log-MAP algorithms. The first one is a simplified algorithm which offers the same optimal performance with a reasonable complexity. The second one and the SOVA are less complex again, but give a slightly degraded performance. The paper is organized as follows. In Section II, the turbo encoder is presented. In Section III, the turbo decoder is ex Manuscript received December 10, 2008. This work was supported in part by the Romanian National University Research Council (CNCSIS) under theGrant type TD (young doctoral students), no. 24.L. A. Peri şoar ă is with the Applied Electronics and InformationEngineering Department, Politehnica University of Bucharest, Romania (e-mail: lucian@orfeu.pub.ro, lperisoara@, www.orfeu.pub.ro).R. Stoian is with the Applied Electronics and Information Engineering Department, Politehnica University of Bucharest, Romania (e-mail: rodica@orfeu.pub.ro, rodicastoian2004@, www.orfeu.pub.ro).plained in detail, presenting firstly the iterative decoding principle (turbo principle), specifying the concepts of a priori information, a posteriori information, extrinsic information, channel reliability and source reliability. Then, we review the MAP, Log-MAP, Max-Log-MAP and SOVA decoding algorithms for which we discuss the decision reliability. In Section IV is analyzed the influence of channel reliability factor on decoding performances for the mentioned decoding algorithms. Section V presents some simulation results, which we obtained.II. T HE T URBO C ODING S CHEME The turbo encoder can use ve Systematic Convolutional (RSC) code arallel, see Fig. 1.es on the input bits represent n their original order, while the sec y the fram o erates on the input bits which are permuted by the interleaver, frame u ’, [4]. The output of the turbo encoder is represented by the frame: I2)()()1211,12,121,22,21,2,,,,,,,,,...,,,k k k u c c u c c u c c ==v u c c /R k n = to b , (1)is less likely where frame c1 is the output of the first RSC and frame c2 is the output of the second RSC. If the input frame u is of length k and the output frame x is of length n , then the encoder rate is .For block encoding data is segmented into non-overlapping blocks of length k with each block encoded (and decoded)independently. This scheme imposes the use of a blockinterleaver with the constraint that the RSC’s must begin in the same state for each new block. This requires either trellis termination or trellis truncation. Trellis termination need appending extra symbols (usually named tail bits) to the inputframe to ensure that the shift registers of the constituent RSC encoders starts and ends at the same zero state. If the encoder has code rate 1/3, then it maps k data bits into 3k coded bits plus 3m tail bits. Trellis truncation simply involves resettingthe state of the RSC’s for each new block.The interleaver used for parallel concatenation is a device that permutes coordinates either on a block basis (a generalized “block” interleaver) or on a sliding window basis(a generalized “convolutional” interleaver). The interleaver ensures that the set of code sequences generated by the turbo code has nice weight properties, which reduces the probabilitythat the decoder will mistake one codeword for another.The output codeword is then modulated, for example with Binary Phase Shift Keying (BPSK), resulting the sequence , which is transmitted over an Additive White Gaussian Noise (AWGN) channel.(12,,=v u c c 12,)p x x )(,s p =x x e a low weight codeword due to the interleaver in front of it. The interleaver shuffles the inputsequence It is known that turbo codes are the best practical codes due to their performance at low SNR. One reason for their better performance is that turbo codes produce high weight code words [4]. For example, if the input sequence u is originally low weight, the systematic u and parity c 1 outputs mayproduce a low weight codeword. However, the parity output c 2 is less likely to be a low weight codeword due to the u , in such a way that when introduced to the second encoder, it is more likely probable to produce a high weight codeword. This is ideal for the code because high weight code words result in better decoder performance. III. T HE T URBO D ECODING S CHEME Let be the received sequence of length n , 12(,,)s p p =y y y y where the vector y s is formed only by the received informationsymbols s y 222222(,,...,)p p p p n y y y =y p 1 and y p 2and . These three streams are applied to the input of the turbo decoder presented in Fig. 2. 11112(,,...,)p p p p n y y y 1=y y At time j , decoder 1 using partial received information 1,s p j j y y (), makes its decision and outputs the a posterioriinformation s j L x +()()()e s s s s . Then, the extrinsic information is computed j j j c jL x L x L x L y +−=−−. Decoder 2 makes itsdecision based on the extrinsic information ()e sj L x 2 from decoder 1 and the received information ',s p j jy y . The term(')s j L x + is the a posteriori information derived from decoder 2 and used by decoder 1 as a priori information about thereceived sequence, noted with (')sj L x −(). Now, the second iteration can begin, and the first decoder decodes the same channel symbols, but now with additional information about the value of the input symbols provided by the second decoder in the first iteration. After some iterations, the algorithm converges and the extrinsic information values remains the same. Now the decision about the message bits u j is made based on the a posteriori values s j L x +.e s y p 2y p 1y sFig. 2. The turbo decoder.Each constituent decoder operates based on the Logarithm Likelihood Ratio (LLR).A. The Decision Reliability of MAP DecoderBahl, Cocke, Jelinek and Raviv proposed the Maximum APosteriori (MAP) decoding algorithm for convolutional codesin 1974 [1]. The iterative decoder developed by Berrou et al.[5] in 1993 has a greatly increased attention. In their paper,they considered the iterative decoding of two RSC codesconcatenated in parallel through a non-uniform interleaver and the MAP algorithm was modified to minimize the sequence error probability instead of bit error probability.Because of its increased complexity, the MAP algorithm was simplified in [6] and the optimal MAP algorithm calledthe Log-MAP algorithm was developed. The LLR of a transmitted bit is defined as [2]:(1)()log ()(1)s Wenoted def j s sj j s j P x L x L x P x −⎛⎞=+==⎜⎟⎜⎟=−⎝⎠where the sign of the LLR ()s j L x indicate whether the bit s j xis more likely to be +1 or -1 and the magnitude of the LLRgives an indication of the correct value of s j x . The term()sj L x − is defined as the a priori information about s j x .In channel coding theory we are interested in theprobability that , based or conditioned on some received sequence 1s j x =±s j y . Hence, we use the conditional LLR: ()()()1||log (1|s s We noted def j j s s s j j j s s j j P x y L x y L x P x y +⎛⎞=+⎜⎟=⎜⎟=−⎝⎠=) The conditional probabilities (1|s sj j P x y =± are the a posteriori probabilities of the decoded bit s j x and ()s j L x + is thea posteriori information about sj x , which is the information that the decoder gives us, including the received frame, the a priori information for the systematic symbols y s j and the apriori information for symbol x s j . It is the output of the MAPalgorithm. In addition, we will use the conditional LLR ()|s s j j L y x based on the probability that the receiver’s output would be s j y when the transmitted bit s j x was either +1 or -1:()()()|1|log |1s s defj j s s jjs s j j P y x L y x P y x ⎛⎞=+⎜=⎜=−⎝⎠⎟⎟. (3)For AWGN channel using BPSK modulation, we can write the conditional probability density functions, [7]:()()20|12s s b j j j EP y x y a N ⎡⎤=±=−⎢⎣⎦m ⎥, (4)where is the transmitted energy per bit, a is the fadingamplitude and is the noise variance.b E 0/2N We can rewrite the (3) as follows: ()()()2200|4,s s s s b j j j j Noteds s b j c j E L y x y a y a N E a y L y N ⎡⎤=−−−+⎢⎥⎣⎦== (5) the fading amplitude and is the noise power. For nonfading AWGN channels a = 1 and 0N /204c b L E N =. Theratio is defined as the Signal to Noise Ration (SNR) of thechannel.0/b E N The extrinsic information can be computed as [1], [2], [9]: ()()()()()()1|()log 1|1|log log 1|()().s s j j e sj s s jj s s j j s sj j s s s j j c j P x y L x P x y P x P y x P x P y x L x L x L y +−⎛⎞=+⎜⎟=⎜⎟=−⎝⎠⎛⎞⎛=+=+⎜⎟⎜−−⎜⎟⎜=−=−⎝⎠⎝=−−11s j s j ⎞⎟⎟⎠ (6)The a posteriori information defined in (2), can be written asthe following [1], [10]:11(')()(',)()log (')()(',)e j j j s j e j j j s s s s L x s s s s −++−−α⋅β⋅γ=α⋅β⋅γ∑∑, (7)where +∑is the summation over all possible transition branch pairs (s ’,s ) in the trellis, at time j , given the transmittedsymbol x s j = +1. Analog, −∑is for transmitted symbol x s j =-1.The forward and backward terms, represented in Fig. 3 as transitions between two consecutive states from the trellis, can be computed recursively as following [7], [10], [11]:1'()(')(',)j j j s s s s s −α=αγ∑, (8)1(')()(',)j j j ss s s s −β=βγ∑. (9)For systematic codes, which is our case, the branch transition probabilities (',)js s γ are given by the relation:11(',)exp ()(',)22s s s s e j j j c jj j s s L x x L x y s −⎡γ=+⋅γ⎢⎣⎦s ⎤⎥, (10) where:112211(',)exp 22e p p j c j j c p p j j s s L x y L x ⎡⎤γ=+⎢⎥⎣⎦y .(11)At each iteration and for each frame y, ()s j L x + is computedat the output of the second decoder and the decision is done,symbol by symbol j = 1…k , based on the sign of ()sj L x +, original information bit u j being estimated as [2], [3]: {ˆ()sj usign L x +=}j . (12) In the iterative decoding procedure, the extrinsicinformation ()e s j L x is permuted by the interleaver andbecomes the a priori information ()sj L x − for the next decoder. influence on ()s j L x + is insignificant.B. The Decision Reliability of Max-Log-MAP DecoderThe MAP algorithm as described in previous section is much more complex than the Viterbi algorithm and with hard decision outputs performs almost identically to it. Therefore for almost 20 years it was largely ignored. However, its application in turbo codes renewed interest in this algorithm. Its complexity can be dramatically reduced without affecting its performance by using the sub-optimal Max-Log-MAP algorithm, proposed in [12]. This technique simplifies the MAP algorithm by transferring the recursions into the log domain and invoking the approximation: ln max()i x i ii e x ⎛⎞≈⎜⎟⎝⎠∑. (13)where max()i i x means the maximum value of x i . If we note:()()ln ()j j A s =αs , (14)()()ln ()j j B s s =β, (15)and:()(',)ln (',)j j G s s s s =γ, (16)then the equations (8), (9) and (10) can be written as: ()(()1'1'1'()ln ()ln (')(',)ln exp (')(',)max (')(',),j j j j s j j s j j s )A s s s s A s G s s A s G s s −−−⎛⎞=α=αγ⎜⎟⎝⎠⎛=+⎜⎝⎠≈+∑∑s ⎞⎟⎞⎟(17) ()()()11(')ln (')ln ()(',)ln exp ()(',)max ()(',),j j j j s j j s j j s B s s s s s B s G s s B s G s s −−⎛⎞=β=βγ⎜⎟⎝⎠⎛=+⎜⎝⎠≈+∑∑ (18) 11(',)()22s s s s jj j c j G s s C x L x L x y −=++j , (19) term ()s s j j x L x −.Finally, the a posteriori LLR ()s j L x + which the Max-Log-MAP algorithm calculates is:Fig. 3. Trellis states transitions.for ()j s αfor 1(')j s −β((1(',)11(',)1()max(')(',)()max (')(',)().j j s j j j j s s for u j j j s s for u L x As G s s B s ))A s G s s B s +−=+−=−≈++−++ (20)In [12] and [13] the authors shows that the complexity of Max-Log-MAP algorithm is bigger than two times that of a classical Viterbi algorithm Unfortunately, the storage requirements are much greater for Max-Log-MAP algorithm, due to the need to store both the forward and backward recursively calculated metrics and before the ()j A s ()j B s ()s j L x + values can be calculated.C. The Decision Reliability of Log-MAP DecoderThe Max-Log-MAP algorithm gives a slight degradation in performance compared to the MAP algorithm due to the approximation of (13). When used for the iterative decodingof turbo codes, Robertson found this degradation to result in a drop in performance of about 0.35 dB, [12]. However, the approximation of (13) can be made exact by using the Jacobian logarithm:()(()121212121212ln()max(,)ln 1exp ||max(,)||(,),x x e e x x x x )x x f x x g x x +=++−−=+−= (21)where ()f δ can be thought of as a correction term. However,the maximization in (17) and (18) is completed by the correction term ()f δ in (21). This means that the exact ratherthan approximate values of and are calculated. For binary trellises, the maximization will be done only for two terms. Therefore we can correct the approximations in (17) and (18) by adding the term ()j A s ()j B s ()f δ, where δ is the magnitude of the difference between the metrics of the twomerging paths. This is the basis of the Log-MAP algorithmproposed by Robertson, Villebrun and Hoeher in [12]. Thus we must generalize the previous equation for more than two 1x terms, by nesting the 12(,)g x x operations as follows: (((13211ln ,,,(,)i n x n n i e g x g x g x g x x −=⎛⎞=⎜⎟⎝⎠∑K ))), (22)The correction term ()f δδ need not to be computed for every value of , but instead can be stored in a look-up table. In [12], Robertson found that such a look-up table need containonly eight values for , ranging between 0 and 5. This meansthat the Log-MAP algorithm is only slightly more complexthan the Max-Log-MAP algorithm, but it gives exactly the same performance as the MAP algorithm. Therefore, it is a very attractive algorithm to use in the component decoders of an iterative turbo decoder. δD. The Decision Reliability of SOVA DecoderThe MAP algorithm has a high computational complexityfor providing the Soft Input Soft Output (SISO) decoding. However, we obtain easily the optimal a posteriori probabilities for each decoded symbol. The Viterbi algorithm provides the Maximum Likelihood (ML) decoding for convolutional codes, with optimalsequence estimation. The conventional Viterbi decoder has two main drawbacks for a serial decoding scheme: the inner Viterbi decoder produces bursts of error bits and hard decision output, which degrades the performance of the outer Viterbi decoder [3]. Hagenauer and Hoeher modified the classical Viterbi algorithms and they provided a substantially less complex and suboptimal alternative in their Soft OutputViterbi Algorithm (SOVA). The performance improvement is obtained if the Viterbi decoders are able to produce reliability values or soft outputs by using a modified metric [14]. These reliability values are passed on to the subsequent Viterbi decoders as a priori information .In soft decision decoding, the receiver doesn’t assign a zero or a one to each received symbol from the AWGN channel, but uses multi-bit quantized values for the received sequence y , because the channel alphabet is greater than the sourcealphabet [3]. In this case, the metric derived from Maximum Likelihood principle, is used instead of Hamming distance. For an AWGN channel, the soft decision decoding produces again of 2÷3 dB over hard decision decoding, and an eight-level quantization offers enough performance in comparison with an infinite bit quantization [7].The original Viterbi algorithm searches for an informationsequence u that maximizes the a posteriori probability, s being the states sequence generated by the message u . Using the Bayes theorem and taking into account that thereceived sequence y is fixed for the metric computation and it can be discarded, the maximization of is: (|)P s y (|)P s y {}{max (|)max (|)()P P =u us }P y y s s . (23)For a systematic code, this relation can be expanded to:(1211max (,,)|,()k s p p j j j j j j j P y y y s s P s −=)⎧⎫⎪⎪⎨⎬⎪⎪⎩⎭∏u. (24) Taking into account that:()()()(1211122(,,)|,|||s p p j j j j j s s p p p p j j j j j j P y y y s s P y x P y x P y x −==⋅⋅), (25)where 1(,)j j s s − denotes the transitions between the states attime j -1 and the states at time j , the SOVA metric is obtained from (24) as [15]:()()***1***|1(1)log log ,(0)|1j j j j j j j j j jP y x P u M M x u P u P y x −⎛⎞=+⎛⎞=⎜⎟=++⎜⎟⎜⎟⎜⎟==−⎝⎠⎝⎠∑ (26)where *1,2,(,,)j j j j x u c c = is the RSC output code word at timej , at channel input and *1(,,)s p p j j j j 2y y y y = is the channeloutput. The summation is made for each pair of information symbols (,s j j u y ) and for each pair of parity symbols (11,,p j j c y )and (2,2,p j j y 1*c ).According [14] and [7], the relation (26) can be reduced as: **c j j ()j j j j M M L −=+∑x y u L u +(), (27)where the source reliability j L u , defined in (26), is the log-likelihood ratio of the binary symbol u j . The sign of ()j L u ) is the hard decision of u j and the magnitude of (j L u is the decision reliability .According [10], the SOVA metric includes values from the past metric M j -1, the channel reliability L c and the source reliability ()j L u (, as an a priori value. If the channel is very good, the second term in (27) is greater than the third term andthe decoding relies on the received channel values. If thechannel is very bad, the decoding relies on the a priori information )j L u . If M 1j , M 2j are two metrics of the survivor path and concurrent path in the trellis, at time j , then the metric difference is defined as [7]:01212j j j M M −)(s m Δ=. (28)The probability of path m , at time j , is related as:()/2mjM (path )exp m j P m P ==. (29) where j s is a states vector and mj M is the metric. The probability of choosing the survivor path is: 001)(path (correc ath 1)(path 2)1jjP e P P P e ΔΔ==++t)(p . (30)The reliability of this path decision is calculated as:(correct)orrect)log 1-(c j P P =Δ. (31) The reliability values along the survivor paths, for aparticular node and time j , are denoted as d j Δ, where d is the distance from the current node at time j . If the survivor path bit for is the same with the associated bit on the competing path, then there would be no error if the competing path is chosen. The reliability value remains unchanged.d j =To improve the reliability values an updating process must be used, so the “soft” values of a decision symbol are:(')'di j d j di L u u −−=j=Δ∑, (32)which can be approximated as:{}0...(')'min i j d j d i d L u u −−=j =⋅Δ. (33)The SOVA algorithm described in this section is the least complex of all the SISO decoders discussed in this section. In [12], Robertson shows that the SOVA algorithm is about halfas complex as the Max-Log-MAP algorithm. However, theSOVA algorithm is also the least accurate of the algorithmsdescribed in this section and, when used in an iterative turbo decoder, performs about 0.6 dB worse than a decoder using the MAP algorithm. If we represent the outputs of the SOVA algorithm they will be significantly more noisy than thosefrom the MAP algorithm, so an increased number of decodingiterations must be used for SOVA to obtain the sameperformances as for MAP algorithm.The same results are reported also for the iterative decoding (turbo decoding) of the turbo product codes, which are basedon two concatenated Hamming block codes not on convolutional codes [19]. IV. T HE INFLUENCE OF L C ON DECODING PERFORMANCE In this section we analyze the importance of an accurate estimate of the channel reliability factor L c is to the good performance of an iterative turbo decoder which uses the MAP, SOVA, Max-Log-MAP and Log-MAP algorithms. In the MAP algorithm the channel inputs and the a priori information are used to calculate the transition probabilities from one state to another, that are then used to calculate theforward and backward recursion terms [2], [8]. Finally, the aposteriori information ()s j L x + is computed and the decision about the original message is made based on it. In the iterative decoding with MAP algorithm, the channelreliability is calculated from the received channel values. At first iteration, the decoder 1 has no a priori information available (the ()s j L x − is zero) and the output from thealgorithm is calculated based on channel values. If an incorrect value of L c is used the decoder will make more decision errors and the extrinsic information from the output of the first decoder will have incorrect values, for the softchannel inputs [16].In the SOVA algorithm the channel values are used torecursively calculate the metric *c j L y j M for the current state s along a path from the metric 1j M − for the previous state along that path added to an a priori information term and to a cross-correlation term between the transmitted and the receivedchannel values, *j x and *j y , using (27). The channel reliability factor is used to scale this cross-correlation. When we usec Lan incorrect value of , e.g. , we are scaling the channel values applied to the inputs of component decoders by a factor of one instead of the correct value of . This has the effect of scaling all the metrics by the same factor, see (8), and the metric differences are also scaled by the same factor, see (9). This scaling of the metrics do not affect the path chosen by the algorithm as a survivor path or as a Maximum Likelihood (ML) path, so the hard decisions given by the algorithm are not affected by using an incorrect value of L c [16]-[18].c L ()j B s 1c L =c L c In the iterative decoding with SOVA algorithm, in the first iteration we assume that no a-priori information about the transmitted bits is available to the decoder (the a-priori information is zero), the first component decoder takes only the channel values. If channel reliability factor is incorrect, the channel values are scaled, the extrinsic information will be also scaled by the same factor and the a-priori information for the second decoder will also be scaled. Because of the linearity of the SOVA, the effect of using an incorrect value of the channel reliability factor is that the output LLR from the decoder is scaled by a constant factor. The relative importance of the two inputs to the decoder, the a priori information and the channel information, will not change, since the LLRs for both these sources of information will be scaled by the same factor. In the final iteration, the soft outputs from the final component decoder will have the same sign as those that would have been calculated using the correct value of . So, the hard outputs from the turbo decoder using the SOVA algorithm are not affected by the channel reliability factor [16].L c L The Max-Log-MAP algorithm has the same linearity that is found in the SOVA algorithm. Instead of one metric, now two metrics and are calculated, for forward andbackward recursions, see (17), (18) and (19), were are used only simple additions of the cross-correlation of the transmitted and received symbols. But, if an incorrect value of the channel reliability value is used, all the metrics are simply scaled by a factor as in the SOVA algorithm. The soft outputs given by the differences in metrics between different paths will also be scaled by the same factor, with the sign unchanged and the final hard decisions given by the turbo decoder will not be affected.()j A s The Log-MAP algorithm is identical to the Max-Log-MAP algorithm, except for a correction term ()()ln exp()f δ=−δ1+, used in the calculation of the forward and backward metrics and ()j A s ()j B s , and the soft output LLRs. The function()f δ is not a linear function, it decreases asymptoticallytowards zero as δ increases. Hence the linearity that is present in the Max-Log-MAP and SOVA algorithms is not present in the Log-MAP algorithm. This effect of non-linearity determines more hard decision errors of thecomponent decoders if the channel reliability factor is incorrect, and the extrinsic information derived from the first component decoder have incorrect amplitudes, which become the a-priori information for the second decoder in the first iteration. Both decoders in subsequent iterations will have incorrect amplitudes relative to the soft channel inputs.c L In the iterative decoding with Log-MAP algorithm, the extrinsic information exchange from one component decoder to another, determines a rapid decrease in the BER as the number of iterations increases. When the incorrect value of is used, no such rapid fall in the BER occurs due to the incorrect scaling of the a priori information relative to the channel inputs. In fact, the performance of the decoder is largely unaffected by the number of iterations used.c L For wireless communications, some of them modeled as Multiple Input Multiple Output (MIMO) systems [23], the channel is considered to be Rayleigh or Rician fading channel. If the Channel State Information (CSI) is not known at the receiver, a natural approach is to estimate the channel impulse response and to use the estimated values to compute the channel reliability factor required by the MAP algorithm to calculate the correct decoding metric.c L In [20], the degradation in the performance of a turbo decoder using the MAP algorithm is studied when the channel SNR is not correctly estimated. The authors propose a method for blind estimation of the channel SNR, using the ratio of the average squared received channel value to the square of the average of the magnitudes of the received channel values. In addition, they showed that using these estimates for SNR gives almost identical performances for the turbo decoder to that given using the true SNR.In [8], the authors proposes a simple estimation scheme for from the statistical computation on the block observation of matched filter outputs. The channel estimator includes the error variance of the channel estimates. In [24], is used the Minimum Mean Squared Error (MMSE) estimation criterion and is studied an iterative joint channel MMSE estimation and MAP decoding.c L None of above works requires a training sequence with pilot symbols to estimate the channel reliability factor. Other studies used pilot symbols to estimate the channel parameters, like [22] and [25].In [22] it is shown that it is not necessary to estimate the channel SNR for a turbo decoder with Max-Log-MAP or SOVA algorithms. If the MAP or the Log-MAP algorithm is used then the value of does not have to be very close to the true value for a good BER performance to be obtained. c LV. S IMULATION RESULTSThis section presents some simulation results for the turbo codes ensembles, with MAP, Max-Log-MAP, Log-MAP and SOVA decoding algorithms. The turbo encoder is the same for the four decoding algorithms and is described by two identical RSC codes with constraint length 3 and the generator polynomials and . No tail bitsand no puncturing are performed. The two constituent encoders are parallel concatenated by a classical block interleaver, with dimensions variable according to the frame21f G =+D D 21b G D =++。

GaN HEMT经时击穿可靠性的研究进展

基金项目:国家重点研发计划(2017YFB 0403000)收稿日期:2020-07-23㊀㊀㊀通信作者:蔡小龙作者简介:孙梓轩(1995-),男,安徽安庆人,工程师,硕士,从事氮化镓射频器件可靠性研究工作;蔡小龙(1989-),男,山东东营人,工程师,博士,主要从事碳化硅光电器件及氮化镓射频器件等方面的研究工作㊂第39卷㊀第12期2020年12月电子元件与材料ELECTRONIC ㊀COMPONENTS ㊀AND ㊀MATERIALSVol .39No .12Dec .2020GaN HEMT 经时击穿可靠性的研究进展孙梓轩1,2,蔡小龙1,2,3,杜成林1,2,段向阳2,陆㊀海3(1.移动网络和移动多媒体技术国家重点实验室,广东深圳㊀518057;2.中兴通讯股份有限公司,江苏南京㊀210012;3.南京大学电子科学与工程学院,江苏南京㊀210093)㊀㊀摘要:氮化镓(GaN )高电子迁移率晶体管(HEMT )凭借着高电子迁移率㊁低导通电阻和高击穿场强等优点,在高频器件和大功率开关器件等领域得到了广泛运用㊂但经时击穿会导致在正常工作电压范围内的器件发生失效,因此GaN 器件的经时击穿成为了评估器件可靠性的关键因素㊂介绍了GaN HEMT 经时击穿的现象及偏压依赖性,总结了经时击穿的物理机制,讨论和展望了场板㊁钝化层以及栅极边缘终端结构对提升器件的经时击穿可靠性的作用㊂关键词:氮化镓;高电子迁移率晶体管;综述;经时击穿;失效;可靠性DOI :10.14106/j .cnki .1001-2028.2020.0523中图分类号:TN 304.2㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀文献标识码:AResearch progress on reliability of time -dependentbreakdown in GaN HEMTSUN Zixuan 1,2,CAI Xiaolong 1,2,3,DU Chenglin 1,2,DUAN Xiangyang 2,LU Hai 3(1.State Key Laboratory of Mobile Network and Mobile Multimedia Technology,Shenzhen 518057,Guangdong Province,China;2.ZTE Corporation,Nanjing 210012,China;3.School of Electronic Science and Engineering,Nanjing University,Nanjing 210093,China)㊀㊀Abstract :Due to their high electron mobility ,low on -resistance and high breakdown field ,GaN high electron mobility transistors (HEMTs )are widely used in high frequency and high power switching devices.Time -dependent breakdown becomes a keyfactor in evaluating the reliability of GaN HEMT ,because it could lead to failure of the device under normal operating voltage.In this paper ,the phenomena and bias dependence of time -dependent breakdown in GaN HEMTs are introduced ,and its physical mechanism are also summarized.The effect of the field plate ,passivation layer ,and gated edge termination structure to the the reliability improvement of time -dependent breakdown in GaN HEMTs are discussed.Key words :GaN ;high electron mobility transistor (HEMT );review ;time -dependent breakdown ;failure ;reliability㊀㊀由于具备高电子迁移率㊁高热导率㊁宽禁带等特点,氮化镓(GaN )高电子迁移率晶体管(HEMT )成为了第三代半导体器件的研究热点[1-2]㊂在不同衬底的GaN HEMT 中硅(Si )基GaN HEMT 具有低成本㊁大尺寸以及与Si 基互补型金属氧化物半导体(CMOS )工艺相互兼容等优势,被广泛应用于转换开关㊁充电设备等电子电力领域㊂相比传统的Si 基CMOS 器件,GaN HEMT 具备更低的导通电阻和更大的开关频率,这些特性降低了开关器件的功率转换损耗[3-4]㊂由于功率转换损耗占全球用电量的10%,因此规模性采用高效功率转换器可以节约全球大量的电力资源㊂与Si 基器件相比,采用碳化硅(SiC )衬底的GaN 器件具备更高的热导率,降低了沟道温度带来的不利影响,因此SiC 基GaN HEMT 被广泛应用于高功率射频器件中[5]㊂此外,GaN 材料的击穿场强高达约3.3MV /cm ,使GaN HEMT 高压器件能够在超过1000V 的电压下有效运行[6-7],展现了在汽车充电桩和大型工业电源应用中的广阔前景㊂但是在实际应用中,GaN HEMT 存在着经时击穿㊁自热效应㊁电流崩塌以及热载流子效应等可靠性问题,严重影响了GaN HEMT 的工作稳定性和使用寿命,因此评估和提升GaN HEMT 的可靠性成为2㊀Vol.39No.12 Dec.2020了继续扩大器件商用规模的重要一环㊂通常而言, GaN HEMT的抗击穿能力是一项关键的可靠性指标,这决定了器件的使用场景以及使用寿命,当器件的抗击穿能力与使用场景不匹配时,将会发生器件级甚至系统级的失效㊂另外,在对GaN HEMT进行击穿测试时发现,器件会发生经时击穿(TDDB, Time-Dependent Breakdown),即器件长时间处于正常工作电压范围内发生击穿失效的现象[8-10]㊂这种可靠性问题会导致GaN HEMT工作在合适的使用场景中也可能会发生失效,因此GaN HEMT的经时击穿需要得到更多的关注㊂在传统的Si基CMOS器件中,经时击穿的相关机理已经得到了深入的研究[11-13]㊂通过参考CMOS 器件经时击穿的研究思路,可以确定在研究GaN HEMT经时击穿时,首先需要了解器件经时击穿的偏压依赖性,然后根据实验结果分析出器件经时击穿失效的物理机理,最后基于前期的研究结果,优化器件的结构来提升器件的经时击穿可靠性㊂在本文中,首先介绍了GaN HEMT的经时击穿现象以及这种现象对电压的强依赖性,然后总结了GaN HEMT经时击穿的物理机理,最后讨论了场板㊁钝化层以及栅极边缘终端(GET)结构对器件经时击穿可靠性的提升㊂这将会有助于从器件工艺层面有效改善经时击穿,从而提升器件寿命及可靠性㊂1㊀GaN HEMT的经时击穿特性介绍1.1㊀经时击穿的电流特性通常采用在栅极施加电压应力,源极和漏极接地,并检测栅电流随应力时间变化的方式来表征GaN HEMT的栅极经时击穿特性㊂以Wu和Meneghini等的研究为例[14-15],在固定栅应力下测得的栅电流的变化:栅电流最初较为稳定,并在陷阱俘获效应的作用下略有下降㊂在应力时间增加到320s之前,栅电流与阈值电压都随着时间增加呈指数形式的降低,如图1(a)所示;320s之后,在栅应力的作用下大量陷阱在器件中生成,从而增大了栅电流噪声幅度,如图1(b)所示;随着应力时间的进一步增加,器件发生击穿失效,此时可以观测到器件的栅电流突然急剧增加(图1(c))㊂1.2㊀经时击穿的偏压依赖性为了研究GaN HEMT经时击穿的电压依赖性, Marcon等进行了几组不同恒定电压应力下的经时击穿测试[16]㊂在实验中对三组相同型号的器件分别施加了55,60和65V三个不同的应力电压㊂实验表明,器件的击穿时间(t BD)随着应力电压的增加而减小,如图2所示㊂因此,器件的经时击穿具有明显的偏压依赖性,即更高的偏压降低了器件的击穿时间[17-19]㊂根据经时击穿的电压依赖性,可以确定器件的内部电场对经时击穿起到了主导作用,在后续的器件设计中需要对器件的内部电场峰值进行优化处理㊂图1㊀(a)GaN器件在不同栅电压下,栅电流随应力时间的变化图[14];(b)栅电流噪声幅度随应力时间变化图;(c)阈值电压随应力时间的退化图[15]Fig.1㊀(a)The relationship between the gate current and stress time in GaN HEMT under various stresses[14];(b)Thegate current noise amplitude changes with stress time; (c)The threshold voltage degradation with stress time[15]图2㊀经时击穿的电压依赖性[17]Fig.2㊀Voltage dependence of time-dependent breakdown[17] 2㊀GaN HEMT的经时击穿机理2007年,Inoue等研究了GaN HEMT经时击穿与初始栅极泄漏电流之间的关系[20],发现了初始泄漏电流较大的器件更容易发生经时击穿㊂因此,认为GaN HEMT的经时击穿与栅极泄漏电流路径有关,长时间的电压应力会增加器件的栅极泄漏电流孙梓轩等:GaN HEMT经时击穿可靠性的研究进展第39卷㊀第12期3㊀路径,导致栅极出现急剧的电流增加现象㊂2012年,Meneghini 等提出了渗流路径物理模型来解释施加反向栅极应力时,器件参数的可逆性和永久性退化,并通过2D 仿真结果证明了该模型的合理性[15]㊂该模型认为,经时击穿是在长时间的电压应力下,于AlGaN 层中产生陷阱并最终形成渗流路径的过程㊂器件经时击穿的物理机制可以由以下六个过程进行描述:(1)器件的缓冲层中存在着施主-深受主对,当向GaN HEMT 施加反向偏置时,高能电子从栅极注入到AlGaN 层,AlGaN 层中的电子积累会导致栅极泄漏电流呈指数下降;(2)在高电场的作用下,电子从AlGaN 层注入到缓冲层中;(3)当在器件上施加较高的反向应力时,电子会获得足够的能量,同时缓冲层中的深受主杂质发生电离,这一过程在场致发光(EL )的光谱上产生宽的黄色发射峰[21-22],或者促使电子从价带转移到深受主能级并产生自由空穴;(4)在器件栅极上施加了较高的负偏压后,缓冲层中的空穴会积聚在AlGaN/GaN 界面处或被AlGaN 层中的陷阱捕获,此时界面处和AlGaN 层中的陷阱都处于正电态,这些正电荷产生的静电势会导致器件的阈值电压降低,如图3(a )所示;(5)在栅极应力下,由于器件内部存在高电场,电子会在AlGaN 层中随机产生陷阱,这些陷阱可以俘获电子,并导致栅极电流噪声增加;(6)随着应力时间的增加,陷阱会发生重叠,在栅极和缓冲层之间产生渗流路径,并导致栅极永久退化㊂基于此模型,可以判断高原生陷阱密度的器件应比低陷阱密度的器件更易发生经时击穿㊂图3(b )中的结果证实了这一判断:对在相同应力条件下的相同型号但初始泄漏电流不同的器件进行经时击穿测试,结果显示t BD 与初始泄漏电流(初始泄漏电流的大小与器件的原生陷阱密度有关)具有幂律关系(Power Law)㊂图3㊀(a )陷阱机制示意图;(b )击穿时间与器件初始泄漏电流的关系[15]Fig .3㊀(a )Schematic representation of the trap mechanism ;(b )Dependence of t BD on the initial leakage current [15]2015年,Wu 等研究了采用等离子体增强原子层沉积(PE -ALD )氮化硅(SiN x )作为栅介质的GaN HEMT 的经时击穿,发现器件在长时间栅应力下,栅介质中会产生陷阱并形成渗流路径,导致器件击穿㊂在此研究中,通过对比耗尽型(D -mode )HEMT 和增强型(E -mode )HEMT 经时击穿点分布的区别,发现栅极在AlGaN 层中拐角处的介质比栅极下侧的介质薄,更容易形成渗流路径导致器件发生经时击穿[14]㊂同年,Meneghini 等结合实验数据和仿真结果,发现了在应力条件下,GaN HEMT 器件漏极侧的栅极边缘拐角处具有很强的电场尖峰,强电场会使载流子具备更高的能量,从而更容易在钝化层中产生陷阱,这些陷阱会导致栅极边缘拐角处发生击穿[23]㊂2017年,Hu 等对GaN HEMT 栅极下方区域的经时击穿进行了实验和仿真分析,发现了GaN 器件的GET 结构在栅应力下会发生两次经时击穿的现象[24]㊂为了探究双次击穿的原因,他们仿真了栅应力-500V 下器件栅极边缘端的电场分布㊂仿真结果显示,栅极下方的二维电子气(2DEG )耗尽区域存在较大的电场,且栅极边缘终端拐角处的电场峰值高达约5MV /cm ㊂据此可以判断第一次击穿过程是在栅极边缘终端拐角处的金属/绝缘体/半导体(MIS )结构中的Si 3N 4介质层内形成了渗流路径㊂第一次击穿后器件的AlGaN /Si 3N 4界面处存在较高的泄漏电流,所以第二次击穿发生在AlGaN 层中㊂对于具有GET 结构的GaN HEMT 器件,高电场的作用会导致PE -ALD Si 3N 4首先被击穿,然后在AlGaN 势垒中发生第二次击穿㊂同年,Tallarico 等研究了具有p -GaN 栅极结构的GaN HEMT 的经时击穿[25]㊂根据Arrhenius 曲线估算出了陷阱激活能E a ʈ0.44eV ,通过与GaN 和AlGaN 器件的深能级陷阱数据库相对比[26],认为0.44eV 激活能的陷阱与p -GaN 层中的氧杂质有关[27],这意味着在长时间的栅极应力条件下,渗流路径逐渐在p -GaN 层中形成,最终导致器件栅极发生经时击穿㊂2019年,He 等提出了p -GaN 栅极结构的GaN HEMT 存在两个阶段的经时击穿[28]㊂第一阶段的经时击穿是金属/p -GaN 界面附近的耗尽层中生成的陷阱所引起的击穿;第二阶段是AlGaN 势垒层中产生的陷阱导致AlGaN 被击穿㊂在器件栅极施加正向应力后,p -GaN 层内的耗尽层使金属/p -GaN 肖特基结被反向偏置,而p -i -n 异质结被正向偏置㊂孙梓轩等:GaN HEMT 经时击穿可靠性的研究进展4㊀Vol.39No.12 Dec.20202DEG中的电子将从AlGaN势垒溢出,并注入进p-GaN层中(如果栅极应力很大,栅极也会向p-GaN层注入空穴)㊂载流子在p-GaN耗尽层的高电场作用下加速并变成高能载流子,这些高能载流子将轰击金属/p-GaN界面或界面附近的p-GaN 层,在界面处或p-GaN层中产生陷阱㊂在长时间的应力作用下,陷阱密度逐渐增加并将栅极接触从肖特基型转变为类欧姆型,引发第一次栅极击穿㊂之后,栅极电压主要被施加在了AlGaN层,陷阱开始在AlGaN层中产生,并形成渗流路径造成AlGaN 层被击穿㊂同年,Lee等研究了在交流(AC)和直流(DC)栅应力下的GaN HEMT的经时击穿,发现器件在AC应力下具备更长的t BD[29]㊂在正的DC栅应力下,AlGaN和栅介质层的导带边缘靠近费米能级,因此AlGaN和栅介质层界面处会积累电子,导致栅介质层电场增加㊂在高电场作用下,栅介质会更易发生经时击穿㊂然而,在AC应力下,AlGaN和栅介质层的导带边缘离费米能级较远,不会在AlGaN 和栅介质界面积累电子㊂所以,AC应力下的GaN HEMT具备更久的t BD㊂3㊀经时击穿可靠性的提升3.1㊀场板技术在GaN HEMT器件工作的过程中,自热效应会导致在AlGaN层表面处产生陷阱[30],同时,器件制备阶段也会在AlGaN层表面引入原生陷阱,这些陷阱可以捕获电子,并在AlGaN层表面形成负电荷㊂表面的高浓度负电荷使AlGaN能带发生弯曲,减薄了AlGaN势垒厚度,热电子更容易发生隧穿,隧穿电流过大会使器件更易发生经时击穿[31]㊂此外,器件栅极边缘拐角处存在电场尖峰,高电场会导致该区域更易产生陷阱,从而影响器件的经时击穿可靠性㊂因此,优化器件的内部电场分布,可以有效提升器件经时击穿可靠性㊂图4为具有场板结构的GaN HEMT剖面示意图,可以发现场板被放置在栅极上方,并且覆盖了栅源区域㊂由于场板与GaN HEMT的源极相连接,当器件处于工作状态时,场板与源极都处于低电位,所以栅极附近的电力线会受到低电位的吸引,部分电力线会从沟道指向场板,缓解了栅极边缘的电场尖峰,降低了栅极漏端附近的电场峰值[32-34]㊂即使在AlGaN层存在缺陷电荷,场板结构也可以使器件内部电场均匀地分布在栅极和漏极之间,降低了陷阱对AlGaN层势垒的影响㊂图4㊀场板结构示意图Fig.4㊀Schematic diagram of field plate structure 2018年,Kabemura等研究了GaN HEMT的场板结构对经时击穿的影响[35]㊂实验结果显示,场板结构的应用可以有效改善器件的经时击穿㊂其中,场板长度在0.2~0.3μm时,GaN HEMT具备最佳的经时击穿可靠性㊂当场板过长,场板边缘到漏端的距离过短时,电场会在场板边缘到漏端区域形成尖峰,导致器件更容易被击穿㊂3.2㊀钝化层技术传统的GaN HEMT工艺主要采用等离子体增强化学气相沉积(PECVD)SiN x作为HEMT的钝化层[36],SiN x钝化了AlGaN层的表面态,降低了由表面态引起的栅漏边缘电场和栅泄露电流,从而优化了HEMT的经时击穿可靠性㊂2016年,Bao等研究指出传统PECVD SiN x钝化层工艺中的活性等离子体源会破坏AlGaN表面并形成表面陷阱,增加器件的泄漏电流[37-38]㊂因此, PECVD工艺会导致器件的功耗增加以及可靠性变差㊂相比而言,低压力化学气相沉积法(LPCVD)是一种高生长温度和无等离子体源的工艺方法,该方法可以避免等离子体源对AlGaN表面的破坏㊂因此采用LPCVD SiN x代替PECVD SiN x作为GaN HMET的钝化层,提升了器件击穿电压,增强了器件的经时击穿可靠性,降低了栅极泄漏电流以及SiN x/AlGaN界面陷阱密度[39-41],但LPCVD SiN x工艺比PECVD SiN x工艺需要耗费更多的时间㊂2019年,Gao等提出了采用NiO x/SiN x和Al2O3/SiN x代替SiN x作为GaN HEMT的钝化层[42]㊂通过电子束蒸发(EB)沉积Ni和Al薄膜,然后在氧环境中退火来制备NiO x和Al2O3㊂由于NiO x和Al2O3都是化学性质稳定的氧化物且具有良好的绝缘性,所以它们可以被用作HEMT的钝化层㊂为了防止金属层被氧化物氧化,在钝化层工艺中采用NiO x/SiN x(Al2O3/SiN x)的堆叠工艺㊂他们在实验孙梓轩等:GaN HEMT经时击穿可靠性的研究进展第39卷㊀第12期5㊀中对比了NiO x /SiN x (Al 2O 3/SiN x )工艺与传统的单层PECVD SiN x ,结果显示采用NiO x /SiN x 和Al 2O 3/SiN x 作为钝化层抑制了HEMT 的电流崩塌效应,降低了栅极泄漏电流,增强了器件的抗击穿能力㊂相比于SiN x 材料,采用高k 材料如:HfO 2(相对介电常数εr ʈ20)[43]㊁LaLuO 3(εr ʈ20)[44]和TiO 2(εr ʈ20)[45]作为GaN HEMT 的钝化层也得到了广泛的研究㊂研究表明采用高k 材料的钝化层降低了器件栅极下方的电场峰值,使栅极和漏极之间的电场分布变得平滑,提升了器件的击穿电压和经时击穿可靠性[46-47]㊂2018年,Kabemura 等研究了不同介电常数的高k 材料对GaN HEMT 栅下电场的影响[35]㊂结果表明,更高介电常数的高k 材料更好地优化了HEMT 栅极下方的电场,增加了器件的击穿电压㊂3.3㊀GET 结构AlGaN /GaN 肖特基势垒二极管(SBD )结构是GaN HEMT 的重要组成部分[48-49]㊂在栅极应力下,SBD 结构中的AlGaN 层被击穿是导致GaN HEMT 经时击穿的关键原因[24,28-29]㊂因此,对SBD 结构的优化可以增强GaN HEMT 的经时击穿可靠性㊂2013年,Lenci 提出了GET 结构[50],通过在GaN HEMT 的栅极边缘增加一层Si 3N 4介质层,来改善器件的栅极边缘电场特性,如图5所示㊂在AlGaN /栅金属界面引入Si 3N 4介质层,不仅钝化了AlGaN 表面的陷阱,也增加了界面势垒高度,从而降低了栅极隧穿电流㊂实验结果显示,具有GET 结构的HEMT 在-600V 栅电压下的栅泄漏电流低于1μA /mm ,比传统栅极结构HEMT 的栅极泄漏电流低约四个数量级,这表明GET 结构的HEMT 具备更好的耐击穿性能㊂图5㊀GaN HEMT 中的栅极边缘终端(GET )结构示意图[50]Fig .5㊀Schematic diagram of gated edge termination structurein GaN HEMT [50]为了提升GET 结构的经时击穿可靠性,2017年Hu 等提出了采用体膜质量更佳的金属有机物化学气相沉积(MOCVD )Si 3N 4代替PE -ALD Si 3N 4作为GET 结构中的介质层[24]㊂他们在实验中对比了分别采用25nm MOCVD Si 3N 4和25nm PE -ALD Si 3N 4作为介质层的GET 结构的经时击穿结果,发现采用MOCVD -Si 3N 4介质层可以将器件的t BD 提升十倍,并且将击穿电压从15V 提升至25V ㊂2018年,Acurio 等提出了双层GET 结构来改善SBD 的经时击穿[51]㊂与传统的GET 结构相比,双层GET 结构通过添加第二个GET 层,在AlGaN 势垒内形成了一个新的电场尖峰,这不仅减轻了第一个GET 结构拐角处的电场,而且使电场的分布更加均匀㊂实验结果显示,相比传统的GET 结构,双层GET 结构有效延长了SBD 的击穿时间㊂这种双层GET 结构也可以引入到GaN HEMT 中,改善器件栅极边缘以及AlGaN 层的电场分布,降低器件的泄漏电流,从而改善器件的经时击穿可靠性㊂4㊀结语GaN HEMT 具备高工作频率㊁高能量密度等优势,在高频㊁高功率器件等领域得到了广泛的应用,然而GaN HMET 器件的可靠性问题成为了限制GaN 器件发展的瓶颈㊂其中,经时击穿可靠性问题作为GaN 器件可靠性研究的关键一环,得到了越来越多的关注㊂本文介绍了GaN HEMT 在长时间栅应力下发生经时击穿的现象及其偏压依赖性㊂随后,总结了GaN HEMT 栅极介质层和AlGaN 层经时击穿的物理机制㊂最后,讨论了通过场板技术㊁钝化层以及GET 技术对GaN HEMT 经时击穿可靠性的提升㊂其中,场板技术降低了栅极边缘处的电场尖峰,改善了器件的经时击穿㊂钝化层技术通过降低器件的初始泄漏电流和栅漏之间的尖峰电场,以提升器件的抗击穿能力㊂GET 结构则是侧重于栅极介质层工艺,不仅降低了栅边缘处的尖峰电场,也抑制了渗流路径的产生㊂这三种工艺技术在器件制备中的灵活运用,可以更好地提升器件的经时击穿可靠性,延长器件的使用寿命,拓宽器件的应用场景㊂参考文献:[1]Ma B D.Driving GaN power transistors [C ]//31stInternational Symposium on Power Semiconductor Devices and ICs (ISPSD ).NY ,USA :IEEE ,2019:87-90.[2]Li X ,Amirifar N ,Geens K ,et al.GaN -on -SOI :monolithically integrated all -GaN ICs for power孙梓轩等:GaN HEMT 经时击穿可靠性的研究进展6㊀Vol.39No.12Dec.2020 conversion[C]//2019IEEE International ElectronDevices Meeting(IEDM).NY,USA:IEEE,2019:4.4.1-4.4.4.[3]冯旭东,胡黎,张宣,等.GaN功率器件栅驱动电路技术综述[J].微电子学,2020,50(2):207-213. [4]Ji D,Li W W,Chowdhury S.A study on the impact ofchannel mobility on switching performance of vertical GaN MOSFETs[J].IEEE Transactions on Electron Devices, 2018,65(10):4271-4275.[5]Mohapatra E,Das S,Dash T P,et al.High frequencyperformance of AlGaN/GaN HEMTs fabricated on SiC substrates[C]//2019Devices for Integrated Circuit.NY,USA:IEEE,2019:326-330.[6]Ma J,Erine C,Zhu M H,et al.1200V multi-channelpower devices with2.8Ω㊃mm on-resistance[C]// 2019IEEE International Electron Devices Meeting (IEDM).NY,USA:IEEE,2019:4.1.1-4.1.4.[7]Wang T F,Ma J,Matioli E.1100V AlGaN/GaNMOSHEMTs with integrated tri-anode freewheeling diodes[J].IEEE Electron Device Letters,2018,39(7):1038-1041.[8]Kim H S,Eom S K,Seo K S,et al.Time-dependentdielectric breakdown of recessed AlGaN/GaN-on-Si MOS-HFETs with PECVD SiO2gate oxide[J].Vacuum,2018,155:428-433.[9]Ivo P,Cho E M,Kotara P,et al.New degradationmechanism observed for AlGaN/GaN HEMTs with sub 100nm scale unpassivated regions around the gate periphery[J].Microelectronics Reliability,2014,54 (6/7):1288-1292.[10]Meneghesso G,Meneghini M,Zanoni E.Breakdownmechanisms in AlGaN/GaN HEMTs:an overview[J].Japanese Journal of Applied Physics,2014,53(10):100211.[11]Kim H,Jin M,Sagong H,et al.A systematic study ofgate dielectric TDDB in FinFET technology[C]//2018IEEE International Reliability Physics Symposium(IRPS).NY,USA:IEEE,2018:4A.4.1-4A.4.4.[12]Mei S,Raghavan N,Bosman M,et al.Newunderstanding of dielectric breakdown in advancedFinFET devices-physical,electrical,statistical andmultiphysics study[C]//2016IEEE InternationalElectron Devices Meeting(IEDM).NY,USA:IEEE,2016:15.5.1-15.5.4.[13]Yang K X,Liu T Z,Zhang R,et al.A comprehensivetime-dependent dielectric breakdown lifetime simulatorfor both traditional CMOS and FinFET technology[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2018,26(11):2470-2482. [14]Wu T L,Marcon D,Jaeger B D,et al.Timedependent dielectric breakdown(TDDB)evaluation ofPE-ALD SiN gate dielectrics on AlGaN/GaN recessedgate D-mode MIS-HEMTs and E-mode MIS-FETs[C]//2015IEEE International Reliability PhysicsSymposium.NY,USA:IEEE,2015:6C.4.1-6C.4.6.[15]Meneghini M,Stocco A,Bertin M,et al.Time-dependent degradation of AlGaN/GaN high electronmobility transistors under reverse bias[J].AppliedPhysics Letters,2012,100(3):033505. [16]Marcon D,Kauerauf T,Medjdoub F,et al.A comprehensivereliability investigation of the voltage,temperature anddevice geometry-dependence of the gate degradation onstate-of-the-art GaN-on-Si HEMTs[C]//2010IEEEInternational Electron Devices Meeting(IEDM).NY,USA:IEEE,2010:20.3.1-20.3.4. [17]Meneghesso G,Meneghini M,Stocco A,et al.Degradationof AlGaN/GaN HEMT devices:role of reverse-bias andhot electron stress[J].Microelectronic Engineering,2013,109:257-261.[18]Meneghini M,Bisi D,Marcon D,et al.Trapping andreliability assessment in D-mode GaN-based MIS-HEMTs for power applications[J].IEEE Transactionson Power Electronics,2014,29(5):2199-2207. [19]Meneghini M,Barbato A,Borga M,et al.Power GaNHEMT degradation:from time-dependent breakdown tohot-electron effects[C]//2018IEEE InternationalElectron Devices Meeting(IEDM).NY,USA:IEEE,2018:30.5.1-30.5.4.[20]Inoue Y,Masuda S,Kanamura M,et al.Degradation-mode analysis for highly reliable GaN-HEMT[C]//2007IEEE/MTT-S International Microwave Symposium.NY,USA:IEEE,2007:639-642.[21]Meneghini M,Stocco A,Ronchi N,et al.Extensiveanalysis of the luminescence properties of AlGaN/GaNhigh electron mobility transistors[J].Applied PhysicsLetters,2010,97:063508.[22]Calleja E,Sanchez F J,Basak D,et al.Yellowluminescence and related deep states in undoped GaN[J].Physical Review B,1997,55(7):4689-4694.[23]Meneghini M,Rossetto I,Hurkx F,et al.Extensiveinvestigation of time-dependent breakdown of GaN-HEMTs submitted to OFF-state stress[J].IEEETransactions on Electron Devices,2015,62(8):2549-2554.[24]Hu J,Stoffels S,Zhao M,et al.Time-dependentbreakdown mechanisms and reliability improvement inedge terminated AlGaN/GaN schottky diodes underHTRB tests[J].IEEE Electron Device Letters,2017,38(3):371-374.㊀[25]Tallarico A N,Stoffels S,Magnone P,et al.Investigation ofthe p-GaN gate breakdown in forward-biased GaN-based power HEMTs[J].IEEE Electron DeviceLetters,2017,38(1):99-102.[26]Bisi D,Meneghini M,Santi D C,et al.Deep-levelcharacterization in GaN HEMTs-part I:advantages andlimitations of drain current transient measurements[J].IEEE Transactions on Electron Devices,2013,60(10):3166-3175.[27]Caesar M,Dammann M,Polyakov V,et al.Generation oftraps in AlGaN/GaN HEMTs during RF-and DC-stresstest[C]//2012IEEE International Reliability PhysicsSymposium(IRPS).NY,USA:IEEE,2012:6.1-6.5.[28]He J B,Wei J,Yang S,et al.Temperature-dependentgate degradation of p-GaN Gate HEMTs under static and孙梓轩等:GaN HEMT经时击穿可靠性的研究进展第39卷㊀第12期7㊀dynamic positive gate stress[C]//31st InternationalSymposium on Power Semiconductor Devices and ICs(ISPSD).NY,USA:IEEE,2019:295-298. [29]Lee E S,Hurtado L,Joh J,et al.Time-dependentdielectric breakdown under AC stress in GaN MIS-HEMTs[C]//2019IEEE International ReliabilityPhysics Symposium(IRPS).NY,USA:IEEE,2019:1-5.[30]Hasegawa H,Inagaki T,Ootomo S,et al.Mechanismsof current collapse and gate leakage currents in AlGaN/GaN heterostructure field effect transistors[J].Journalof Vacuum Science&Technology B,2003,21(4):1844.[31]Mizuno S,Ohno Y,Kishimoto S,et rge gateleakage current in AlGaN/GaN high electron mobilitytransistors[J].Japanese Journal of Applied Physics,2002,41(1):5125-5126.[32]Rossetto I,Meneghini M,Pandey S,et al.Field-related failure of GaN-on-Si HEMTs:dependence ondevice geometry and passivation[J].IEEE Transactionson Electron Devices,2017,64(1):73-77. [33]Chini A,Soci F,Fantini F,et al.Field plate relatedreliability improvements in GaN-on-Si HEMTs[J].Microelectronics Reliability,2012,52(9/10):2153-2158.[34]Onodera H,Horio K.Analysis of buffer-impurity andfield-plate effects on breakdown characteristics in small-sized AlGaN/GaN high electron mobility transistors[J].Semiconductor Science and Technology,2016,27(8):085016.[35]Kabemura T,Ueda S,Kawada Y,et al.Enhancementof breakdown voltage in AlGaN/GaN HEMTs:fieldplate plus high-k passivation layer and high acceptordensity in buffer layer[J].IEEE Transactions onElectron Devices,2018,65(9):3848-3854. [36]Tang Z K,Jiang Q M,Lu Y Y,et al.600V normallyOFF SiN x/AlGaN/GaN MIS-HEMT with large gateswing and low current collapse[J].IEEE ElectronDevice Letters,2013,34(11):1373-1375. [37]Bao Q L,Huang S,Wang X H,et al.Effect ofinterface and bulk traps on the C-V characterization of aLPCVD SiN x/AlGaN/GaN metal-insulator-semiconductor structure[J].Semiconductor Science andTechnology,2016,31(6):065014.[38]Cho H J,Her J C,Lee K I,et al.Low damage SiN xsurface passivation using remote ICP-CVD for AlGaN/GaN HEMTs[C]//2008International Conference onSolid State Devices and Materials.Ibaraki,Japan:TheJapan Society of Applied Physics,2008:504-505. [39]Moon S W,Lee J,Seo D,et al.High-voltage GaN-on-Si hetero-junction FETs with reduced leakage and currentcollapse effects using SiN x surface passivation layerdeposited by low pressure CVD[J].Japanese Journal ofApplied Physics,2014,53(8S3):08NH02.1-08NH02.6.[40]Hua M Y,Liu C,Yang S,et al.Characterization ofleakage and reliability of SiN x gate dielectric by low-pressure chemical vapor deposition for GaN-based MIS-HEMTs[J].IEEE Transactions on Electron Devices,2015,62(10):3215-3222.[41]Shi Y J,Huang S,Bao Q L,et al.Normally OFF GaN-on-Si MIS-HEMTs fabricated with LPCVD-SiN xpassivation and high-temperature gate recess[J].IEEETransactions on Electron Devices,2016,63(2):614-619.[42]Gao S,Zhou Q B,Liu X Y,et al.Breakdownenhancement and current collapse suppression in AlGaN/GaN HEMT by NiO x/SiN x and Al2O3/SiN x as gatedielectric layer and passivation layer[J].IEEE ElectronDevice Letters,2019,40(12):1921-1924. [43]Liu C,Chor E F,Tan L S.Enhanced deviceperformance of AlGaN/GaN HEMTs using HfO2high-kdielectric for surface passivation and gate oxide[J].Semiconductor Science and Technology,2007,22(5):522-527.[44]Yang S,Huang S,Chen H W,et al.AlGaN/GaNMISHEMTs with high-k LaLuO3gate dielectric[J].IEEE Electron Device Letters,2012,33(7):979-981.[45]Lee C S,Hsu W C,Chou B Y,et al.Investigations ofTiO2-AlGaN/GaN/Si-passivated HFETs and MOS-HFETs using ultrasonic spray pyrolysis deposition[J].IEEE Transactions on Electron Devices,2015,62(5):1460-1466.[46]Hanawa H,Kazushige H.Increase in breakdown voltage ofAlGaN/GaN HEMTs with a high-k dielectric layer[J].Physical Status Solidi A,2014,211(4):784-787. [47]Hanawa H,Onodera H,Nakajima A,et al.Numericalanalysis of breakdown voltage enhancement in AlGaN/GaN HEMTs with a high-k passivation layer[J].IEEETransactions on Electron Devices,2014,61(3):769-775.[48]Lei J C,Wei J,Tang G F,et al.An interdigitatedGaN MIS-HEMT/SBD normally-off power switchingdevice with low ON-resistance and low reverseconduction loss[C]//2017IEEE International ElectronDevices Meeting(IEDM).NY,USA:IEEE,2017:25.2.1-25.2.4.[49]Li S,Liu S Y,Zhang C,et al.Integrated GaN MIS-HEMT with multi-channel heterojunction SBD structures[C]//201931st International Symposium on PowerSemiconductor Devices and ICs(ISPSD).NY,USA:IEEE,2019:447-450.[50]Lenci S,Jaeger B D,Carbonell L,et al.Au-freeAlGaN/GaN power diode on8-in Si substrate with gatededge termination[J].IEEE Electron Device Letters,2013,34(8):1035-1037.[51]Acurio E,Crupi F,Ronchi N,et al.Reliability improvementsin AlGaN/GaN schottky barrier diodes with a gated edgetermination[J].IEEE Transactions on ElectronDevices,2018,65(5):1765-1770.孙梓轩等:GaN HEMT经时击穿可靠性的研究进展。

DYNEX_AN5945_IGBT Module Reliability

Qualification procedure: The principle behind this method is to qualify a product based on a test plan according to defined conditions such as international standards and or some reference test plan. The obvious advantages of this method are the same evaluation process for all companies in a same industry sector and no additional cost for study (test plan definition). The major disadvantage is that the test plan becomes obsolete when considering new technology. The test plan can be very general and not exactly adapted to the application (constraint choice). Table 2 shows an example of a standard qualification tests (based mainly on the IEC and CENELEC Standard) adopted by Dynex during the product release stage and the maintenance of the qualified product. Theoretical calculations: The traditional method of calculating failure rate uses an accelerated life testing of the device. The method involves testing devices from a random sample obtained from the parent population followed by a stress test, under accelerated conditions, to promote failures. The acceleration factor (AF) thus obtained is then extrapolated to end-use conditions by means of a predetermined statistical model to give an estimate of the failure rate in the field applications. For Page 3 of 7

1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。

Multistage Interconnection Networks Reliability Nasser S. Fard and Indra Gunawan Department of Mechanical, Industrial, and Manufacturing Engineering Northeastern University Boston, MA 02115, USA

Abstract Reliability and performance of interconnection network systems significantly depends on the interconnection of its components, among other factors. The interconnection among switches, number of stages, and the types of switches normally determine the system configuration. System performance could be analyzed based on its redundant paths, information transition time, and its reliability. As the number of interconnection paths and number of input/output of connecting switches in a network increases, the performance measurement becomes more complicated. This paper presents several multistage interconnection network systems, with complexity of each for performance analysis. We also present a method for reliability improvement of interconnection communication systems.

Keywords Networks, Multistage, Interconnection, Reliability, and Switches.

1. Introduction Interconnection networks are a natural result of advances in computer technology that provide the need in the improved system performance. As computer systems evolved, the hardware costs being a significant limiting factor. However, interconnection technology is creating an entirely new atmosphere; it is now economically feasible to construct a multiple-processor computer system by interconnecting a large number of processors and memory modules. Interconnection networks are currently being used for many different applications such as telephone switches, processor/memory interconnects for supercomputer, networks for industrial application, and wide area computer networks [3]. Therefore, concept, design, and implementation of interconnection networks are crucial factors at this point in time.

To solve a problem of providing fast, efficient communications at a reasonable cost, many different networks between the extremes of the single bus and the completely connected scheme have been proposed in the literature [6]. There is no single network that is generally considered best. This paper is an in depth study of a collection of network designs that can be used to support large-scale parallelism. These networks can provide the communications needed in a parallel processing system consisting of a large number of processors that are working together to perform a single overall task. Many of these networks can be used in dynamically reconfigurable machines that can perform independent multiple tasks, where each task is processed using parallelism. This hardware model consists of a set of processors, a set of memory, and an interconnection network between processors and memory [5]. The interconnection network facilitates communication not only among the processors and the memory modules but also between the processors and memory modules. In this case, shared-memory multiprocessors model simplifies the task of exchanging data among processors.

2. Fault Tolerant Multistage Interconnection Networks (MINs) connect input devices to output devices through a number of switch stages, where each switch is a crossbar network. The number of stages and the connection patterns between stages determine the routing capability of the networks. A fault-tolerant MIN is one that provides service, in at least some cases, even when it contains a faulty component or components. A fault can be either permanent or transient, unless stated otherwise; it is assumed that faults are permanent. Fault tolerance is defined only with respect to a chosen fault-tolerance model, which has two parts. The fault

model characterizes all faults assumed to occur, stating the failure modes (if any) for each network component. The fault-tolerance criterion is the condition that must be met for the network to be said to have tolerated a given fault or faults.

A network is single-fault tolerant if it can function as specified by its fault-tolerance criterion despite any single fault conforming to its fault model. More generally, if any set of i faults can be tolerated, then a network is i-fault tolerant. A network that can tolerate some instances of i faults is robust although not i-fault tolerant.

3. Multistage Interconnection Network Configurations A multistage interconnection network configuration depends on the number of stages, types of switches, and interconnection among the network switches/stages. In this paper, several types of MINs will be introduced: 1. Multistage Cube Network: The generalized cube topology (Figure 1) was introduced as a standard for comparing different types of multistage cube networks. It has n = log2 N stages, numbered from 0 to n – 1,