A Low-Noise Readout Circuit for Gyroscopes

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[GA Rincon-Mora]A low-voltage, low quiescent current, low drop-out regulator[1998][317]

A Low-V oltage,Low Quiescent Current,Low Drop-Out RegulatorGabriel A.Rincon-Mora,Member,IEEE,and Phillip E.Allen,Fellow,IEEE Abstract—The demand for low-voltage,low drop-out(LDO)regulators is increasing because of the growing demand forportable electronics,i.e.,cellular phones,pagers,laptops,etc.LDO’s are used coherently with dc-dc converters as well asstandalone parts.In power supply systems,they are typicallycascaded onto switching regulators to suppress noise and providea low noise output.The need for low voltage is innate to portablelow power devices and corroborated by lower breakdown voltagesresulting from reductions in feature size.Low quiescent current ina battery-operated system is an intrinsic performance parameterbecause it partially determines battery life.This paper discussessome techniques that enable the practical realizations of low qui-escent current LDO’s at low voltages and in existing technologies.The proposed circuit exploits the frequency response dependenceon load-current to minimize quiescent currentﬂow.Moreover,the output current capabilities of MOS power transistors areenhanced and drop-out voltages are decreased for a given devicesize.Other applications,like dc-dc converters,can also reapthe beneﬁts of these enhanced MOS devices.An LDO prototypeincorporating the aforementioned techniques was fabricated.Thecircuit was operable down to input voltages of1V with a zero-load quiescent currentﬂow of23 A.Moreover,the regulatorprovided18and50mA of output current at input voltages of1and1.2V,respectively.Index Terms—Low drop-out,low-voltage regulators,powersupply circuits,regulators.I.I NTRODUCTIONT HE low drop-out nature of the regulator makes it appro-priate for use in many applications,namely,automotive,portable,industrial,and medical applications[1].The automo-tive industry requires low drop-out(LDO)regulators to powerup digital circuits,especially during cold-crank conditionswhere the battery voltage can be below6V.The increasingdemand,however,is especially apparent in mobile battery-operated products,such as cellular phones,pagers,camerarecorders,and laptops[2].In a cellular phone,for instance,switching regulators are used to boost up the voltage butLDO’s are cascaded in series to suppress the inherent noiseassociated with switchers.LDO’s beneﬁt from working withlow input voltages because power consumption is minimizedaccordingly,.Low voltage and low quiescentcurrent are intrinsic circuit characteristics for increased batteryefﬁciency and longevity[3].Low voltage operation is also aconsequence of process technology.This is because isolationManuscript received October4,1996;revised March30,1997.G.A.Rincon-Mora is with the Standard Linear Design Branch,TexasInstruments Incorporated,Dallas,TX75243USA.P.E.Allen is with the School of Electrical and Computer Engineering,Georgia Institute of Technology,Atlanta,GA30332-0250USA.Publisher Item Identiﬁer S0018-9200(98)00368-0.Fig.1.Typical low drop-out regulator topology.barriers decrease as the component densities per unit areaincrease,thereby exhibiting lower breakdown voltages[4],[5].Therefore,low power andﬁner lithography require regulatorsto operate at low voltages,produce precise output voltages,andhave characteristically lower quiescent currentﬂow[5].By theyear2004,the power supply voltage is expected to be as lowas0.9V in0.14-current of the regulatorEfﬁciencyincreases,which resultsfrom low-voltage operation and/or increased output currentspeciﬁcations.Consequently,the quiescent current of the am-pliﬁer’s gain stage is limited by a bandwidth minimumwhileFig.2.Current efﬁcient LDO buffer stage.the quiescent current of the ampliﬁer’s buffer stage is limitedby the slew-rate current required todriveis negligible,therebyyielding high overall current efﬁciency and not aggravatingbattery life.Consequently,the current through the emitterfollower issimply when load-current is low.Duringhigh load-current conditions,the current through the emitterfollower is increasedbyto higher frequencies andby increasing the current available for slew-rate conditions.Thus,the biasing conditions for the case of zero load-currentcan be designed to utilize a minimum amount of current,whichyields maximum current efﬁciency and prolonged battery life.1)Frequency Response:When the load-current is low,themagnitude of the system’s dominant pole,determinedby the output capacitor and the output impedance of the passdevice,is also low[10].This is because the output impedanceof the pass device is inversely proportional to the currentﬂowing throughitis the channel length modulation parameter,and is the load-current.Consequently,the unity gainfrequency(UGF)is at low frequencies when the load-current islow,which relaxes the requirement of the parasitic pole at theoutput of the errorampliﬁer to be approximately greater than or equal to the minimum unity gainfrequency with an associated design equationofis the transconductance of the emitter followerandis inverselyproportional to the square root of the loadcurrent(4)whereandincreases faster than the gain decreases with load-current,the unity gain frequency increases as the load-current increases [(2)and (4)].These consequential effects of load-current onfrequency response are graphically illustrated in Fig.3.Zero,associated equivalent series resistance (ESR)ofshown in Fig.1[9].Therefore,theparasiticpole is also required to increase with load-current,which is achieved by the load dependent boost current.This is apparent from the followingequation:corresponds to a constant mirror ratio,i.e.,1/1500forFig.2.The circuit can be designed suchthat(6)orrequiredfor the system to react and may be expressedasis theoutput slew-rate current of the error ampliﬁer [9].However,the slew-rate current is not constant for the circuitproposed,------(9)where BW is the closed-loop bandwidth of the system(approximately ).The composite buffer stage is essentially a localized positive feedback circuit.The system is stable because the positive feedback gain is less than one.Consequently,the circuit attempts to latch up until the output transistor is fully turned on;at which point,the error ampliﬁer forces the circuit back into the linear region.As a result,the performance tradeoffs between the slew-rate and the quiescent current requirements of typical LDO’s are circumvented.For instance,if the parasiticcapacitance is 200pF,the source-to-gate voltage change required for the output PMOStransistor is 0.5V,the bandwidth of the system is 1MHz,and the response time is limited to be less than5required is approximately25A can provide the sameperformance.The dominant factor of thenewFig.4.LDO output voltage variation with and without the boost element Mps in the current efﬁcient buffer stage.It is observed that the output voltage variation is lower for the circuit implementing the current efﬁcient buffer resulting from a reduction in response time.This does not come at the expense of additional quiescent currentﬂow during zero load-current conditions.Consequently,current efﬁciency and battery life are maximized.III.C URRENT B OOSTINGA.ChallengeAs the power supply voltages decrease,the gate drive available for the PMOS pass device decreases.As a result, the aspect ratio of the power transistor needs to be increased to provide acceptable levels of output current.However,the parasitic gate capacitance also increases as the size of thePMOS transistor increases.This constitutes an increaseindown to lower frequencies.Consequently,the phase margin of the system is degraded and stability may be compromised.This presents a problem when working in a low quiescent current environment.B.Boosting TechniqueOne way to improve gate drive without increasing input voltage or device size is by forward biasing the source-to-bulk junction of the PMOS pass device.This results in a reduction of threshold voltage,commonly referred as the bulk effect phenomenon.The thresholdvoltage(10)where at a source-to-bulk voltageis the body bias coefﬁcient,andincreases,thereby effectively increasing the gate driveof the power PMOS transistor(pass device).1)Maximum Output Current:For comparative analysis,the maximum current can be observed at the region wherethe power PMOS device is in saturation,which correspondsto the nondrop-out condition.The corresponding draincurrentFig.5.Maximum load-current performance of the current boost enhance-ment.is the transconductance parameter of a PMOStransistor.Maximum output current results when the gate driveis at its peak,which occurs when the source-to-gatevoltage.Thus,ifA/V is0.9V,is30k m,andis38.5mA(assumingthatandm/A.For the same input voltage,the maximumoutput current capability is increasedasFig.6.LDO with current boosting capabilities.bias voltage is a function of load-current.This is similar to the operation of the current efﬁcient circuit of Fig.2.Thus,is close to zero at low load-currents.Athigh load-currents,however,increase,thereby decreasing the threshold voltage and increasing the gate drive of the output PMOS device.2)Drop-Out Voltage:The method of forward biasing the source-to-bulk junction also yields lower drop-out voltages.In other words,the “on”resistance of the pass device (Mpo)is reduced.When the regulator is in drop-out,Mpo is charac-teristically in the triode region and exhibits the well-known current relationshipofof the PMOS device is approxi-matelyisA/Vis 0.9V,is 30km,is 20mA,then the drop-out voltageis 296mV (corresponding to14.8becomes 216mV (corresponding to10.8is 0.5Vm/--is the transconductance ofMpo,is theimpedance of the diodeDs,--is,.This canbe illustrated by assumingthatm/(a)(b)(c)Fig.8.Ampliﬁertopologies.Fig.9.Low voltageLDO.Fig.10.Load regulation performance.is20m,is 50mA,and Mn1/Mn2have a 1:1mirror ratio;the effective transconductance of the composite power PMOS transistor isapproximatelyA/VVV,and V.IV.C IRCUIT D ESIGNThe problems of low voltage operation emerge in theform of headroom,common-mode range,dynamicrange,Fig.11.Quiescent current as a function ofload-current.Fig.12.Drop-out voltage performance at 60mA of load-current.and voltage swings.Appropriate design techniques must be implemented to approach the practical low voltage limits of a given process technology.Some of the techniques that are generally recommended are complementary input ampliﬁers and common source [emitter]gain stages.On the other hand,some of the discouraged techniques are unnecessary cascoding,Darlington conﬁgurations,and source [emitter]followers [7].At the end,however,the choice of circuit topology and conﬁguration depends on the speciﬁc application and the process technology.The theoretical headroom limit of low voltage operation is a transistor stack of one diode and one nondiode connecteddeviceFig.13.Output voltage variation (Traces A &B—without and with the transient boost)resulting from a load-current pulse train (Trace C—0to 50mA).TABLE IP ERFORMANCE SUMMARYapproximately between 0.9and 1.1V in most of today’s standard technologies.The theoretical headroom limit of low voltage for the MOSIS2--V).Thelower limit is deﬁned to provide maximum gate drive for the pass element (PMOS transistor).On the other hand,the upper limit is set by the voltage necessary to shut off the pass device,in other words,extend to just beyond the threshold voltage.This can be accomplished by a class “A”NPN emitter follower stage.This assumes that the output swing of the gain stage includes the positive power supply,approximately.The single-stage,ﬁve-transistor ampliﬁer shown in Fig.8(a)is simple enough to yield good frequency response for a given amount of quiescent current ﬂow.However,a regular current mirror load presents a problem for low-voltage operation.A regular mirror load,as seen in the ﬁgure,yields a transistor stack whose associated voltage dropisV),as illus-trated in Fig.8(b).It is basically a mirror with an emitter follower level shift.The circuit operates properly becausethe base-emitter voltage drop of the NPN transistor is less than the source-to-gate voltage of the PMOS device.The current through the NPN transistor is designed such that the parasitic pole at the gate of the PMOS device is at highfrequencies.This parasiticpoleis approximated tobe(18)whereis the transconductance of the NPN transistorandis the gate-to-source capacitance of each PMOS transistor in the mirror.Among the ampliﬁers in Fig.8,this topology exhibits the best systematic offset performance because the voltages at the collector of both NPN transistors in the differential pair are thesame,(equivalenttom technology with an added p-base layer.The Schottky diode was not included in the layout but in-stead implemented discretely.The aspect ratio of the powerdevice Mpo is 30km.The LDO produced a maximum output current of 18and 50mA at input voltages of 1and 1.2V.The circuit achieved approximately a 65%output current improvement over its noncurrent boosted counterpart,as shown in Fig.10.The quiescent current ﬂow was23A at 50mA of load-current,illustrated in Fig.11.The maximum quiescent current at full load was higher than expected by simulations,approximately180A of quiescent current at zero load-current.At 1.2V,the circuit was able to provide 50mA of output current with230Gabriel A.Rincon-Mora(S’91–M’97)was bornin Caracas,Venezuela.He received the B.S.E.E.degree with high honors from Florida InternationalUniversity,Miami,in1992and the M.S.E.E.andPh.D.degrees(named outstanding Ph.D.graduate)in electrical engineering from Georgia Institute ofTechnology,Atlanta,in1994and1996,respec-tively.He is presently working in the Linear DesignBranch with Texas Instruments Incorporated,Dallas,TX.He has been involved in the design of BiCMOSpower supply systems,i.e.,references,linear and switching regulators,powerdrivers,and associated control and protection circuitry.His general technicalinterests include low-power and low-voltage analog and mixed-signal BiC-MOS/CMOS circuit and system design.He has several patents as well aspublications in theﬁeld of integrated circuit design.Dr.Rincon-Mora is a member of Tau Beta Pi,Eta Kappa Nu,and PhiKappaPhi.Phillip E.Allen(M’62–SM’82–F’92)received thePh.D.degree in electrical engineering from theUniversity of Kansas,Lawrence,in1970.He presently is a Professor in the School ofElectrical Engineering at Georgia Institute of Tech-nology,Atlanta,and holds the Schlumberger Chair.He has worked for the Lawrence Livermore Lab-oratory,Paciﬁc Missile Range,Texas Instruments,and consulted with numerous companies.He hastaught at the University of Nevada at Reno,theUniversity of Kansas,the University of Californiaat Santa Barbara,and Texas A&M University.His technical interests includeanalog integrated circuit and systems design with focus on implementinglow-voltage and high-frequency circuits and systems in standard CMOStechnology.He is also involved in research to improve and enhance theteaching of undergraduate and graduate courses in analog circuits.He hasover40refereed publications in the area of analog circuits.He has co-authoredTheory and Design of Active Filters(1980),Switched Capacitor Filters(1984),CMOS Analog Circuit Design(1987),and VLSI Design Techniques for Analogand Digital Circuits(1990).。

Low-power reading reference circuit for split-gate

专利名称：Low-power reading reference circuit forsplit-gate flash memory发明人：Meng-Fan Chang,Hsien-Yu Pan,Ding-MingKwai,Yung-Fa Chou申请号：US11473250申请日：20060622公开号：US20070133275A1公开日：20070614专利内容由知识产权出版社提供专利附图：摘要：A low-power reading reference circuit for split-gate flash memory includes at least a pair of first reference cell and a second reference cell, which provides a readingreference current to regular cells of the split-gate flash memory. A first floating gate of the first reference cell and a second floating gate of the second reference cell are connected to an output of a logic circuit. The logic circuit receives at least one external state signal to determine whether the split-gate flash memory is ready to switch to reading mode or not, and then switches the first floating gate and the second floating gate between the state of activated and deactivated, so as to activate the first reference cell or the second reference cell to provide the reference current.申请人：Meng-Fan Chang,Hsien-Yu Pan,Ding-Ming Kwai,Yung-Fa Chou地址：Taipei City TW,Pingtung County TW,Hsinchu County TW,Kaohsiung TW国籍：TW,TW,TW,TW更多信息请下载全文后查看。

Richtek RT9049 500mA LDO调压器说明书

1DS9049-01 April 2011Ordering InformationNote :Richtek products are :` RoHS compliant and compatible with the current require-ments of IPC/JEDEC J-STD-020.` Suitable for use in SnPb or Pb-free soldering processes.ApplicationszCDMA/GSM Cellular Handsets z Portable Information Appliancesz Laptop, Palmtops, Notebook Computers z HandHeld Instrumentsz Mini PCI & PCI-Express Cards z PCMCIA & New CardsPin ConfigurationsGeneral DescriptionThe RT9049 is a high-performance, 500mA LDO regulator,offering extremely high PSRR and ultra-low dropout. The RT9049 is designed for portable RF and wireless applications with demanding performance and space requirements. The RT9049 quiescent current is as low as 115μA, further prolonging the battery life. The RT9049 also works with low-ESR ceramic capacitors, reducing the amount of board space necessary which is critical for power applications in hand-held wireless devices. The RT9049 consumes typical 1.35μA in shutdown mode and has fast turn-on time less than 40μs. The other features include ultra-low dropout voltage, high output accuracy,current limiting protection, and high ripple rejection ratio.The RT9049 is available in the SOT-23-5 package.Features500mA, Low Dropout, Low Noise Ultra-Fast Without Bypass Capacitor CMOS LDO RegulatorzWide Operating Voltage Ranges : 2.2V to 5.5V z Low Dropout : 250mV at 500mA z Ultra-Low-Noise for RF Applicationz Ultra-Fast Response in Line/Load Transient z Current Limiting Protection z Thermal Shutdown Protectionz High Power Supply Rejection Ratioz Only 10μF Output Capacitor Required for Stability z 1.35μA Shutdown Currentz TTL-Logic-Controlled Shutdown Input z RoHS Compliant and Halogen FreeSOT-23-5(TOP VIEW)Marking InformationFor marking information, contact our sales representative directly or through a Richtek distributor located in your area.Typical Application CircuitVOUTRT904912 : 1.2V2DS9049-01 April 2011Functional Pin DescriptionFunction Block DiagramENAbsolute Maximum Ratings (Note 1)z Input Voltage, V IN----------------------------------------------------------------------------------------------------------6Vz EN, V EN----------------------------------------------------------------------------------------------------------------------6Vz Power Dissipation, P D @ T A = 25°CSOT-23-5--------------------------------------------------------------------------------------------------------------------0.4Wz Package Thermal Resistance (Note 2)SOT-23-5, θJA---------------------------------------------------------------------------------------------------------------250°C/WSOT-23-5, θJC--------------------------------------------------------------------------------------------------------------25°C/Wz Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------------260°Cz Junction T emperature-----------------------------------------------------------------------------------------------------150°Cz Storage T emperature Range--------------------------------------------------------------------------------------------−65°C to 150°C z ESD Susceptibility (Note 3)HBM (Human Body Mode)----------------------------------------------------------------------------------------------2kVMM (Machine Mode)------------------------------------------------------------------------------------------------------200VRecommended Operating Conditions (Note 4)z Junction T emperature Range--------------------------------------------------------------------------------------------−40°C to 125°C z Ambient T emperature Range--------------------------------------------------------------------------------------------−40°C to 85°C Electrical Characteristics(V IN =2.7V, V EN= V IN, C IN =1μF, C OUT = 10μF(Ceramic, X7R), T A = 25°C, unless otherwise specified)DS9049-01 April 20113Note 1. Stresses listed as the above“Absolute Maximum Ratings”may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity single layer test board of JEDEC 51-3 thermal measurement standard. The case position of θJC is on the package top of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended.Note 4. The device is not guaranteed to function outside its operating conditions.Note 5. Quiescent, or ground current, is the difference between input and output currents. It is defined by I Q = I IN-I OUT under no load condition (I OUT = 0mA). The total current drawn from the supply is the sum of the load current plus the ground pin current.Note 6. Regulation is measured at constant junction temperature by using a 2ms current pulse. Devices are tested for loadregulation in the load range from 10mA to 500mA.DS9049-01 April 2011 45DS9049-01 April 2011Line Transient Response Time (100μs/Div)3.62.6V IN (1V/Div)20−20V OUT(20mV/Div)V IN = 2.6V to 3.6V, V OUT = 1.2V, I OUT = 100mATypical Operating CharacteristicsOutput Voltage vs. Temperature1.1001.1251.1501.1751.2001.2251.2501.2751.300-50-25255075100125Temperature O u tp u t V o l t a g e (V )(°C)Quiescent Current vs. Temperature8090100110120130140-50-25255075100125Temperature Q ui e s c e n t C u r r e n t (μA )(°C)Load Transient ResponseTime (500μs/Div)V IN = 2.75V, V OUT = 1.2V, I OUT = 10mA to 100mAV OUT (5mV/Div)I OUT(50mA/Div)Power On-Off from EN Time (100μs/Div)V EN (1V/Div)V OUT (0.5V/Div)V IN = 2.75V, V OUT = 1.2V, I OUT = 50mALine Transient ResponseTime (100μs/Div)3.62.6V IN (1V/Div)20−20V OUT(20mV/Div)V IN = 2.6V to 3.6V, V OUT = 1.2V, I OUT = 10mA6DS9049-01 April 2011PSRR-70-60-50-40-30-20-1001020101001000100001000001000000Frequency (Hz)P S R R (d B )Load Transient ResponseTime (500μs/Div)V OUT (5mV/Div)I OUT(100mA/Div)V IN = 2.75V, V OUT = 1.2V, I OUT = 10mA to 300mANoiseTime (10msDiv)V OUT(100μV/Div)V IN = 4.5V (By Battery), V OUT = 1.2V, No LoadNoiseTime (10msDiv)V OUT(100μV/Div)V IN = 4.5V (By Battery), V OUT = 1.2V, I OUT = 10mA7DS9049-01 April 2011Applications InformationLike any low-dropout regulator, the external capacitors used with the RT9049 must be carefully selected for regulator stability and performance. Using a capacitor more than 1μF on the RT9049 is suitable. The input capacitor must be located at a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground.The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response.The output capacitor must meet both requirements for minimum capacitance and ESR in all LDOs application.The RT9049 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 10μF with ESR is > 45m Ω on the RT9049 output ensures stability. The RT9049 still works well with output capacitor of other types due to the wide stable ESR range.Figure 1. shows the curves of allowable ESR range as a function of load current for various output capacitor values.Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR.The output capacitor should be located at less than 0.5inch from the VOUT pin of the RT9049 and returned to a clean analog ground.Figure 1.Region of Stable C OUT ESR vs. Load CurrentEnableThe RT9049 goes into sleep mode when the Enable pin is in a logic low condition. During this condition, the pass transistor, error amplifier, and bandgap are turned off,reducing the supply current to 1.35μA typical. The Enable pin may be directly tied to V IN to keep the part on. The Enable input is CMOS logic and cannot be left floating.PSRRThe power supply rejection ratio (PSRR) is defined as the gain from the input to output divided by the gain from the supply to the output. The PSRR is found to be ⎟⎟⎠⎞⎜⎜⎝⎛ΔΔ×=Supply Error Gain log 20 PSRR Note that when heavy load measuring, Δsupply will cause Δtemperature. And Δtemperature will cause Δoutputvoltage. So the heavy load PSRR measuring is includes temperature effect.Current LimitThe RT9049 contains an independent current limiter, which monitors and controls the pass transistor's gate voltage,limiting the output current to 0.6A (typ.). The output can be shorted to ground indefinitely without damaging the part.Thermal ConsiderationsFor continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient.The maximum power dissipation can be calculated by following formula :P D(MAX) = (T J(MAX) − T A ) / θJAWhere T J(MAX) is the maximum operation junction temperature, T A is the ambient temperature and the θJA is the junction to ambient thermal resistance.For recommended operating conditions specification of RT9049, the maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For SOT-23-5 package, the thermal resistanceRegion of Stable C OUT ESR vs. Load Current0.010.11101000.10.20.30.40.5Load Current (mA)R e g i o n o f S t a b l e C O U T E S R (Ω)8DS9049-01 April 20119DS9049-01 April 2011Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.Richtek Technology CorporationHeadquarter5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C.Tel: (8863)5526789 Fax: (8863)5526611Richtek Technology CorporationTaipei Office (Marketing)5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C.Tel: (8862)86672399 Fax: (8862)86672377Email:*********************Outline DimensionA1HLSOT-23-5 Surface Mount Package。

A low-noise, low-power VCO

A Low-Noise,Low-Power VCO with AutomaticAmplitude Control for Wireless ApplicationsMihai A.Margarit,Joo Leong(Julian)Tham,Member,IEEE,Robert G.Meyer,Fellow,IEEE,and M.Jamal Deen,Senior Member,IEEE Abstract—Voltage-controlled oscillators(VCO’s)used inportable wireless communications applications,such as cellulartelephony,are required to achieve low phase-noise levels whileconsuming minimal power.This paper presents the designchallenges of a monolithic VCO with automatic amplitudecontrol,which operates in the300MHz to1.2GHz frequencyrange using different external resonators.The VCO phase-noiselevel is0106dBc/Hz at100-KHz offset from an800-MHzcarrier,and it consumes1.6mA from a2.7-V power supply.An extensive phase-noise analysis is employed for this VCOdesign in order to identify the most important noise sourcesin the circuit and toﬁnd the optimum tradeoff between noiseperformance and power consumption.Index Terms—Phase noise,voltage-controlled oscillator(VCO),wireless applications.I.I NTRODUCTIONT HE remarkable growth in telecommunication systems,such as cellular telephony,demands continuous efforts to-ward the improvement of radio-frequency(RF)circuit perfor-mance at ever increasing levels of plete trans-ceiver solutions that integrate low-noise ampliﬁers(LNA’s),mixers,voltage-controlled oscillators(VCO’s),and transmitmodulators already exist.Moreover,the stringent noise andspurious emissions requirements for cellular communicationssystems,such as GSM,DCS,and PCS,need to be achievedwith even lower power-consumption levels.This paper describes the analysis and implementation ofa monolithic VCO with automatic amplitude control(AAC),which is part of a one-chip transceiver dedicated for dual-bandcellular systems[1].The VCO is capable of operating from300MHz to1.2GHz using different resonators.The measuredphase-noise level is(a)(b)Fig.1.(a)Simpliﬁed diagram of a voltage-controlled oscillator.(b)V oltage-controlled oscillator with damping resistor R s:has negligible effect on the fundamental mode[2].However,care needs to be taken in the design,since too large a valueoffor the differential ampliﬁer in order to maintain constantMARGARIT et al.:LOW-NOISE,LOW-POWER VCO763Fig.2.Schematic of the VCO with AAC.gain.for minimum phase-noise levels largely independent of considerations for proper oscillation startup. In steady-state operation,the AAC loop forces the dc signal provided by the rectiﬁer and the low-passﬁlter at the sensing input to track the reference level applied at the reference input.This leads to the second advantage of using the AAC circuit of enabling the VCO to provide constant output power independent of theresonator(3)Since the system is timevariant,and observation timein(3)with theequivalent noise source of each individual node,the phase-noise contribution of each node can be calculated[5].To explore the oscillator excess phase response,each nodeof the circuit needs to be excited at evenly distributed timesteps of the oscillation period.Due to thehighis an integer chosen such that the oscillation waveform hassettled before the next pulse is applied.The ramp generator isreset by theﬁrst positive-going zero crossing of the oscillation.The ramp is then compared in COMP2with a staircase voltage,which is incremented ateachis the number of pulses to be injected.In this way,pulses areinjected with a period equalto764IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.34,NO.6,JUNE1999(a)(b)(c)Fig.3.(a)Sequence of pulses used to excite the oscillator.(b)Block diagram of the behavioral test generator.(c)VCO test points for phase sensitivity to injectedcharge.Fig.4.Impulse shape.is almost constant from DC to 25GHz,which is sufﬁcient for this design that uses a bipolar processwithCurrentsourcethe effect of thenoise voltage generatedbytheeffect of the resistive losses in theresonator(5)(6)The collector shot noise oftransistormA).Thecyclostationarityofis8.6MARGARIT et al.:LOW-NOISE,LOW-POWER VCO765Fig.5.Tail-current noise spectrum.(a)(b)Fig.6.(a)VCO output waveform.(b)Simulated function h8;I(t; )(vertical axis in degrees/pC).across the nodes“out”and“outb”(Fig.2),and it has thevaluefor current pulsesinjected at the tail of the emitter-coupled pair.This functionhas a periodicity that is half the oscillation period.To obtainmore meaningful information on the phase sensitivity forperturbations in the tail current of the VCO,the functionis plotted together with the oscillation outputwaveform.It can be seen that for perturbations injectedaround the zero crossings and the peaks of the oscillation,the phase sensitivity is close to zero and reaches its maxima766IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.34,NO.6,JUNE1999Fig.7.Frequency spectrum of h 8;I (t; )(vertical axis in dBV).forwhereis shown in Fig.7.As expected,there areharmonics at multiples of double the oscillation frequency.The harmonics mix with the noise around these frequencies and contribute to the total phase noise.For calculation of the phase-noise contribution from the tail current,the Fourier coefﬁcientsof[4]th harmonic of the oscillation fre-quency.In this analysis,the summation is performed over the ﬁrst ﬁve harmonics.Higher order harmonics have insigniﬁcant contribution to the phase noise.Of particular interest is the dc component,coefﬁcientregion of the phase noiseintersectstheis deﬁnedas(9)In the aboveequation,andhas a period equalto the oscillation period.Again,in order to see the effect of this noise source,the oscillation output waveform and the collector currentofreaches its maximum when the collector currentis close to the peak,and it reaches the minimumwhenin Fig.9show that thecollector shot noise is mixed mostly with the ﬁrst and second harmonics of the oscillation frequency to contribute to the total phase noise.However,the collector shot noiseofwas performed.Todo this,theratioMARGARIT et al.:LOW-NOISE,LOW-POWER VCO767(a)(b)(c)Fig.8.(a)VCO output waveform.(b)Collector current of Q1.(c)Simulated functions h8;IIt768IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.34,NO.6,JUNE 1999Fig.9.Frequency spectrum of h 8e (t; )(vertical axis in dBV).Fig.10.Phase noise (continuous line)and ﬁgure of merit (dashed line)versus feedback ratio n:TABLE IN OISE C ONTRIBUTIONS AT100-kHz O FFSET FROM AN 800-MHz C ARRIERAlthough the noise contribution from the tail current is not important at this offset frequency,it becomes the major noise source at offset frequencies less than 3kHz.The factor of two for some of the noise sources in Table I accounts for noise sources that are considered twice due to the circuit symmetry [5].The sum of these values gives a noise-to-signal ratio ofregion of the spectrum.SpectreRFpredicts a phase-noise level ofMARGARIT et al.:LOW-NOISE,LOW-POWER VCO769parison of the phase noise calculated with phase noise simulated in SpectreRF.Fig.12.Microphotograph of the VCO with AAC.However,the current version of SpectreRF did not predictthe43dBc and the third harmonic is106dBc/Hz at100-770IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.34,NO.6,JUNE1999Fig.13.VCO outputspectrum.Fig.14.Measured phase noise.kHz offset for a carrier frequency of 800MHz,which is in agreement with the analysis presented in this paper (Fig.14).The VCO core consumes 1.6mA from a 2.7-V power supply.The remaining circuits used for the AAC (rectiﬁer,voltage reference,and ampliﬁer)consume 0.25mA.If better phase-noise performance is desired,only the current consumption inthe VCO core needs to be increased,while the consumption of the AAC circuits remains unchanged.V.C ONCLUSIONSIn this paper,the possibilities of developing a low-noise,low-power VCO with capabilities for wireless applicationsMARGARIT et al.:LOW-NOISE,LOW-POWER VCO 771have been explored.An automatic amplitude control circuit was implemented,which allows the choice of the optimum oscillator feedback ratio for noise performance without being constrained by startup considerations.At the same time,the automatic amplitude control allows proper VCO operation for a wide range of the resonator quality factor.A novel method was used to study the phase-noise performance of the VCO.The method predicts results that are close to the measurements and allows the designer to obtain detailed information about the processes that contribute to oscillator phase noise.A CKNOWLEDGMENTThe authors would like to thank Dr.C.Hull and R.Magoon for helpful discussions.R EFERENCES[1]J.L.Tham,M.Margarit,B.Pregardier, C.Hull,and F.Carr,“A2.7V 900MHz/1.9GHz dual-band transceiver IC for digital wireless communication,”in Proc.CICC ,1998,p.559.[2]J.L.Tham,“Integrated radio frequency LC voltage-controlled oscil-lators,”College of Engineering,University of California,Berkeley,Electronics Research Laboratory Memo.,1995.[3]P.Davis,P.Smith,E.Campbell,J.Lin,K.Gross,G.Bath,Y.Low,M.Lau,Y.Degani,J.Gregus,R.Frye,and K.Tai,“Si-on-Si integration of a GSM transceiver with VCO resonator,”in Proc.ISSCC 1998,vol.41,Feb.1998,p.248.[4] A.Hajimiri and T.H.Lee,“A general theory of phase noise in electricaloscillators,”IEEE J.Solid-State Circuits ,vol.33,pp.179–194,Feb.1998.[5] C.D.Hull and R.G.Meyer,“A systematic approach to the analysisof noise in mixers,”IEEE Trans.Circuits Syst.I ,vol.40,pp.909–919,Dec.1993.Mihai A.Margarit received the Dipl.Ing.degree in electrical engineering from the “Politehnica”Uni-versity Bucharest,Romania,in 1984.He currently is pursuing the Ph.D.degree in electrical engineering at Simon Fraser University,Burnaby,B.C.,Canada.Since 1984,he has worked in analog circuit design for the National Institute for Microelectron-ics,Bucharest,the Fraunhofer Institute,Erlangen,Germany,and Simon Fraser University,Vancouver,Canada.He is currently with Rockwell Semicon-ductor Systems,Newport Beach,CA,where he isa Senior Design Engineer working on high-frequency circuits for wireless communicationapplications.Joo Leong (Julian)Tham (S’88–M’96)received the B.S.degree in electrical engineering (with high-est honors)from the University of California,Santa Barbara,and the M.S.degree in electrical engineer-ing from the University of California,Berkeley.He has worked at Raytheon and Trimble Navi-gation.His previous work includes autocalibration systems and global positioning system receivers.From 1993to 1999,he was with Rockwell Semi-conductor Systems,Newport Beach,CA,where he was a Principal Design Engineer and Managerworking on radio-frequency integrated circuits for wireless communication applications.He currently is with Maxim Integrated Products,Sunnyvale,CA.His current interests are in the areas of high-frequency circuit design and integrated transceiver architectures.Mr.Tham is a member of Eta Kappa Nu,Tau Beta Pi,and the Golden Key Honor Society.He was named Rockwell Semiconductor Systems Engineer of the Year in1995.Robert G.Meyer (S’64–M’68–SM’74–F’81)was born in Melbourne,Australia,on July 21,1942.He received the B.E.,M.Eng.Sci.,and Ph.D.degrees in electrical engineering from the University of Melbourne in 1963,1965,and 1968,respectively.In 1968,he was an Assistant Lecturer in electrical engineering at the University of Melbourne.Since September 1968,he has been with the Department of Electrical Engineering and Computer Sciences,University of California,Berkeley,where he is now a Professor.His current research interests are high-frequency analog integrated-circuit design and device fabrication.He has been a Consultant on electronic circuit design for numerous companies in the electronics industry.He is a coauthor of Analysis and Design of Analog Integrated Circuits (New York:Wiley,1993)and Editor of Integrated Circuit Operational Ampliﬁers (New York:IEEE Press,1978).Dr.Meyer was President of the IEEE Solid-State Circuits Council and was an Associate Editor of the IEEE J OURNAL OF S OLID -S TATE C IRCUITS and of the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS.M.Jamal Deen (S’81–M’86–SM’92)was born in Georgetown,Guyana.He received the B.Sc.degree in physics and mathematics from the University of Guyana in 1978and the M.S.and Ph.D.degrees in electrical engineering and applied physics from Case Western Reserve University,Cleveland,OH,in 1982and 1985,respectively.From 1978to 1980,he was an Instructor of physics at the University of Guyana.From 1980to 1983,he was a Research Assistant at Case Western Reserve University.He was a Research Engineer(1983–1985)and an Assistant Professor (1985–1986)at Lehigh University,Bethlehem,PA.In 1986,he joined the School of Engineering Science,Simon Fraser University,Vancouver,BC,Canada,as an Assistant Professor and since 1993has been a full Professor.He was a Visiting Scientist at the Herzberg Institute of Astrophysics,National Research Council,Ottawa,Ont.,Canada,in summer 1986,and he spent his sabbatical leave as a Visiting Scientist at Northern Telecom,Ottawa,in 1992–1993.He was also a Guest Professor in the Faculty of Electrical Engineering,Delft University of Technology,The Netherlands,in summer 1997and a CNRS scientist at the Physics of Semiconductor Devices Laboratory,Grenoble,France,in summer 1998.His current research interests include integrated devices and circuits;device physics,modeling,and characterization;and low-power,low-noise,high-frequency circuits.Dr.Deen is a member of Eta Kappa Nu,the American Physical Society,and the Electrochemical Society.He was a Fulbright-Laspau Scholar from 1980to 1982,an American Vacuum Society Scholar from 1983to 1984,and an NSERC Senior Industrial Fellow in 1993.。

线性技术 lmt9001 16 位接收子系统 dc1398a 评估电路说明书

1 DC1250 DESCRIPTIONDemonstration circuit 1398 is an evaluation board featur-ing Linear Technology Corporation’s LTM9001 16-bit Receiver Subsystem. DC1398 demonstrates good circuit layout techniques and recommended external circuitry for optimal system performance.DC1398 comes with Linear Technology’s 16-bit LTM9001 amplifier/ADC subsystem installed. The board includes a wideband input transformer (for evaluation with a single-ended RF signal generator) and output CMOS buffers.DC1398 plugs into the DC890 Data Ac-quisition demo board and the output can be easily ana-lyzed with Linear Technology’s PScope data processing software, which is available for no charge on our website at .Design files for this circuit board are available. Call the LTC factory., LTC and LT are registered trademarks of Linear Technology Corporation.QUICK START PROCEDUREValidating the performance of the LTM9001 is simple with DC1398, and requires only an input source, a clock source, a computer, and a lab power supply. Refer to Figure 1 for proper board evaluation equipment setup and follow the procedure below:1. Connect the power supply as shown in Figure 1.There are on-board low-noise voltage regulators that provide the three supply voltages for the LTM9001.The entire board and all components share a com-mon ground. The power supply should still be a low-noise lab power supply capable of supplying at least1 Amp.2. Provide an encode clock to the ADC via SMA con-nector J3. Use a low-phase-noise clock source such as a filtered RF signal generator or a high-quality clock oscillator. Obtain DC1216 for a low-phase-noise ADC clock source that can plug directly into DC1398.NOTE. Similar to having a noisy input, a high-jitter (phase noise)encode clock will degrade the signal-to-noise ratio (SNR) of thesystem.Table 1: DC1398 Connectors and JumpersREFERENCE FUNCTIONJ1 (AIN-) Differential Board Input. Normally not con-nected. See text for differential-input evalua-tion methods.J2 (AIN+) Board Signal Input. Impedance-matched to50Ω for use with lab signal generators.J3 (ENC) Board Clock Input. Impedance-matched to50Ω. Drive with a low-phase-noise clock oscil-lator or filtered sine wave signal source.E1 (EXT REF) Reference input to adjust the full-scale range ofthe LTM9001. Connects to the SENSE pin; bydefault, tied to VDD for internal reference.E2 (VS) DC Supply input (3.8 to 6VDC).E3 (GND) DC ground.JP1 (PGA_GAIN) Selects the input range of LTM9001. Default isLOW (low PGA gain, larger input range) JP2 (RAND) Output Randomizer. Default is NORM.JP3 (ADC_SHDN) Enables the LTM9001 ADC. Default is NORM.JP4 (DITH) ADC Internal Dither. Default is OFF.JP5 (AMP_EN) Enables the LTM9001 amplifier. Default is EN. 3. Apply an input signal to the board. DC1398 allows great flexibility in applying input signals (see the sec-tion on Applying Input Signals). For best results, use a low distortion, low noise signal generator with suffi-cient filtering to avoid degrading the performance of the amplifier and ADC.4. Observe the ADC output with demo circuit DC890, aUSB cable, a Windows computer, and Linear Tech-nology’s Pscope data processing software.DEMO CIRCUIT 1398QUICK START GUIDELTM9001 16-bit High Performance ADC DriversADDITIONAL INFORMATIONAlthough the DC1398 demo board is ready to use on de-livery, it has additional flexibility built in for various types of input networks. Below is some information about con-figuring DC1398 to meet the specific needs of your eval-uation.APPLYING INPUT SIGNALSThe input network consists of various components de-signed to allow either single-ended or differential inputs, AC-coupled or DC-coupled. Table 2 shows some possi-ble input configurations, and which components to in-stall. LTM9001 is designed for excellent performance with both single-ended and differential input drive, with little difference in distortion performance. When using DC-coupled inputs, the inputs to DC1398 need to be lev-el-shifted to within the input common-mode limits in the datasheet.Table 2: DC1398 Input Configuration Guide CONFIGURATION COMPONENTS NECESSARYSingle-Ended InputAC-Coupled(Default Setup)No change. Transformer T1 acts as a balun for differential drive. Single-Ended InputNo TransformerAC-CoupledRemove T1, replace with 0Ω jumpers. May need to install impedance-matching resistor at R4 or R2/R6. Single-Ended InputNo TransformerDC-CoupledSame as above. Change C1 and C8 to 0Ω jump-ers. Inputs must be within the common-mode voltage limits of LTM9001. Differential InputsRemove R7 and install R5. T1 and C1/C8 can be replaced with 0Ω for DC coupling.NOTE. When driving the ADC driver with a direct DC-coupled path, increased input bias currents may occur due to the amplifier’s input impedance. See the LTM9001 datasheet for more details.OTHER BOARD CIRCUITRYDevice U5 is an EEPROM device that is used by the PScope software to identify the board and apply the cor-rect settings for the data collection.USING PSCOPE SOFTWAREPScope, downloadable from Linear Technology’s website /, processes data from the DC890 FastDAACS board and displays FFT and signal analysis information on the computer screen. The on-board EEPROM U5 should enable automatic board detection and auto-configuration of the software, but if the user wishes to change the settings, theycaneasily do so.From the Configure menu in the toolbar, uncheck “Auto-detect Device”. The default settings for DC1398 areshown in Figure 2. The LTM9001 also has an output ran-domizer, which the user needs to select if it is enabled onthe board. The software will automatically un-randomizethe output by performing an exclusive-OR with each bitand the LSB.Figure 2. Entering the correct device information for your ADC. Select the correct parameters for the DC1398. Under normal conditions, PSCOPE should automatically recognize the board and adjust the software settings accordingly.Figure 3. Schematic。

Agile Low-Noise Frequency Synthesizer

Agile Low-Noise Frequency SynthesizerA. RidenourR. AurandSpectrum Microwave Abstract—Simultaneously achieving low phase noise, fast switching speed and acceptable levels of spurious outputs in microwave frequency synthesizers has long been considered difficult. Presented here is a description of a solution developed by Spectrum Microwave to achieve such resultsIntroductionThe need for spectrally pure signal sources capable of fast frequency hopping for such applications as spread spectrum data links and Doppler radar has been growing. Traditional synthesizer architectures, such as Direct Analog Synthesis, single or multi loop analog or digital PLL’s or Mix and Divide, all have weaknesses when it comes to switching time. Direct Digital Synthesis (DDS) is capable of fast switching however, from a microwave perspective, it remains in the low frequency domain.A hybrid approach of up converting a DDS against a microwave LO signal can combine the advantages of DDS while reducing the shortcomings of other approaches.A Hybrid Frequency SynthesizerSpectrum Microwave Model 96999 is a state-of-the-art low noise frequency synthesizer targeted at applications requiring low phase noise and frequency agility. Figure 1 is a general block diagram of the frequency synthesizer. Two architectural features are notable:1.The synthesizer is built around a low noise crystal oscillator. Alloutput frequencies from the LO Generator Module are generated by multiplying and filtering the crystal signal before mixing witha signal generated by the DDS. Clock signals for the DDS arealso derived from this high performance crystal oscillator bymultiplication and filtering. This technique ensures the lowestpossible phase noise while retaining flexible frequency control.2.The design is scalable. The native bandwidth occupies a 200MHz slice of spectrum which may be converted anywhere withinthe microwave spectrum by suitable selection of multipliers andfilters during the design phase. Wider bandwidths areaccommodated by adding more mix/filter stages to theUpconverter Module and using appropriate RF switchingnetworks to select the desired range.Figure 1Phase NoiseFigure 2 shows the single-sideband phase noise spectral density plot for a typical crystal reference oscillator employed in the model 96999 frequency synthesizer. This ovenized oscillator design is based on SC cut crystal technology.Figure 2SSB Phase Noise of Crystal Reference OscillatorFigure 3SSB Phase Noise of Frequency SynthesizerFigure 3 shows the measured phase noise of a typical synthesizer when it is tuned to 3 GHz. Table 1 compares the measured phase noise densities and computes the difference between the scaled 100 MHz reference crystal oscillator and the 3 GHz output. All readings in the table are corrected by 3dB for 2 source measurement. The final column in Table 1 contains the best theoretically available phase noise, computed using the equation:Phase Noise = 20 * log (N)WhereN = (3 GHz / 100 MHz )For the example given this equation resolves to 29.5 dB. Multiplying the 100 MHz crystal reference signal to 3 GHz will degrade the phase noise of the crystal by at least 29.5 dB.As can be seen in the Table, at low offset frequencies the Model 96999 phase noise exceeds the 20 log(N) factor by several dB. However at 1 kHz offset the noise is approximately equal to 20 log(N). The noise situation is somewhat different at larger offset frequencies and ultimately the farther out noise floor is determined by other elements in the signal chain.Offset FrequencyCrystalOscillator3 GHzoutputDifference 20 log N10 Hz -98 dBc -73 dBc 25 dB100 Hz -130 dBc -105 dBc 25 dB1 kHz -155 dBc -125 dBc 30 dB10 kHz -165 dBc -133 dBc 32 dB100 kHz -167 dBc -134 dBc 33 dB29.5 dBTable 1The data in Table 1 describes the phase noise performance that can be achieved at any output frequency within the tuning range of the frequency synthesizer. Selection of output frequency is limited only by the step size resolution of the synthesizer. Fine step resolution is a function of the DDS programming.Tuning SpeedIncorporating DDS technology into frequency synthesizers in this fashion brings another unique advantage to the Spectrum Microwave product. DDS frequency selection can be fast. Tuning speed within any 200 MHz sub-band is typically limited by the data interface, typically less than 1 µsec.In cases where the fastest tuning speeds are desired, a wide parallel interface offers the best solution. Slower tuning speeds can be achieved with any of the I2C or serial communications protocols. Jumping across band segments imposes minimal switching time overhead, typically measured in 10’s of nanoseconds. Band switching can be either internal, using ROM based look-up tables, or discrete band switch lines can be brought to the parallel interface for direct control.Spurious OutputsWhenever frequency multipliers and multiple conversions are used in a frequency generation scheme, control of spurious outputs must be taken seriously during the design and planning stages. The Spectrum Microwave frequency synthesizers achieve the desired low spurious levels by judiciously placement of multi-pole bandpass filters in the signal path. In cases where multiple sub-bands are used, filters are switched.PackagingUltimate isolation of frequency generating stages, and thus lowest possible spurious levels, demands keeping the various signal processing stages physically separated. Figure 3 shows a synthesizer configuration using multiple interconnected housings mounted on an aluminum baseplate. Also shown in the figure is an optional vibration isolation system for the crystal oscillator. More will be said about this feature later.Figure 3Mechanical ConfigurationFor less demanding applications a more compact arrangement can be used and this is shown in Figure 4. Also visible in this figure is a thumb-wheel switch used for selecting a nominal center output frequency. In this design variant the DDS control interface uses a serial RS-232 link allowing “steering” of the synthesizer frequency between pulses of a Magnetron Doppler Radar used for an atmospheric imaging application.Figure 4Compact Frequency SynthesizerSynchronizationSome applications of low noise, fast tuning frequency synthesizers may require frequency synchronization to an external reference frequency such as Rubidium or Caesium primary standards. Or a need may exist for multiple frequency synthesizers to be operated in a master/slave configuration. To address these requirements the low-noise VHF crystal oscillator is phase-locked to the external reference signal using an additional phase locked loop.Figure 5 shows the typical phase noise of a VHF crystal oscillator when phase locked to an external reference frequency. As can be seen, phase noise is somewhat degraded from the ideal case presented earlier using an optimized phase noise condition. Clearly seen in this graph is the noise plateau resulting from the phase detector noise floor transferring to the output of the PLL.Many configurations using external frequency references are possible and optimal trade-off between loop bandwidth and phase noise is best determined at the system level.Figure 5SSB Phase Noise of Phase-Locked Crystal OscillatorShock and VibrationMany applications are subject to some physical vibration, even if it is just fan noise in equipment racks. For these situations vibration isolation of the VHF crystal oscillator is possible. A suitable strategy calls for designing the VHF oscillator mechanical assembly in a way that minimizes transmission of the vibration through the housings. Without isolation, vibration will ruin the low phase noise performanceof the quartz crystals used in the VHF oscillators.For More InformationContact:Art RidenourSr. TechnologistSpectrum Microwave1900 W. College AveState College, PA 16801Tele: 814-272-2700ridenourr@ConclusionDesign considerations for an agile, low noise microwave frequency synthesizer have been discussed. Some design data highlighting low phase noise has been presented. Several of the possible packaging options have been presented.INTELLECTUAL PROPERTY NOTICEThe design concepts presented in this paper are offered for considerationin developing specific solutions for our customers, and remain the exclusiveproperty of Spectrum Microwave. Any unauthorized copying, distribution,or conversion of the contents of this paper for other purposes without theprior written consent of Spectrum Microwave is strictly prohibited.。

NORMA 4000 5000 Power Analyzer 用户说明手册说明书

Since some countries or states do not allow limitation of the term of an implied warranty, or exclusion or limitation of incidental or consequential damages, the limitations and exclusions of this warranty may not apply to every buyer. If any provision of this Warranty is held invalid or unenforceable by a court or other decision-maker of competent jurisdiction, such holding will not affect the validity or enforceability of any other provision.
BEGRENZTE GEWÄHRLEISTUNG UND HAFTUNGSBESCHRÄNKUNG
Fluke gewährleistet, daß jedes Fluke-Produkt unter normalem Gebrauch und Service frei von Material- und Fertigungsdefekten ist. Die Garantiedauer beträgt 2 Jahre ab Versanddatum. Die Garantiedauer für Teile, Produktreparaturen und Service beträgt 90 Tage. Diese Garantie wird ausschließlich dem Erster

500mA 低噪声 LDO 电压调节器使用手册说明书

Rev. 2.0.5GENERAL DESCRIPTIONThe SPX3819 is a positive voltage regulator with a low dropout voltage and low noise output. In addition, this device offers a very low ground current of 800μA at 100mA output. The SPX3819 has an initial tolerance of less than 1% max and a logic compatible ON/OFF switched input. When disabled, power consumption drops to nearly zero. Other key features include reverse battery protection, current limit, and thermal shutdown. The SPX3819 includes a reference bypass pin for optimal low noise output performance. With its very low output temperature coefficient, this device also makes a superior low power voltage reference.The SPX3819 is an excellent choice for use in battery-powered applications such as cordless telephones, radio control systems, and portable computers. It is available in several fixed output voltage options or with an adjustable output voltage.This device is offered in 8 pin NSOIC, 8 pin DFN and 5-pin SOT-23 packages. APPLICATIONS•Portable Consumer Equipment •Portable Instrumentation•Industrial Equipment•SMPS Post RegulatorsFEATURES•Low Noise: 40μV Possible•High Accuracy: 1%•Reverse Battery Protection•Low Dropout: 340mV at Full Load•Low Quiescent Curre nt: 90μA•Zero Off-Mode Current•Fixed & Adjustable Output Voltages: −1.2V, 1.5V, 1.8V, 2.5V, 3.0V, 3.3V & 5.0VFixed Output Voltages−≥1.235V Adjustable Output Voltages •Available in RoHS Compliant, Lead Free Packages:−5-pin SOT-23, 8-pin SOIC and 8-pin DFNTYPICAL APPLICATION DIAGRAMFig. 1: SPX3819 Application CircuitABSOLUTE MAXIMUM RATINGSThese are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.V IN, EN ..................................................... -20V to +20V Storage Temperature .............................. -65°C to 150°C Junction Temperature .......................................... 150°C Power Dissipation ................................ Internally Limited Lead Temperature (Soldering, 5 sec) ..................... 260°C ESD Rating (HBM - Human Body Model) .................... 1kV OPERATING RATINGSInput Voltage Range V IN................................ 2.5V to 16V Enable Pin EN ............................................... 0.0V to V IN Junction Temperature Range ................. -40°C to +125°C Thermal Resistance1..................................................... θJA (SOT23-5) ...............................................191°C/W θJA (NSOIC-8) ............................................ 128.4°C/W θJA (DFN-8) ................................................... 59°C/W Note 1: The maximum allowable power dissipation is a function of maximum operating junction temperature, T J(max) the junction to ambient thermal resistance, and theambient θJA, and the ambient temperature T A. The maximum allowable power dissipation at any ambient temperature is given: P D(max)= (T J(max)-T A)/θJA, exceeding the maximum allowable power limit will result in excessive die temperature; thus, the regulator will go into thermal shutdown.ELECTRICAL SPECIFICATIONSSpecifications with standard type are for an Operating Junction Temperature of T J = 25°C only; limits applying over the full Operating Junction Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T J = 25°C, and are provided for reference purposes only. Unless otherwise indicated, V IN = V OUT + 1V (V IN = V OUT + 1.2V for 1.2V option), I L= 100µA, C L = 1µF, V EN≥ 2.5V, T A= T J = 25°C.Parameter Min. Typ. Max. Units ConditionsOutput Voltage Tolerance -1 +1%-2 +2 •Output Voltage TemperatureCoefficient 57 ppm/°CLine Regulation 0.04 0.1%/VV IN = V OUT +1 to 16V and V EN≤ 6V0.2 • V IN = V EN = V OUT +1 ≤ 8V0.2 V IN = V EN = V OUT +1 ≤16VT A = 25°C to 85°CLoad Regulation 0.05 0.4 % I L= 0.1mA to 500mADropout Voltage (V IN-V OUT) 210 60mVI L = 100µA80 •125 175I L= 50mA250 •180 350I L= 150mA450 •340 550I L= 500mA700 •Quiescent Current (I GND) 0.05 3µAV ENABLE≤ 0.4V8 • V ENABLE = 0.25VGround Pin Current (I GND) 90 150µAI L = 100µA190 •250 650I L= 50mA900 •1.02.0mAI L= 150mA2.5 •6.5 25.0I L= 500mA30.0 •Ripple Rejection (PSRR) 70 dBParameterMin. Typ. Max. Units ConditionsCurrent Limit (I LIMIT )800 mAV OUT =0V 950 • Output Noise (e NO )300 µV RMS I L = 10mA, C L = 1.0µF, C IN = 1µF, (10Hz – 100kHz)40 µV RMS I L = 10mA, C L = 1.0µF, C BYP = 1µF, C IN = 1µF, (10Hz – 100kHz) Input Voltage Level Logic Low (V IL )0.4 V OFF Input Voltage Level Logic High (V IH )2 V ONENABLE Input Current0.01 2 µAVIL ≤ 0.4V VIH ≥ 2.0V320Note 2: Not applicable to output voltage 2V or less.PIN ASSIGNMENTFig. 2: SPX3819 Pin AssignmentPIN DESCRIPTIONName Pin #nSOICPin # DFN Pin # SOT-23 DescriptionVIN 2 3 1 Supply Input GND 5, 6, 7, 87 2 GroundVOUT 3 5 5 Regulator OutputEN 113Enable(input). CMOS compatible control input. Logic high – enable; logic low or open = shutdownADJ 4 8 4Adjust able part only. Feedback input. Connect to resistive voltage-divider networkBYP Fixed version only. Internal reference bypass pin. Connect 10nF to ground to reduce thermal noise on the output. NC-2, 4, 6-No ConnectORDERING INFORMATION(1)Part Number Operating Temperature Range Lead-Free Package Packaging Method SPX3819M5-L/TR-40°C≤T J≤+125°C Yes(2)SOT-23-5Tape & ReelSPX3819M5-L-1-2/TRSPX3819M5-L-1-5/TRSPX3819M5-L-1-8/TRSPX3819M5-L-2-5/TRSPX3819M5-L-3-0/TRSPX3819M5-L-3-3/TRSPX3819M5-L-5-0/TRSPX3819R2-L/TRDFN-8 SPX3819R2-L-1-2/TRSPX3819S-L/TRNSOIC-8 SPX3819S-L-5-0/TRNOTES:1.Refer to /SPX3819 for most up-to-date Ordering Information2.Visit for additional information on Environmental Rating.TYPICAL PERFORMANCE CHARACTERISTICSFig. 3: Ground Current vs Load Current Fig. 4: Ground Current vs Input VoltageFig. 5 Ground Current vs Load Current in Dropout Fig. 6 Output Voltage vs Input VoltageFig. 7 Dropout Voltage vs Load Current Fig. 8 Output Voltage vs Load CurrentFig. 9 Ground Current vs Temperature with 100μA LoadFig. 10 Ground Current vs Temperature with 50mA LoadFig. 11 Ground Current vs Temperature with 500mA LoadFig. 12 Ground Current vs Temperature in DropoutFig. 13 ENABLE Voltage, ON threshold, vs Input VoltageFig. 14 Output Voltage vs TemperatureFig. 15 Output Noise vs Bypass Capacitor Value IL = 10mA,10Hz - 100kHzFig. 16 Line Transient Response for 3.3V DeviceFig. 17 Load Transient Response for 3.3V DeviceAPPLICATION INFORMATIONThe SPX3819 requires an output capacitor for device stability. Its value depends upon the application circuit. In general, linear regulator stability decreases with higher output currents.In applications where the SPX3819 is sourcing less current, a lower output capacitance may be sufficient. For example, a regulator outputting only 10mA, requires approximately half the capacitance as the same regulator sourcing 150mA.Bench testing is the best method for determining the proper type and value of the capacitor since the high frequency characteristics of electrolytic capacitors vary widely, depending on type and manufacturer. A high quality 2.2μF aluminum electrolytic capacitor works in most application circuits, but the same stability often can be obtained with a1μF tantalum electrolytic.With the SPX3819 adjustable version, the minimum value of output capacitance is a function of the output voltage. The value decreases with higher output voltages, since closed loop gain is increased.T YPICAL A PPLICATIONS C IRCUITSFor fixed voltage options only. A 10nF capacitor on the BYP pin will significantly reduce output noise, but it may be left unconnected if the output noise is not a major concern. The SPX3819 start-up speed is inverselyproportional to the size of the BYP capacitor.Applications requiring a slow rampup of the output voltage should use a larger CBYP. However, if a rapid turn-on is necessary, the BYP capacitor can be omitted.The SPX3819’s internal reference is available through the BYP pin.Figure 18 represents a SPX3819 standard application circuit. The EN (enable) pin is pulled high (>2.0V) to enable the regulator. To disable the regulator, EN < 0.4V.Fig. 18: Standard Application Circuit The SPX3819 in Figure 19 illustrates a typical adjustable output voltage configuration. Two resistors (R1 and R2) set the output voltage. The output voltage is calculated using the formula:VOUT = 1.235V x [1 + R1/R2]R2 must be >10kΩand for best results, R2 should be bet ween 22kΩ and 47kΩ.Fig. 19: Typical Adjustable Output Voltage ConfigurationMECHANICAL DIMENSIONS 8-PIN SOICNMECHANICAL DIMENSIONS(CONTINUED) 8-PIN 2X3DFNRECOMMENDED LAND PATTERN AND STENCIL8-PIN 2X3DFNMECHANICAL DIMENSIONS(CONTINUED) 5-PIN SOT-23REVISION HISTORY RevisionDate Description 2.0.008/23/12 Reformat of Datasheet Addition of SPX3819R2-L and SPX3819R2-L/TR part numbers 2.0.112/02/13 Added Storage Temperature Range and Junction Temperature in ABS MAX Ratings.2.0.205/20/14 Updated package drawings and corrected DFN-8 package marking information [ECN 1423-03 6/3/14] 2.0.308/31/16 Updated logo and Ordering Information table. 2.0.407/19/18 Update to MaxLinear logo. Updated format and Ordering Information. Clarified ADJ and BYP pin. Correct y-axis on Figure 14. Updated ESD rating. 2.0.5 12/05/19 Corrected table alignment on last 5 specs of the Electrical Specifications table.C ORPORATE H EADQUARTERS :5966 La Place CourtSuite 100Carlsbad, CA 92008Tel.: +1 (760) 692-0711Fax: +1 (760) 444-8598The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Maxlinear, Inc. Maxlinear, I nc. Assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of Maxlinear, Inc.Maxlinear, Inc. Does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Maxlinear, Inc. Receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of Maxlinear, Inc. Is adequately protected under the circumstances.Maxlinear, Inc. May have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written license agreement from Maxlinear, Inc., the furnishing of this document does not give you any license to these patents, trademarks, copyrights, or other intellectual property.Maxlinear, the Maxlinear logo, and any Maxlinear trademarks, MxL, Full-Spectrum Capture, FSC, G.now, AirPHY and the Maxlinear logo are all on the products sold, are all trademarks of Maxlinear, I nc. or one of Maxlinear’s subsidiaries in the U.S.A. and other countries. All rights reserved. Other company trademarks and product names appearing herein are the property of their respe ctive owners.© 2012 - 2019 Maxlinear, Inc. All rights reserved.。

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