基于xilinx仿真 数字电子时钟的VHDL设计

VHDL语言设计数字时钟

实验性质：综合性实验级别：

开课单位：信息与通信工程学院通信工程系学时：4学时

一、实验目的：

1、学习用VHDL语言实现比较大型的电路的方法。

2、继续巩固cpld技术层次化设计方法。

二、实验器材：

计算机、Quartus II软件或xilinx ISE

三、实验内容：

设计一数字时钟，要求具有时、分、秒、计数显示功能，以24小时循环计时；具有清零，调节小时，分钟功能；具有整点报时功能。

四、实验步骤：

1、根据电路特点，用层次设计的概念，将此任务分成若干模块，规定每一模块的功能和各模块之间的接口。让几个学生分作和调试其中之一，然后再将各模块合起来联试。以培养学生之间的合作精神，同时加深层次化设计概念。

2、了解软件的元件管理深层含义，以及模块元件之间的连接概念，对于不同目录下的同一设计，如何融合。

3、模块说明：

各种进制的计数及时钟控制模块（10进制、6进制、24进制）

扫描分时显示，译码模块

各模块都用VHDL语言编写

实现电子钟原理图

各模块程序

秒模块：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity second is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

semin : in STD_LOGIC;

enmin : out STD_LOGIC;

daout : out STD_LOGIC_VECTOR (6 downto 0)); end second;

architecture Behavioral of second is

signal count:std_logic_vector(6 downto 0);

signal enmin_1,enmin_2:std_logic;

begin

daout<=count;

enmin_2<=(semin and clk);

enmin<=(enmin_1 or enmin_2);

process(clk,reset,semin)

begin

if(reset='0')then

count<="0000000";

enmin_1<='0';

elsif(clk'event and clk='1')then

if(count(3 downto 0))="1001"then

if(count<16#60#)then

if(count="1011001")then

enmin_1<='1';count<="0000000";

else

count<=count+7;

end if;

else

count<="0000000";

end if;

elsif(count<16#60#)then

count<=count+1;

enmin_1<='0';

else

count<="0000000";enmin_1<='0';

end if;

end if;

end process;

end Behavioral;

分模块：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity minute3 is

Port ( clk : in STD_LOGIC;

clks : in STD_LOGIC;

reset : in STD_LOGIC;

sethour : in STD_LOGIC;

enhour : out STD_LOGIC;

daout : out STD_LOGIC_VECTOR (6 downto 0)); end minute3;

architecture Behavioral of minute3 is

signal count:std_logic_vector(6 downto 0);

signal enhour_1,enhour_2:std_logic;

begin

daout<=count;

enhour_2<=(sethour and clks);

enhour<=(enhour_1 or enhour_2);

process(clk,reset,sethour)

begin

if(reset='0')then

count<="0000000";

enhour_1<='0';

elsif(clk'event and clk='1')then

if(count(3 downto 0))="1001"then

if(count<16#60#)then

if(count="1011001")then

enhour_1<='1';count<="0000000";

else

count<=count+7;

enhour_1<='0';

end if;

else

count<="0000000";

end if;

elsif(count<16#60#)then

count<=count+1;

enhour_1<='0' after 100 ns;

else

count<="0000000";enhour_1<='0';

end if;

end if;

end process;

end Behavioral;

时模块：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity hour is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

daut : out STD_LOGIC_VECTOR (5 downto 0)); end hour;

architecture Behavioral of hour is

signal count:std_logic_vector(5 downto 0);

begin

daut<=count;

process(clk,reset)

begin

if(reset='0')then

count<="000000";

elsif(clk'event and clk='1')then

if(count(3 downto 0)="1001")then

if(count<16#23#)then

count<=count+7;

else

count<="000000";

end if;

elsif(count<16#23#)then

count<=count+1;

else

count<="000000";

end if;

end if;

end process;

end Behavioral;

转换器7

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity s is

Port ( a : in STD_LOGIC_VECTOR (6 downto 0);

low : out STD_LOGIC_VECTOR (3 downto 0);

high : out STD_LOGIC_VECTOR (3 downto 0)); end s;

architecture Behavioral of s is

begin

low<=a(3 downto 0);

high(3)<='0';

high(2 downto 0)<=a(6 downto 4);

end Behavioral;

转换器6

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity aaa is

Port ( a : in STD_LOGIC_VECTOR (5 downto 0);

high : out STD_LOGIC_VECTOR (3 downto 0);

low : out STD_LOGIC_VECTOR (3 downto 0)); end aaa;

architecture Behavioral of aaa is

begin

low<=a(3 downto 0);

high(3 downto 2)<="00";

high(1 downto 0)<=a(5 downto 4);

end Behavioral;

显示模块：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity xianshi is

Port ( num : in STD_LOGIC_VECTOR (3 downto 0);

led : out STD_LOGIC_VECTOR (6 downto 0)); end xianshi;

architecture Behavioral of xianshi is

begin

led<="1111110"when num="0000"else

"0110000"when num="0001"else

"1101101"when num="0010"else

"1111001"when num="0011"else

"0110011"when num="0100"else

"1011011"when num="0101"else

"1011111"when num="0110"else

"1110000"when num="0111"else

"1111111"when num="1000"else

"1110011"when num="1001"else

"1110111"when num="1010"else

"0011111"when num="1011"else

"1001110"when num="1100"else

"0111101"when num="1101"else

"1001111"when num="1110"else

"0000000"when num="1111";

end Behavioral;

报时模块：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity baoshi is

Port ( enhour : in STD_LOGIC;

din,daut : in STD_LOGIC_VECTOR (6 downto 0);

y : out STD_LOGIC);

end baoshi;

architecture Behavioral of baoshi is

begin

process(enhour,din)

begin

if(enhour='1' and din="0000000" and daut(0)='0')then

y<='1';

else y<='0';

end if;

end process;

end Behavioral;

测试结果

图中xlxn_1——xlxn_6依次为时分秒的时位与个位，xlxn_36为报时模块输出

图中秒模块个位按0-9依次增加最为明显，其他位增加较为缓慢在setmin设为1时分模块的个位马上增加一位，sethour设为1时，时模块个位亦是如此。而报时模块会出现三次上升是因为报时条件（enhour='1' and din="0000000" and daut(0)='0'）所致。