程序分析

1. 1.分析下面程序，说出该程序的功能。

Entity test isgeneric(setup_time: time := 5ns);port(D:in std_logic;Q:out std_logic;clk : in std_logic);end test;architecture test of test isbeginprocess(clk)beginif clk=…1‟ and clk‟event thenassert(D‟last_event > setup_time)report “ setup violation”severity error;end if ;end test;2. 2.分析下面程序，说出该程序的功能。

library IEEE;use IEEE.STD_LOGIC_1164.all;entity s_machine isport(clk : in STD_LOGIC;rst : in STD_LOGIC;din : in STD_LOGIC;comb_output : out STD_LOGIC);end s_machine;architecture s_machine of s_machine istype states is (st0,st1,st2,st3);signal cur_state,next_state : states;beginprocess(clk,rst)beginif rst='1' thencur_state<=st0;elsif clk'event and clk='1' thencur_state<=next_state;end if;end process;process(cur_state,next_state)begincase cur_state iswhen st0=>comb_output<=…0‟;if din=…1‟ thennext_state<=st1;elsenext_state<=st0;end if;when st1=>comb_output<=…0‟;if din=…1‟ thennext_state<=st2;elsenext_state<=st0;end if;when st2=>if din=…1‟ thennext_state<=st3;comb_output<=…1‟;else next_state<=st0;comb_output<=…0‟;end if;when st3=> if state_input=…1‟ thennext_state<=st3;comb_output<=…1‟;else next_state<=st0;comb_output<=…0‟;end if;end case;end process;end s_machine;3. 3.分析下面程序，指出该程序的功能。

process(a,dr,en)beginif en='0' and dr='1' thenbout<=a;elsebout<="ZZZZZZZZ";end if;b<=bout;end process;process(a,dr,en)beginif en='0' and dr='0' thenaout<=b;elseaout<="ZZZZZZZZ";end if;a<=aout;end process;4. 4.分析下面程序，指出电路功能。

library IEEE;use IEEE.STD_LOGIC_1164.all;entity shift isport(clk : in STD_LOGIC;a: in STD_LOGIC;b : out STD_LOGIC);end shift;architecture shift of shift isbegincomponent dffport (d,clk: in std_logic;q: out std_logic);end component ;signal z:std_logic_vector(0 to 4);beginz(0)<=a;g1:for i in 0 to 3 generatedffx:dff port map (z(i),clk,z(i+1));end generate;b<=z(4);end shift;5.分析下面程序，所明该程序的功能。

library IEEE;use IEEE.STD_LOGIC_1164.all;entity chk isport(din : in STD_LOGIC;clk,clr : in STD_LOGIC;d : in STD_LOGIC_VECTOR(7 downto 0);check_out : out STD_LOGIC);end chk;architecture chk of chk issignal q: integer range 0 to 8;beginprocess(clk,clr)beginif clr='1' then q<=0;elsif clk'event and clk='1' thencase q iswhen 0=> if din=d(7) then q<=1; else q<=0; end if;when 1=> if din=d(6) then q<=2; else q<=0; end if;when 2=> if din=d(5) then q<=3; else q<=0; end if;when 3=> if din=d(4) then q<=4; else q<=0; end if;when 4=> if din=d(3) then q<=5; else q<=0; end if;when 5=> if din=d(2) then q<=6; else q<=0; end if;when 6=> if din=d(1) then q<=7; else q<=0; end if;when 7=> if din=d(0) then q<=8; else q<=0; end if;when others=>q<=0;end case;end if;end process;process(q)beginif q=8 then check_out<='1';else check_out<='0';end if;end process;end chk;6.分析下面程序，所明该程序的功能。

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity pulse isport ( clk,rst : in std_logic;d : in std_logic_vector(7 downto 0);fout : out std_logic );end pulse;architecture one of pulse issignal full : std_logic;signal cnt8 : std_logic_vector(7 downto 0);signal fout_tmp: std_logic;beginp_reg: process(clk)beginif rst='1' thencnt8<=(others=>'1');full<='0';elsif clk'event and clk = '1' thenif cnt8 = "11111111" thencnt8 <= d; --当cnt8计数计满时，输入数据d被预置给计数器cnt8 full <= '1'; --同时使溢出标志信号full输出为高电平else cnt8 <= cnt8 + 1; --否则继续作加1计数full <= '0'; --且输出溢出标志信号full为低电平end if;end if;end process p_reg ;p_div: process(full)beginif rst='1' thenfout_tmp<='0';elsif full'event and full = '1' thenfout_tmp<= not fout_tmp;--如果full为高电平，d触发器输出取反end if;end process p_div ;fout<=fout_tmp;end one;7.分析下面程序，所明该程序的功能。

library IEEE;use IEEE.STD_LOGIC_1164.all;entity nand2 isport(a : in STD_LOGIC;b : in STD_LOGIC;y : out STD_LOGIC);end nand2;architecture nand2 of nand2 isbeginprocess(a,b)variable comb:std_logic_vector(1 downto 0);comb:=a&b;case comb iswhen "00"=>y<='1';when "01"=>y<='1';when “10"=>y<='1';when “11"=>y<='0';when others=>y<='Z';end case;end process;end nand2;8.分析下面程序，说明其功能。

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4 ISPORT(input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);sel: IN STD_LOGIC_VECTOR(1 DOWNTO 0);y: out STD_LOGIC);END mux4;ARCHITECTURE rtl OF mux4 ISBEGINPROCESS(input,sel)BEGINIF sel=”00” THENy<=input(0);ELSIF sel=”01” THENy<=input(1);ELSIF sel=”10” THENy<=input(2);ELSEy<=input(3);END IF;END PROCESS;END rtl;9.分析下面程序，说明其功能。