2014-2015数字逻辑试卷

数字电路与逻辑设计期末考试样题一、TO FILL YOUR ANSWERS IN THE “( )”（1’ X 5）1. An unused CMOS NAND gate input should be tied to logic ( ) or another input.2. DAC can proportionally convert ( ) input to analog signal output.512 3. A truth table for a ( ) input, 4-output combinational logic function could be stored in a 4 EPROM.4. The RCO output of 74X163 is asserted if and only if the enable signal ( )is asserted and the counter is in state ‘1111’.5. If the signed-magnitude representation is（001101）2 for one number, then it’s 8-bit two’s complement representation is（）2.二、Single selection problems: there is only one correct answer in the following questions.（2’ X 5）1、An 8-output demultiplexer has ( ) select inputs.A. 2B. 3C. 4D. 52、For a logical function ,which representation as follows is one and only（唯一）. ( )A. logic expressionB. logic diagramC. truth tableD. timing diagram3、In general, to complete the same function, compared to a MOORE machine, the MEAL Y machine has （）。

A. more statesB. fewer statesC. more flip-flopsD. fewer flip-flops4、To design a “1000001” serial sequence generator by shift registers, at least needs a ( ) bit shift register.A. 2B. 3C. 4D.55、The following logic expressions is equal, and the hazard-free one is ( ).A. F=B’C’+AC+A’BB. F=A’C’+BC+AB’C. F=A’C’+BC+AB’+A’BD. F=B’C’+AC+A’B+BC+AB’+A’C’三. Combinational Circuit Analysis: [10]1．Find the minimal product-of-sums expression for BC BC A AB F ++=''. [4]2．Write the minterm list expression for F=W+XZ+XY . [3]F=ΣWXYZ ( )3．Complete the timing diagram of the circuit below. (Assume that the propagation delay of each gate is one Δ) [3]四.Show how to build the following logic function using one 74X138 3-8 binary decoder and some NAND gates.F = A’BD’ + A’CD’ + BCD’Write the truth table and draw the logic diagram. The logic symbol of 74X138 3-to-8 decoder is shown as follows.[10]五. A 2-bit comparator circuit receives two 2-bit numbers, P (P=PP0) and Q (Q=Q1Q0). Design a circuit that the1output F P>Q is 1 if and only if P>Q. Please write the truth table for the circuit. [5]Truth table （真值表）F P>Q六. Clocked Synchronous State Machine Design [ 20 total ]1. Design a clocked synchronous state machine with the state/output table shown below, using D flip-flops. Use two state variables,Q1 Q2, with the state assignment shown as follows. Write transition/output table and excitation/output table. [7]state/output table ： state assignment ：S X 0 1 A B ，0 D ，1 B C ，0 A ，0 C D ，0 B ，0 D A ，1 C ，0S*，Z2. An excitation/output table of a clocked synchronous state machine using D flip-flops is shown as follows. Write the excitation equations and output equation. [8]3. The excitation equations and output equitation of a clocked synchronous state machine is shown as follows. Draw the logic diagram using positive-edge-triggered （上升沿触发） J-K flip-flops . [5]excitation equations ： J 0=( A ⊕Q 1 )’ ; K 0=( A Q 1)’J1= A ⊕Q 0 ; K 1=(A ’Q 0)’output equitation : Y=((AQ 1)’(A ’Q 0))’S Q1 Q2 A 0 0 B 0 1 C 1 0 D 1 1七.Clocked Synchronous State Machine Analysis [ 15 total ]1．Analyze the circuit shown below, write the excitation equations, output equation, transition equations and construct a transition/output table. [8]2. The transition equations and output equitation of a clocked synchronous state machine is shown as follows. Complete the timing diagram for Y, assuming that the machine starts in state Q1,Q0=00. [7]transition equations：Q0*=Q0A’+Q0’AQ1*=Q1A’+Q1’Q0A+Q1Q0’Aoutput equitation: Y=Q1Q0A八．74X163 is a synchronous 4-bit binary counter with synchronous load and synchronous clear inputs. Design a modulo-14 counter, using one 74X163 and some necessary gates, with the following counting sequence: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 1, 2, …. Complete the design and draw a logic diagram. [10]Function table for a 74X163Inputs Current State Next state OutputCLR_L LD_L ENT ENP QD QC QB QA QD* QC* QB* QA* RCO0 X X X X X X X 0 0 0 0 01 0 X X X X X X D C B A 01 1 0 X X X X X QD QC QB QA 01 1 X 0 X X X X QD QC QB QA 01 1 1 1 0 0 0 0 0 0 0 1 01 1 1 1 0 0 0 1 0 0 1 0 01 1 1 1 0 0 1 0 0 0 1 1 01 1 1 1 0 0 1 1 0 1 0 0 01 1 1 1 ............. .. 01 1 1 1 1 1 1 1 0 0 0 0 1九. Analyze the circuit showed below, which contains a 74X194 4-bit shift register and a 74151 MSI multiplexer. [15]1. Write the logic expression of feedback function F.2. Write the sequence of states for the 74X194 in this circuit,3. Write the transition/output table of the circuit.（the output is Y and Z）The function table for 74X194 4-bit universal shift register is showed below,Function table for 74194:inputs Next statefunction S1S0 QA* QB* QC* QD*Hold 0 0 QA QB QC QDShift right 0 1 SRSI QA QB QCShift left 1 0 QB QC QD SLSIload 1 1 A B C D。