MSP430F42x用户手册

D Wake-Up From Standby Mode in Less Than 6 μsD Frequency-Locked Loop, FLL+D 16-Bit RISC Architecture, 125-ns Instruction Cycle TimeD Three Independent 16-bit Sigma-Delta A/D Converters With Differential PGA Inputs D 16-Bit Timer_A With Three Capture/Compare RegistersD Integrated LCD Driver for 128 Segments D Serial Communication Interface (USART),Asynchronous UART or Synchronous SPI Selectable by Software DBrownout DetectorD Bootstrap Loader in Flash Devices DFamily Members Include:− MSP430F423:8KB + 256B Flash Memory,256B RAM− MSP430F425:16KB + 256B Flash Memory,512B RAM− MSP430F427:32KB + 256B Flash Memory,1KB RAMD Available in 64-Pin Quad Flat Pack (QFP)DFor Complete Module Descriptions, Refer to the MSP430x4xx Family User’s Guide ,Literature Number SLAU056descriptionThe T exas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs.The MSP430F42x series are microcontroller configurations with three independent 16-bit sigma-delta A/D converters, each with an integrated differential programmable gain amplifier input stage. Also included is a built-in 16-bit timer, 128 LCD segment drive capability, hardware multiplier, and 14 I/O pins.Typical applications include high resolution applications such as handheld metering equipment, weigh scales,and energy meters.This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection.Copyright © 2004−2007 T exas Instruments IncorporatedPRODUCTION DATA nformat on s current as of publ cat on date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.AVAILABLE OPTIONSPACKAGED DEVICEST APLASTIC 64-PIN QFP(PM)−40°C to 85°CMSP430F423IPM MSP430F425IPM MSP430F427IPMpin designation{P1.5/TACLK/ACLK/S28P 2.3/S V S I N P 2.4/U T X D 0P 2.5/U R X D 0R S T /N M I T C K T M S T D I /T C L K T D O /T D I P 1.0/T A 0P 1.1/T A 0/M C L K P 1.2/T A 1/S 31P 1.3/S V S O U T /S 30P 1.4/S 29S 5S 6S 7S 8S 9S 10S 11S 12S 13S 14S 15S 16S 17S 18S 19S 20P1.6/SIMO0/S27P1.7/SOMI0/S26P2.0/TA2/S25P2.1/UCLK0/S24R33R23R13R03COM3COM2COM1COM0S23S21S22A0.0+A0.0−A1.0+A1.0−A2.0+A2.0−XIN XOUTP2.2/STE0S0S1S2S4S3V REFA V C CDV CC A V S SD V S S†Open connection recommended for all unused analog inputs.functional block diagramDV DV AV AVRST/NMIMSP430F42x Terminal FunctionsTERMINALPNI/O DESCRIPTIONNAME NO.DV CC1Digital supply voltage, positive terminal.A0.0+2I Internal connection to SD16 Channel 0, input 0 +. (see Note 1)A0.0−3I Internal connection to SD16 Channel 0, input 0 −. (see Note 1)A1.0+4I Internal connection to SD16 Channel 1, input 0 +. (see Note 1)A1.0−5I Internal connection to SD16 Channel 1, input 0 −. (see Note 1)A2.0+6I Internal connection to SD16 Channel 2, input 0 +. (see Note 1)A2.0−7I Internal connection to SD16 Channel 2, input 0 −. (see Note 1)XIN8I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.XOUT9O Output terminal of crystal oscillator XT1V REF10I/O Input for an external reference voltage / internal reference voltage output (can be used as mid-voltage) P2.2/STE011I/O General-purpose digital I/O / slave transmit enable—USART0/SPI modeS012O LCD segment output 0S113O LCD segment output 1S214O LCD segment output 2S315O LCD segment output 3S416O LCD segment output 4S517O LCD segment output 5S618O LCD segment output 6S719O LCD segment output 7S820O LCD segment output 8S921O LCD segment output 9S1022O LCD segment output 10S1123O LCD segment output 11S1224O LCD segment output 12S1325O LCD segment output 13S1426O LCD segment output 14S1527O LCD segment output 15S1628O LCD segment output 16S1729O LCD segment output 17S1830O LCD segment output 18S1931O LCD segment output 19S2032O LCD segment output 20S2133O LCD segment output 21S2234O LCD segment output 22S2335O LCD segment output 23COM036O Common output, COM0−3 are used for LCD backplanes.COM137O Common output, COM0−3 are used for LCD backplanes.COM238O Common output, COM0−3 are used for LCD backplanes.COM339O Common output, COM0−3 are used for LCD backplanes.R0340I Input port of fourth positive (lowest) analog LCD level (V5)NOTE 1:Open connection recommended for all unused analog inputs.MSP430F42x Terminal Functions (Continued) TERMINALPN I/O DESCRIPTION NAME NO.R1341I Input port of third most positive analog LCD level (V4 or V3)R2342I Input port of second most positive analog LCD level (V2)R3343O Output port of most positive analog LCD level (V1)P2.1/UCLK0/S2444I/O General-purpose digital I/O / external clock input-USART0/UART or SPI mode, clock output—USART0/SPI mode / LCD segment output 24 (See Note 1)P2.0/TA2/S2545I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output 25 (See Note 1)P1.7/SOMI0/S2646I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26 (See Note 1)P1.6/SIMO0/S2747I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27 (See Note 1)P1.5/TACLK/ ACLK/S2848I/OGeneral-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1,2, 4, or 8) / LCD segment output 28 (See Note 1)P1.4/S2949I/O General-purpose digital I/O / LCD segment output 29 (See Note 1)P1.3/SVSOUT/S3050I/O General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)P1.2/TA1/S3151I/O General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment output 31 (See Note 1)P1.1/TA0/MCLK52I/O General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output. Note: TA0 is only an input on this pin / BSL receiveP1.0/TA053I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit TDO/TDI54I/O Test data output port. TDO/TDI data output or programming data input terminal.TDI/TCLK55I Test data input or test clock input. The device protection fuse is connected to TDI.TMS56I Test mode select. TMS is used as an input port for device programming and test.TCK57I Test clock. TCK is the clock input port for device programming and test.RST/NMI58I Reset input or nonmaskable interrupt input portP2.5/URXD059I/O General-purpose digital I/O / receive data in—USART0/UART modeP2.4/UTXD060I/O General-purpose digital I/O / transmit data out—USART0/UART modeP2.3/SVSIN61I/O General-purpose digital I/O / Analog input to brownout, supply voltage supervisorAV SS62Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry.DV SS63Digital supply voltage, negative terminalAV CC64Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry; must not power up prior to DV CC.NOTE 1:LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.General-Purpose Register Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R12R13General-Purpose Register General-Purpose Register R6R7General-Purpose Register General-Purpose Register R8R9General-Purpose Register General-Purpose Register R10R11General-Purpose Register General-Purpose RegisterR14R15short-form descriptionCPUThe MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions,are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register,and constant generator respectively. The remaining registers are general-purpose registers.Peripherals are connected to the CPU using data,address, and control buses, and can be handled with all instructions.instruction setThe instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.Table 1. Instruction Word FormatsDual operands, source-destination e.g. ADD R4,R5R4 + R5 −−−> R5Single operands, destination only e.g. CALL R8PC −−>(TOS), R8−−> PC Relative jump, un/conditionale.g. JNEJump-on-equal bit = 0Table 2. Address Mode DescriptionsADDRESS MODES DSYNTAX EXAMPLE OPERATION Register D D MOV Rs,Rd MOV R10,R11R10 −−> R11IndexedD D MOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5)−−> M(6+R6)Symbolic (PC relative)D D MOV EDE,TONI M(EDE) −−> M(TONI)Absolute D DMOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)Indirect D MOV @Rn,Y(Rm)MOV @R10,Tab(R6)M(R10) −−> M(Tab+R6)Indirect autoincrement D MOV @Rn+,Rm MOV @R10+,R11M(R10) −−> R11R10 + 2−−> R10ImmediateDMOV #X,TONIMOV #45,TONI #45 −−> M(TONI)NOTE:S = source D = destinationoperating modesThe MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.The following six operating modes can be configured by software:D Active mode (AM)−All clocks are activeD Low-power mode 0 (LPM0)−CPU is disabledACLK and SMCLK remain active, MCLK is available to modulesFLL+ loop control remains activeD Low-power mode 1 (LPM1)−CPU is disabledACLK and SMCLK remain active, MCLK is available to modulesFLL+ loop control is disabledD Low-power mode 2 (LPM2)−CPU is disabledMCLK, FLL+ loop control, and DCOCLK are disabledDCO’s dc-generator remains enabledACLK remains activeD Low-power mode 3 (LPM3)−CPU is disabledMCLK, FLL+ loop control, and DCOCLK are disabledDCO’s dc-generator is disabledACLK remains activeD Low-power mode 4 (LPM4)−CPU is disabledACLK is disabledMCLK, FLL+ loop control, and DCOCLK are disabledDCO’s dc-generator is disabledCrystal oscillator is stoppedinterrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h.The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITYPower-upExternal ResetWatchdogFlash memoryPC Out-of-Range (see Note 4)WDTIFGKEYV(see Note 1)Reset0FFFEh15, highestNMIOscillator FaultFlash memory access violationNMIIFG (see Notes 1 and 3)OFIFG (see Notes 1 and 3)ACCVIFG (see Notes 1 and 3)(Non)maskable(Non)maskable(Non)maskable0FFFCh140FFFAh13SD16SD16CCTLx SD16OVIFG,SD16CCTLx SD16IFG(see Notes 1 and 2)Maskable0FFF8h120FFF6h11Watchdog Timer WDTIFG Maskable0FFF4h10 USART0 Receive URXIFG0Maskable0FFF2h9 USART0 Transmit UTXIFG0Maskable0FFF0h80FFEEh7 Timer_A3TACCR0 CCIFG (see Note 2)Maskable0FFECh6Timer_A3TACCR1 and TACCR2CCIFGs, and TACTL TAIFG(see Notes 1 and 2)Maskable0FFEAh5I/O port P1 (eight flags)P1IFG.0 to P1IFG.7(see Notes 1 and 2)Maskable0FFE8h40FFE6h30FFE4h2I/O port P2 (eight flags)P2IFG.0 to P2IFG.7(see Notes 1 and 2)Maskable0FFE2h1Basic Timer1BTIFG Maskable0FFE0h0, lowest NOTES: 1.Multiple source flags2.Interrupt flags are located in the module.3.(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or fromwithin unused address ranges (from 0600h to 0BFFh).special function registersMost interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.interrupt enable 1 and 2Address 0hWDTIE:Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode.OFIE:Oscillator-fault-interrupt enable NMIIE:Nonmaskable-interrupt enable ACCVIE:Flash access violation interrupt enableURXIE0:USART0: UART and SPI receive-interrupt enable UTXIE0:USART0: UART and SPI transmit-interrupt enableAddress 1hBTIE:Basic Timer1 interrupt enableinterrupt flag register 1 and 2Address 02hWDTIFG:Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V CC power up or a reset condition at the RST/NMI pin in reset mode.OFIFG:Flag set on oscillator fault NMIIFG:Set via RST/NMI pinURXIFG0:USART0: UART and SPI receive flag UTXIFG0:USART0: UART and SPI transmit flagAddress 3hBTIFG:Basic Timer1 interrupt flagmodule enable registers 1 and 2rw–0rw–0Address 04hURXE0:USART0: UART mode receive enable UTXE0:USART0: UART mode transmit enableUSPIE0:USART0: SPI mode transmit and receive enableAddress 05hLegend:rw−0,1:Bit Can Be Read and Written. It Is Reset or Set by PUC.Bit Can Be Read and Written. It Is Reset or Set by POR.SFR Bit Not Present in Device.memory organizationMSP430F423MSP430F425MSP430F427MemoryInterrupt vector Code memory Size Flash Flash 8KB0FFFFh − 0FFE0h 0FFFFh − 0E000h 16KB0FFFFh − 0FFE0h 0FFFFh − 0C000h 32KB0FFFFh − 0FFE0h 0FFFFh − 08000h Information memory Size 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h Boot memory Size 1kB0FFFh − 0C00h 1kB0FFFh − 0C00h 1kB0FFFh − 0C00h RAM Size 256 Byte 02FFh − 0200h 512 Byte 03FFh − 0200h 1KB05FFh − 0200h Peripherals16-bit 8-bit 8-bit SFR01FFh − 0100h 0FFh − 010h 0Fh − 00h01FFh − 0100h 0FFh − 010h 0Fh − 00h01FFh − 0100h 0FFh − 010h 0Fh − 00hbootstrap loader (BSL)The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430Bootstrap Loader , Literature Number SLAA089.BSL Function PM Package PinsData Transmit 53 - P1.0Data Receive52 - P1.1flash memoryThe flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:D Flash memory has n segments of main memory and two segments of information memory (A and B) of128 bytes each. Each segment in main memory is 512 bytes in size.D Segments 0 to n may be erased in one step, or each segment may be individually erased.D Segments A and B can be erased individually, or as a group with segments 0−n.Segments A and B are also called information memory.D New devices may have some bytes programmed in the information memory (needed for test duringmanufacturing). The user should perform an erase of the information memory prior to the first use.32KB Main MemoryInformation Memory0FFFFh0FA00h 0FE00h 0FDFFh0FC00h 0FBFFh0F9FFh08400h 083FFh 08200h 081FFh01000h010FFh08000h 01080h 0107Fh16KB0FFFFh0FA00h 0FE00h 0FDFFh 0FC00h 0FBFFh 0F9FFh0C400h 0C3FFh 0C200h 0C1FFh 01000h010FFh 0C000h 01080h 0107Fh 8KB0FFFFh 0FA00h 0FE00h 0FDFFh 0FC00h 0FBFFh 0F9FFh0E400h 0E3FFh 0E200h 0E1FFh 01000h010FFh 0E000h 01080h 0107FhperipheralsPeripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, TI literature number SLAU056.oscillator and system clockThe clock system in the MSP430F42x family of devices is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction witha digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals:D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.D Main clock (MCLK), the system clock used by the CPU.D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.brownout, supply voltage supervisorThe brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).The CPU begins code execution after the brownout circuit releases the device reset. However, V CC may not have ramped to V CC(min) at that time. The user must insure the default FLL+ settings are not changed until V CC reaches V CC(min). If desired, the SVS circuit can be used to determine when V CC reaches V CC(min).digital I/OThere are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external pins):D All individual I/O bits are independently programmable.D Any combination of input, output, and interrupt conditions is possible.D Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of P2.D Read/write access to port-control registers is supported by all instructions.NOTE:Six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits for portP2 are implemented.Basic Timer1The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.LCD driveThe LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.WDT+ watchdog timerThe primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.timer_A3Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.Timer_A3 Signal ConnectionsInput Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number48 - P1.5TACLK TACLKACLK ACLKTimer NASMCLK SMCLK48 - P1.5TACLK INCLK53 - P1.0TA0CCI0A53 - P1.052 - P1.1TA0CCI0BCCR0TA0DV SS GNDDV CC V CC51 - P1.2TA1CCI1A51 - P1.251 - P1.2TA1CCI1BCCR1TA1DV SS GNDDV CC V CC45 - P2.0TA2CCI2A45 - P2.0ACLK (internal)CCI2BCCR2TA2DV SS GNDDV CC V CCUSART0The MSP430F42x devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.hardware multiplierThe multiplication operation is supported by a dedicated peripheral module. The module performs 1616, 168, 816, and 88 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.SD16The SD16 module integrates three independent 16-bit sigma-delta A/D converters, internal temperature sensor and built-in voltage reference. Each channel is designed with a fully differential analog input pair and programmable gain amplifier input stage.peripheral file mapPERIPHERALS WITH WORD ACCESSWatchdog Watchdog Timer control WDTCTL0120hTimer_A3Timer_A interrupt vector TAIV012Eh _Timer_A control TACTL0160hCapture/compare control 0TACCTL00162hCapture/compare control 1TACCTL10164hCapture/compare control 2TACCTL20166hTimer_A register TAR0170hCapture/compare register 0TACCR00172hCapture/compare register 1TACCR10174hCapture/compare register 2TACCR20176h Hardware Multiplier Sum extend SUMEXT013EhpResult high word RESHI013ChResult low word RESLO013AhSecond operand OP20138hMultiply signed + accumulate/operand1MACS0136hMultiply + accumulate/operand1MAC0134hMultiply signed/operand1MPYS0132hMultiply unsigned/operand1MPY0130h Flash Flash control 3FCTL3012ChFlash control 2FCTL2012AhFlash control 1FCTL10128h SD16General Control SD16CTL0100h(see also: Peripherals with Byte Access)Channel 0 Control SD16CCTL00102hwith Byte Access)Channel 1 Control SD16CCTL10104hChannel 2 Control SD16CCTL20106hReserved0108hReserved010AhReserved010ChReserved010EhInterrupt vector word register SD16IV0110hChannel 0 conversion memory SD16MEM00112hChannel 1 conversion memory SD16MEM10114hChannel 2 conversion memory SD16MEM20116hReserved0118hReserved011AhReserved011ChReserved011Ehperipheral file map (continued)PERIPHERALS WITH BYTE ACCESSSD16Channel 0 Input Control SD16INCTL00B0h(see also: Peripherals with Word Access)Channel 1 Input Control SD16INCTL10B1hwith Word Access)Channel 2 Input Control SD16INCTL20B2hReserved0B3hReserved0B4hReserved0B5hReserved0B6hReserved0B7hChannel 0 preload SD16PRE00B8hChannel 1 preload SD16PRE10B9hChannel 2 preload SD16PRE20BAhReserved0BBhReserved0BChReserved0BDhReserved0BEhReserved0BFh LCD LCD memory 20LCDM200A4h:::LCD memory 16LCDM160A0hLCD memory 15LCDM1509Fh:::LCD memory 1LCDM1091hLCD control and mode LCDCTL090h USART0Transmit buffer U0TXBUF077hReceive buffer U0RXBUF076hBaud rate U0BR1075hBaud rate U0BR0074hModulation control U0MCTL073hReceive control U0RCTL072hTransmit control U0TCTL071hUSART control U0CTL070h Brownout, SVS SVS control register SVSCTL056h FLL+ Clock FLL+ Control1FLL_CTL1054hFLL+ Control0FLL_CTL0053hSystem clock frequency control SCFQCTL052hSystem clock frequency integrator SCFI1051hSystem clock frequency integrator SCFI0050h Basic Timer1BT counter2BTCNT2047hBT counter1BTCNT1046hBT control BTCTL040hperipheral file map (continued)PERIPHERALS WITH BYTE ACCESS (CONTINUED)Port P2Port P2 selection P2SEL02EhPort P2 interrupt enable P2IE02DhPort P2 interrupt-edge select P2IES02ChPort P2 interrupt flag P2IFG02BhPort P2 direction P2DIR02AhPort P2 output P2OUT029hPort P2 input P2IN028h Port P1Port P1 selection P1SEL026hPort P1 interrupt enable P1IE025hPort P1 interrupt-edge select P1IES024hPort P1 interrupt flag P1IFG023hPort P1 direction P1DIR022hPort P1 output P1OUT021hPort P1 input P1IN020h pSpecial Functions SFR module enable 2ME2005hSFR module enable 1ME1004hSFR interrupt flag 2IFG2003hSFR interrupt flag 1IFG1002hSFR interrupt enable2IE2001hSFR interrupt enable1IE1000habsolute maximum ratings †Voltage applied at V CC to V SS −0.3 V to + 4.1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage applied to any pin (see Note 1) −0.3 V to V CC + 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode current at any device terminal . ±2 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature (unprogrammed device) −55°C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature (programmed device) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1:All voltages referenced to V SS . The JTAG fuse-blow voltage, V FB , is allowed to exceed the absolute maximum rating. The voltage isapplied to the TDI/TCLK pin when blowing the JTAG fuse.recommended operating conditionsPARAMETERMIN NOMMAX UNITS Supply voltage during program execution; SD16 disabled. V CC (AV CC = DV CC = V CC ) (see Note 1)MSP430F42x 1.8 3.6V Supply voltage during program execution; SD16 disabled, SVS enabled, and PORON = 1. V CC (AV CC = DV CC = V CC ) (see Note 1 and Note 2)MSP430F42x 2.0 3.6V Supply voltage during program execution; SD16 enabled orduring programming of flash memory. V CC (AV CC = DV CC = V CC )MSP430F42x2.73.6V Supply voltage, V SS (AV SS = DV SS = V SS )00V Operating free-air temperature range, TAMSP430F42x −4085°C LF selected, XTS_FLL=0Watch crystal 32768Hz XT1 selected, XTS_FLL=1Ceramic resonator 4508000kHz LFXT1 crystal frequency, f (LFXT1) (see Note 3)XT1 selected, XTS_FLL=1Crystal 10008000kHz Processor frequency (signal MCLK)f V CC = 1.8 V DC 4.15Processor frequency (signal MCLK), f(System)V CC = 3.6 VDC8MHzNOTES: 1.It is recommended to power AV CC and DV CC from the same source. A maximum difference of 0.3 V between AV CC and DV CC canbe tolerated during power up and operation.2.The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.3.The LFXT1 oscillator in LF-mode requires a watch crystal.f (MHz)1.8 V 3.6 V2.7 V 3 V 4.15 MHz8 MHzV CC − Supply Voltage − Vf S y s t e m − M a x i m u m P r o c e s s o r F r e q u e n c y − M H z6 MHzFigure 1. Frequency vs Supply Voltage。