MSP430F438_439 Mixed Signal Microcontroller

D Wake-Up From Standby Mode in Less Than 6µsD 16-Bit RISC Architecture,125-ns Instruction Cycle Time D Single-Channel Internal DMAD 12-Bit A/D Converter With Internal Reference,Sample-and-Hold and Autoscan FeatureD 16-Bit Timer_A With Three Capture/Compare Registers D 16-Bit Timer_B With ThreeCapture/Compare-With-Shadow Registers D On-Chip ComparatorDSerial Communication Interface (USART),Select Asynchronous UART or Synchronous SPI by SoftwareNo External Programming Voltage Needed Programmable Code Protection by Security FuseD Integrated LCD Driver for Up to 128SegmentsDFamily Members Include:--MSP430F438:48KB+256B Flash Memory,2KB RAM--MSP430F439:60KB+256B Flash Memory,2KB RAMDFor Complete Module Descriptions,See The MSP430x4xx Family User’s Guide ,Literature Number SLAU056descriptionThe Texas Instruments MSP430family of ultralow power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications.The architecture,combined with five low-power modes,is optimized to achieve extended battery life in portable measurement applications.The device features a powerful 16-bit RISC CPU,16-bit registers,and constant generators that contribute to maximum code efficiency.The digitally controlled oscillator (DCO)allows wake-up from low-power modes to active mode in less than 6µs.The MSP430F43x series are microcontroller configurations with two 16-bit timers,a high performance 12-bit A/D converter,one universal synchronous/asynchronous communication interface (USART),DMA,48I/O pins,and a liquid crystal display (LCD)driver.Typical applications for this device include analog and digital sensor systems,digital motor control,remote controls,thermostats,digital timers,hand-held meters,etc.This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.These devices have limited built-in ESD protection.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.AVAILABLE OPTIONSPACKAGED DEVICEST APLASTIC 80-PIN QFP(PN)--40°C to 85°CMSP430F438IPN MSP430F439IPN†For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI web site at .‡Package drawings,thermal data,and symbolization are available at /packaging.pin designation,MSP430F438IPN,MSP430F439IPNP1.7/CA1P2.0/TA2P2.1/TB0P2.2/TB1P2.3/TB2P2.4/UTXD0P2.5/URXD0DV SS2DV CC2P5.7/R33P5.6/R23P5.5/R13R03P5.4/COM3P5.3/COM2P5.2/COM1COM0P3.0/STE0/S31P3.1/SIMO0/S30P3.2/SOMI0/S29DV CC1P6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7/SVSINV REF+XIN XOUT Ve REF+V REF--/Ve REF--P5.1/S0/A12P5.0/S1/A13P4.7/S2/A14P4.6/S3/A15P4.5/S4P4.4/S5P4.3/S6P4.2/S7P4.1/S8PN PACKAGE (TOP VIEW)T D O /T D I P 6.1/A 1P 6.0/A 0R S T /N M I T C K T M S P 2.6/C A O U T /S 19S 21S 15S 16S 17P 4.0/S 9X T 2O U T S 22S 23P 3.7/S 24P 3.6/S 25/D M A E 0P 1.0/T A 0P 1.1/T A 0/M C L K P 1.2/T A 1P 1.3/T B O U T H /S V S O U TP 3.5/S 26P 3.4/S 27P 1.4/T B C L K /S M C L K P 1.5/T A C L K /A C L K T D I /T C L K X T 2I N P 1.6/C A 0S 10S 20P 3.3/U C L K 0/S 28S 11S 12S 13S 14P 2.7/A D C 12C L K /S 18P 6.2/A 2A V C CV S S 1A V S Sfunctional block diagramDV DV AV AVRST/NMITerminal FunctionsTERMINALPNI/ONAME NO.DESCRIPTIONDV CC11Digital supply voltage,positive terminal.P6.3/A32I/O General-purpose digital I/O/analog input a3—12-bit ADCP6.4/A43I/O General-purpose digital I/O/analog input a4—12-bit ADCP6.5/A54I/O General-purpose digital I/O/analog input a5—12-bit ADCP6.6/A65I/O General-purpose digital I/O/analog input a6—12-bit ADCP6.7/A7/SVSIN6I/O General-purpose digital I/O/analog input a7—12-bit ADC/analog input to supply voltagesupervisorV REF+7O Positive output terminal of the reference voltage in the ADCXIN8I Input terminal of crystal oscillator XT1XOUT9O Output terminal of crystal oscillator XT1Ve REF+10I/O Positive input terminal for an external reference voltage to the12-bit ADCV REF--/Ve REF--11I Negative terminal for the12-bit ADC reference voltage for both sources,the internal reference voltage or an external applied reference voltage to the12-bit ADC.P5.1/S0/A1212I/O General-purpose digital I/O/LCD segment output0/analog input a12—12-bit ADC P5.0/S1/A1313I/O General-purpose digital I/O/LCD segment output1/analog input a13—12-bit ADC P4.7/S2/A1414I/O General-purpose digital I/O/LCD segment output2/analog input a14—12-bit ADC P4.6/S3/A1515I/O General-purpose digital I/O/LCD segment output3/analog input a15—12-bit ADC P4.5/S416I/O General-purpose digital I/O/LCD segment output4P4.4/S517I/O General-purpose digital I/O/LCD segment output5P4.3/S618I/O General-purpose digital I/O/LCD segment output6P4.2/S719I/O General-purpose digital I/O/LCD segment output7P4.1/S820I/O General-purpose digital I/O/LCD segment output8P4.0/S921I/O General-purpose digital I/O/LCD segment output9S1022O LCD segment output10S1123O LCD segment output11S1224O LCD segment output12S1325O LCD segment output13S1426O LCD segment output14S1527O LCD segment output15S1628O LCD segment output16S1729O LCD segment output17P2.7/ADC12CLK/S1830I/O General-purpose digital I/O/conversion clock—12-bit ADC/LCD segment output18 P2.6/CAOUT/S1931I/O General-purpose digital I/O/Comparator_A output/LCD segment output19S2032O LCD segment output20S2133O LCD segment output21S2234O LCD segment output22S2335O LCD segment output23P3.7/S2436I/O General-purpose digital I/O/LCD segment output24P3.6/S25/DMAE037I/O General-purpose digital I/O/LCD segment output25/DMA Channel0external trigger P3.5/S2638I/O General-purpose digital I/O/LCD segment output26P3.4/S2739I/O General-purpose digital I/O/LCD segment output27Terminal Functions(Continued) TERMINALPNNAME NO.I/ODESCRIPTIONP3.3/UCLK0/S2840I/O General-purpose digital I/O/ext.clock i/p—USART0/UART or SPI mode,clock o/p—USART0/SPI mode /LCD segment output28P3.2/SOMI0/S2941I/O General-purpose digital I/O/slave out/master in of USART0/SPI mode/LCD segment output29 P3.1/SIMO0/S3042I/O General-purpose digital I/O/slave out/master out of USART0/SPI mode/LCD segment output30 P3.0/STE0/S3143I/O General-purpose digital I/O/slave transmit enable-USART0/SPI mode/LCD segment output31 COM044O Common output,COM0--3are used for LCD backplanes.P5.2/COM145I/O General-purpose digital I/O/common output,COM0--3are used for LCD backplanes.P5.3/COM246I/O General-purpose digital I/O/common output,COM0--3are used for LCD backplanes.P5.4/COM347I/O General-purpose digital I/O/common output,COM0--3are used for LCD backplanes.R0348I Input port of fourth positive(lowest)analog LCD level(V5)P5.5/R1349I/O General-purpose digital I/O/input port of third most positive analog LCD level(V4or V3)P5.6/R2350I/O General-purpose digital I/O/input port of second most positive analog LCD level(V2)P5.7/R3351I/O General-purpose digital I/O/output port of most positive analog LCD level(V1)DV CC252Digital supply voltage,positive terminal.DV SS253Digital supply voltage,negative terminal.P2.5/URXD054I/O General-purpose digital I/O/receive data in—USART0/UART modeP2.4/UTXD055I/O General-purpose digital I/O/transmit data out—USART0/UART modeP2.3/TB256I/O General-purpose digital I/O/Timer_B3CCR2. Capture:CCI2A/CCI2B input,compare:Out2outputP2.2/TB157I/O General-purpose digital I/O/Timer_B3CCR1. Capture:CCI1A/CCI1B input,compare:Out1outputP2.1/TB058I/O General-purpose digital I/O/Timer_B3CCR0. Capture:CCI0A/CCI0B input,compare:Out0outputP2.0/TA259I/O General-purpose digital I/O/Timer_A Capture:CCI2A input,compare:Out2outputP1.7/CA1360I/O General-purpose digital I/O/Comparator_A input P1.6/CA061I/O General-purpose digital I/O/Comparator_A inputP1.5/TACLK/ACLK62I/O General-purpose digital I/O/Timer_A,clock signal TACLK input/ ACLK output(divided by1,2,4,or8)P1.4/TBCLK/SMCLK63I/O General-purpose digital I/O/input clock TBCLK—Timer_B3/submain system clock SMCLK outputP1.3/TBOUTH/SVSOUT64I/O General-purpose digital I/O/switch all PWM digital output ports to high impedance—Timer_B3TB0to TB2 /SVS:output of SVS comparatorP1.2/TA165I/O General-purpose digital I/O/Timer_A,Capture:CCI1A,compare:Out1outputP1.1/TA0/MCLK66I/O General-purpose digital I/O/Timer_A.Capture:CCI0B/MCLK output.Note:TA0is only an input on this pin/BSL receiveP1.0/TA067I/O General-purpose digital I/O/Timer_A.Capture:CCI0A input,compare:Out0output/BSL transmit XT2OUT68O Output terminal of crystal oscillator XT2XT2IN69I Input port for crystal oscillator XT2.Only standard crystals can be connected.TDO/TDI70I/O Test data output port.TDO/TDI data output or programming data input terminalTDI/TCLK71I Test data input or test clock input.The device protection fuse is connected to TDI/TCLK.TMS72I Test mode select.TMS is used as an input port for device programming and test.TCK73I Test clock.TCK is the clock input port for device programming and test.Terminal Functions(Continued)TERMINALPNI/ONAME NO.DESCRIPTION RST/NMI74I Reset or nonmaskable interrupt inputP6.0/A075I/O General-purpose digital I/O/analog input a0--12-bit ADC P6.1/A176I/O General-purpose digital I/O/analog input a1--12-bit ADC P6.2/A277I/O General-purpose digital I/O/analog input a2--12-bit ADCAV SS78Analog supply voltage,negative terminal.Supplies SVS,brownout,oscillator,comparator_A,port1, and LCD resistive divider circuitry.DV SS179Digital supply voltage,negative terminal.AV CC80Analog supply voltage,positive terminal.Supplies SVS,brownout,oscillator,comparator_A,port1, and LCD resistive divider circuitry;must not power up prior to DV CC1/DV CC2.General-Purpose Register Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R12R13General-Purpose Register General-Purpose Register R6R7General-Purpose Register General-Purpose Register R8R9General-Purpose Register General-Purpose Register R10R11General-Purpose Register General-Purpose RegisterR14R15short-form descriptionCPUThe MSP430CPU has a 16-bit RISC architecture that is highly transparent to the application.All operations,other than program-flow instructions,are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.The CPU is integrated with 16registers that provide reduced instruction execution time.The register-to-register operation execution time is one cycle of the CPU clock.Four of the registers,R0to R3,are dedicated as program counter,stack pointer,status register,and constant generator respectively.The remaining registers are general-purpose registers.Peripherals are connected to the CPU using data,address,and control buses,and can be handled with all instructions.instruction setThe instruction set consists of 51instructions with three formats and seven address modes.Each instruction can operate on word and byte data.Table 1shows examples of the three types of instruction formats;Table 2shows the address modes.Table 1.Instruction Word FormatsDual operands,source-destination e.g.ADD R4,R5R4+R5------>R5Single operands,destination only e.g.CALL R8PC ---->(TOS),R8---->PC Relative jump,un/conditionale.g.JNEJump-on-equal bit =0Table 2.Address Mode DescriptionsADDRESS MODES D SYNTAX EXAMPLE OPERATION Register F F MOV Rs,Rd MOV R10,R11R10—>R11IndexedF F MOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5)—>M(6+R6)Symbolic (PC relative)F F MOV EDE,TONI M(EDE)—>M(TONI)Absolute F F MOV &MEM,&TCDAT M(MEM)—>M(TCDAT)Indirect F MOV @Rn,Y(Rm)MOV @R10,Tab(R6)M(R10)—>M(Tab+R6)Indirect autoincrement F MOV @Rn+,Rm MOV @R10+,R11M(R10)—>R11R10+2—>R10ImmediateFMOV #X,TONIMOV #45,TONI #45—>M(TONI)NOTE:S =sourceD =destinationoperating modesThe MSP430has one active mode and five software selectable low-power modes of operation.An interrupt event can wake up the device from any of the five low-power modes,service the request,and restore back to the low-power mode on return from the interrupt program.The following six operating modes can be configured by software:D Active mode(AM)--All clocks are activeD Low-power mode0(LPM0)--CPU is disabled--ACLK and SMCLK remain active,MCLK is disabled--FLL+loop control remains activeD Low-power mode1(LPM1)--CPU is disabled--FLL+loop control is disabled--ACLK and SMCLK remain active,MCLK is disabledD Low-power mode2(LPM2)--CPU is disabled--MCLK,FLL+loop control,and DCOCLK are disabled--DCO’s dc-generator remains enabled--ACLK remains activeD Low-power mode3(LPM3)--CPU is disabled--MCLK,FLL+loop control,and DCOCLK are disabled--DCO’s dc-generator is disabled--ACLK remains activeD Low-power mode4(LPM4)--CPU is disabled--ACLK is disabled--MCLK,FLL+loop control,and DCOCLK are disabled--DCO’s dc-generator is disabled--Crystal oscillator is stoppedinterrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range0FFFFh to0FFE0h.The vector contains the16-bit address of the appropriate interrupt-handler instruction sequence.INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPTWORDADDRESS PRIORITYPower-Up External Reset Watchdog Flash MemoryWDTIFGKEYV(see Note1)Reset0FFFEh15,highestNMIOscillator FaultFlash Memory Access ViolationNMIIFG(see Notes1and3)OFIFG(see Notes1and3)ACCVIFG(see Notes1and3)(Non)maskable(Non)maskable(Non)maskable0FFFCh14Timer_B3TBCCR0CCIFG0(see Note2)Maskable0FFFAh13Timer_B3TBCCR1CCIFG1,TBCCR2CCIFG2,TBIFG(see Notes1and2)Maskable0FFF8h12Comparator_A CAIFG Maskable0FFF6h11 Watchdog Timer WDTIFG Maskable0FFF4h10 USART0Receive URXIFG0Maskable0FFF2h9 USART0Transmit UTXIFG0Maskable0FFF0h8 ADC12ADC12IFG(see Notes1and2)Maskable0FFEEh7 Timer_A3TACCR0CCIFG0(see Note2)Maskable0FFECh6Timer_A3TACCR1CCIFG1and TACCR2CCIFG2,TAIFG(see Notes1and2)Maskable0FFEAh5I/O Port P1(Eight Flags)P1IFG.0to P1IFG.7(see Notes1and2)Maskable0FFE8h4 DMA DMA0IFG(see Notes1and2)Maskable0FFE6h30FFE4h2 I/O Port P2(Eight Flags)P2IFG.0to P2IFG.7(see Notes1and2)Maskable0FFE2h1 Basic Timer1BTIFG Maskable0FFE0h0,lowest NOTES: 1.Multiple source flags2.Interrupt flags are located in the module.3.(Non)maskable:the individual interrupt-enable bit can disable an interrupt event,but the general-interrupt enable cannot disableit.special function registersThe MSP430special function registers(SFR)are located in the lowest address space and are organized as byte mode registers.SFRs should be accessed with byte instructions.interrupt enable 1and2Address 0hWDTIE:Watchdog timer interrupt enable.Inactive if watchdog mode is selected.Active if watchdog timer is configured as a general-purpose timer.OFIE:Oscillator fault interrupt enable NMIIE:Nonmaskable interrupt enable ACCVIE:Flash access violation interrupt enableURXIE0:USART0:UART and SPI receive-interrupt enable UTXIE0:USART0:UART and SPI transmit-interruptenableAddress 01hrw–0BTIE:Basic timer interrupt enableinterrupt flag register 1and2Address 02hWDTIFG:Set on watchdog timer overflow (in watchdog mode)or security key violation Reset on V CC power-on or a reset condition at the RST/NMI pin in reset mode OFIFG:Flag set on oscillator fault NMIIFG:Set via RST/NMI pinURXIFG0:USART0:UART and SPI receive flag UTXIFG0:USART0:UART and SPI transmitflagAddress 03hrw–0BTIFG:Basic timer flagmodule enable registers 1and2rw–0rw–0Address 04hURXE0:USART0:UART mode receive enable UTXE0:USART0:UART mode transmit enableUSPIE0:USART0:SPI mode transmit and receiveenableAddress 05hrw–0,1:Legend:rw:Bit Can Be Read and WrittenBit Can Be Read and Written.It Is Reset or Set by PUC.Bit Can Be Read and Written.It Is Reset or Set by POR.SFR Bit Not Present in Devicerw–(0,1):memory organizationMSP430F438MSP430F439MemoryMain:interrupt vector Main:code memory Size Flash Flash 48KB0FFFFh --0FFE0h 0FFFFh --04000h 60KB0FFFFh --0FFE0h 0FFFFh --01100h Information memory Size Flash 256Byte 010FFh --01000h 256Byte 010FFh --01000h Boot memory Size ROM 1KB0FFFh --0C00h 1KB0FFFh --0C00h RAM Size 2KB09FFh --0200h 2KB09FFh --0200h Peripherals16-bit 8-bit 8-bit SFR01FFh --0100h 0FFh --010h 0Fh --00h01FFh --0100h 0FFh --010h 0Fh --00hbootstrap loader (BSL)The MSP430bootstrap loader (BSL)enables users to program the flash memory or RAM using a UART serial interface.Access to the MSP430memory via the BSL is protected by user-defined password.For complete description of the features of the BSL and its implementation,see the MSP430Memory Programming User’s Guide (SLAU265).BSL Function PN Package PinsData Transmit 67--P1.0Data Receive66--P1.1flash memoryThe flash memory can be programmed via the JTAG port,the bootstrap loader,or in-system by the CPU.The CPU can perform single-byte and single-word writes to the flash memory.Features of the flash memory include:D Flash memory has n segments of main memory and two segments of information memory (A and B)of128bytes each.Each segment in main memory is 512bytes in size.D Segments 0to n may be erased in one step,or each segment may be individually erased.D Segments A and B can be erased individually,or as a group with segments 0to n.Segments A and B are also called information memory.D New devices may have some bytes programmed in the information memory (needed for test duringmanufacturing).The user should perform an erase of the information memory prior to the first use.Main MemoryInformation Memory32KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh48KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh60KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh08400h 083FFh 08200h 081FFh 08000h 010FFh 01080h 0107Fh 01000h04400h 043FFh 04200h 041FFh 04000h 010FFh 01080h 0107Fh 01000h01400h 013FFh 01200h 011FFh 01100h 010FFh01080h 0107Fh 01000h†MSP430F439flash segment n =256bytes.peripheralsPeripherals are connected to the CPU through data,address,and control busses and can be handled using all instructions.For complete module descriptions,see the MSP430x4xx Family User’s Guide(SLAU056).DMA controllerThe DMA controller allows movement of data from one memory address to another without CPU intervention.For example,the DMA controller can be used to move data from the ADC12conversion memory to ing the DMA controller can increase the throughput of peripheral modules.The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.oscillator and system clockThe clock system in the MSP430F43x family of devices is supported by the FLL+module that includes support for a32768-Hz watch crystal oscillator,an internal digitally-controlled oscillator(DCO),and a high-frequency crystal oscillator.The FLL+clock module is designed to meet the requirements of both low system cost and low-power consumption.The FLL+features digital frequency locked loop(FLL)hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.The internal DCO provides a fast turn-on clock source and stabilizes in less than6µs.The FLL+module provides the following clock signals:D Auxiliary clock(ACLK),sourced from a32768-Hz watch crystal or a high-frequency crystal.D Main clock(MCLK),the system clock used by the CPU.D Sub-Main clock(SMCLK),the sub-system clock used by the peripheral modules.D ACLK/n,the buffered output of ACLK,ACLK/2,ACLK/4,or ACLK/8.brownout,supply voltage supervisorThe brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off.The supply voltage supervisor(SVS)circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision(the device is automatically reset)and supply voltage monitoring(SVM,the device is not automatically reset).The CPU begins code execution after the brownout circuit releases the device reset.However,V CC may not have ramped to V CC(min)at that time.The user must insure the default FLL+settings are not changed until V CC reaches V CC(min).If desired,the SVS circuit can be used to determine when V CC reaches V CC(min).digital I/OThere are six8-bit I/O ports implemented—ports P1through P6:D All individual I/O bits are independently programmable.D Any combination of input,output,and interrupt conditions is possible.D Edge-selectable interrupt input capability for all the eight bits of ports P1and P2.D Read/write access to port-control registers is supported by all instructions.Basic Timer1The Basic Timer1has two independent8-bit timers which can be cascaded to form a16-bit timer/counter.Both timers can be read and written by software.The Basic Timer1can be used to generate periodic interrupts and clock for the LCD module.LCD driveThe LCD driver generates the segment and common signals required to drive an LCD display.The LCD controller has dedicated data memory to hold segment drive mon and segment signals are generated as defined by the mode.Static,2-MUX,3-MUX,and 4-MUX LCDs are supported by this peripheral.watchdog timerThe primary function of the watchdog timer (WDT)module is to perform a controlled system restart after a software problem occurs.If the selected time interval expires,a system reset is generated.If the watchdog function is not needed in an application,the module can be configured as an interval timer and can generate interrupts at selected time intervals.USART0The MSP430F43x has one hardware universal synchronous/asynchronous receive transmit (USART)peripheral module that is used for serial data communication.The USART supports synchronous SPI (3or 4pin)and asynchronous UART communication protocols,using double-buffered transmit and receive channels.Timer_A3Timer_A3is a 16-bit timer/counter with three capture/compare registers.Timer_A3can support multiple capture/compares,PWM outputs,and interval timing.Timer_A3also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.Timer_A3Signal ConnectionsInput Pin NumberDevice Input Module Module Module OutputOutput Pin NumberPN Signal InputNameBlockSignalPN62-P1.5TACLK TACLK ACLK ACLK SMCLKSMCLK TimerNA62-P1.5TACLK INCLK 67-P1.0TA0CCI0A 67-P1.066-P1.1TA0CCI0B DV SS GND CCR0TA0DV CCV CC 65-P1.2TA1CCI1A 65-P1.2CAOUT (internal)CCI1B ADC12(internal)DV SS GND CCR1TA1DV CCV CC 59-P2.0TA2CCI2A 59-P2.0ACLK (internal)CCI2B DV SS GND CCR2TA2DV CCV CCTimer_B3Timer_B3is a 16-bit timer/counter with three capture/compare registers.Timer_B3can support multiple capture/compares,PWM outputs,and interval timing.Timer_B3also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.Timer_B3Signal ConnectionsInput Pin NumberDevice Input Module Module Module OutputOutput Pin NumberPN Signal InputName BlockSignalPN63-P1.4TBCLK TBCLK ACLK ACLK SMCLKSMCLK TimerNA63-P1.4TBCLK INCLK 58-P2.1TB0CCI0A 58-P2.158-P2.1TB0CCI0B ADC12(internal)DV SS GND CCR0TB0DV CCV CC 57-P2.2TB1CCI1A 57-P2.257-P2.2TB1CCI1B ADC12(internal)DV SS GND CCR1TB1DV CCV CC 56-P2.3TB2CCI2A 56-P2.356-P2.3TB2CCI2B DV SS GND CCR2TB2DV CCV CCComparator_AThe primary function of the Comparator_A module is to support precision slope analog-to-digital conversions,battery-voltage supervision,and monitoring of external analog signals.ADC12The ADC12module supports fast,12-bit analog-to-digital conversions.The module implements a 12-bit SAR core,sample select control,reference generator and a 16word conversion-and-control buffer.The conversion-and-control buffer allows up to 16independent ADC samples to be converted and stored without any CPU intervention.peripheral file mapPERIPHERALS WITH WORD ACCESSWatchdog Watchdog timer control WDTCTL0120h _Timer_B3Capture/compare register2TBCCR20196hCapture/compare register1TBCCR10194hCapture/compare register0TBCCR00192hTimer_B register TBR0190hCapture/compare control2TBCCTL20186hCapture/compare control1TBCCTL10184hCapture/compare control0TBCCTL00182hTimer_B control TBCTL0180hTimer_B interrupt vector TBIV011Eh _Timer_A3Capture/compare register2TACCR20176hCapture/compare register1TACCR10174hCapture/compare register0TACCR00172hTimer_A register TAR0170hCapture/compare control2TACCTL20166hCapture/compare control1TACCTL10164hCapture/compare control0TACCTL00162hTimer_A control TACTL0160hTimer_A interrupt vector TAIV012Eh Flash Flash control3FCTL3012ChFlash control2FCTL2012AhFlash control1FCTL10128h DMA DMA module control0DMACTL00122hDMA module control1DMACTL10124hDMA channel0control DMA0CTL01E0hDMA channel0source address DMA0SA01E2hDMA channel0destination address DMA0DA01E4hDMA channel0transfer size DMA0SZ01E6hperipheral file map(continued)PERIPHERALS WITH WORD ACCESS(CONTINUED)ADC12Conversion memory15ADC12MEM15015EhSee Conversion memory14ADC12MEM14015Ch also Peripheralsywith Byte Access Conversion memory13ADC12MEM13015AhConversion memory12ADC12MEM120158hConversion memory11ADC12MEM110156hConversion memory10ADC12MEM100154hConversion memory9ADC12MEM90152hConversion memory8ADC12MEM80150hConversion memory7ADC12MEM7014EhConversion memory6ADC12MEM6014ChConversion memory5ADC12MEM5014AhConversion memory4ADC12MEM40148hConversion memory3ADC12MEM30146hConversion memory2ADC12MEM20144hConversion memory1ADC12MEM10142hConversion memory0ADC12MEM00140hInterrupt-vector-word register ADC12IV01A8hInerrupt-enable register ADC12IE01A6hInerrupt-flag register ADC12IFG01A4hControl register1ADC12CTL101A2hControl register0ADC12CTL001A0hperipheral file map(continued)PERIPHERALS WITH BYTE ACCESSLCD LCD memory20:LCD memory16LCD memory15:LCD memory1LCD control and mode LCDM20:LCDM16LCDM15:LCDM1LCDCTL0A4h:0A0h09Fh:091h090hADC12ADC memory-control register15ADC12MCTL1508Fh (Memory control ADC memory-control register14ADC12MCTL1408Eh registers require byteADC memory-control register13ADC12MCTL1308Dh access)ADC memory-control register12ADC12MCTL1208ChADC memory-control register11ADC12MCTL1108BhADC memory-control register10ADC12MCTL1008AhADC memory-control register9ADC12MCTL9089hADC memory-control register8ADC12MCTL8088hADC memory-control register7ADC12MCTL7087hADC memory-control register6ADC12MCTL6086hADC memory-control register5ADC12MCTL5085hADC memory-control register4ADC12MCTL4084hADC memory-control register3ADC12MCTL3083hADC memory-control register2ADC12MCTL2082hADC memory-control register1ADC12MCTL1081hADC memory-control register0ADC12MCTL0080h USART0Transmit buffer U0TXBUF077h (UART or SPI mode)Receive buffer U0RXBUF076h Baud rate U0BR1075hBaud rate U0BR0074hModulation control U0MCTL073hReceive control U0RCTL072hTransmit control U0TCTL071hUSART control U0CTL070h Comparator_A Comparator_A port disable CAPD05Bh p_Comparator_A control2CACTL205AhComparator_A control1CACTL1059h BrownOUT,SVS SVS control register(Reset by brownout signal)SVSCTL056h。