实验五 max+plusⅱ的参数化兆功能模块库使

ENDESS(s1)
BEGIN
CASE s1 IS
WHEN "000"=>bcd_out<=no1_bcd;
WHEN "001"=>bcd_out<=no2_bcd;
WHEN OTHERS=>bcd_out<="0000";
END CASE;
END PROCESS;
WHEN "0111"=>dout<="0000111"; --07H显示"7"
WHEN "1000"=>dout<="1111111"; --7FH显示"8"
WHEN "1001"=>dout<="1101111"; --6FH显示"9"
WHEN OTHERS=>dout<="1111001"; --79H显示"E"错误
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY scan2aIS
PORT( clk_scan:IN std_logic;
en:OUT std_logic;
no1_BCD,no2_bcd:IN std_logic_vector(3 DOWNTO 0);
PROCESS(bcd_out)
BEGIN
CASE bcd_out IS
WHEN "0000"=>dout<="0111111"; --3FH显示"0"
WHEN "0001"=>dout<="0000110"; --06H显示"1"
WHEN "0010"=>dout<="1011011"; --5BH显示"2"
WHEN "0100"=>led7s<="1100110"; --66H显示"4"
WHEN "0101"=>led7s<="1101101"; --6DH显示"5"
WHEN "0110"=>led7s<="1111101"; --7DH显示"6"
WHEN "0111"=>led7s<="0000111"; --07H显示"7"
PORT(a:IN std_logic_vector(3 DOWNTO 0);
led7s:OUT std_logic_vector(6 DOWNTO 0);
en:OUT std_logic);
End decl7s2;
ARCHITECTURE one OF decl7s2 IS
BEGIN
PROCESS(a)
Ⅰ.VHDL源程序
（1）十进制计数器程序
LIBRARYieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY cnt10aIS
PORT(clk,rst,ena:IN std_logic;
count:OUT std_logic_vector(3 DOWNTO 0);
IF c1="1001" then outy<='1';
ELSE outy<='0';
END IF;
END IF;
count<=c1;
END PROCESS;
END beha;
(2)7段译码器程序
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decl7s2 IS
outy:OUT std_logic);
END cnt10a;
ARCHITECTURE beha OF cnt10aIS
SIGNAL c1:std_logic_vector(3 DOWNTO 0);
BEGIN
PROCESS(clk,rst,ena)
BEGIN
IF(rst='1')THEN
c1<="0000";
WHEN "1000"=>led7s<="1111111"; --7FH显示"8"
WHEN "1001"=>led7s<="1101111"; --6FH显示"9"
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
en<='0';
END;
(3)SCAN2A程序
LIBRARY ieee;
END CASE;
END PROCESS;
en<='0';
sel<=s1;
END behave;
Ⅱ.仿真波形
（1）十进制仿真波形
（2）100进制仿真波形
Ⅲ.元件符号
(1)十进制元件符号
（2）100进制元件符号
Ⅳ.实验体会
通过对十进制100进制的实验仿真，让我对程序设计更加了解了，在这次实验中我看到了自己的不足之处，以后一定会更加努力学习！
WHEN "0011"=>dout<="1001111"; --4FH显示"3"
WHEN "0100"=>dout<="1100110"; --66H显示"4"
WHEN "0101"=>dout<="1101101"; --6DH显示"5"
WHEN "0110"=>dout<="1111101"; --7DH显示"6"
BEGIN
CASE a(3 DOWNTO 0)IS
WHEN "0000"=>led7s<="0111111"; --3FH显示"0"
WHEN "0001"=>led7s<="0000110"; --06H显示"1"
WHEN "0010"=>led7s<="1011011"; --5BH显示"2"
WHEN "0011"=>led7s<="1001111"; --4FH显示"3"
sel:OUT std_logic_vector(2 DOWNTO 0);
dout:OUT std_logic_vector(6 DOWNTO 0));
END scan2a;
ARCHITECTURE behave OF scan2aIS
SIGNAL s1:std_logic_vector(2 DOWNTO 0);
SIGNAL bcd_out:std_logic_vector(3 DOWNTO 0);
BEGIN
PROCESS(clk_scan)
BEGIN
IF clk_scan'event AND clk_scan='1' THEN
IF s1<"001" THEN s1<=s1+1;
ELSE s1<="000";
ELSIF (clk'event AND clk='1') THEN
IF ena='1' THEN c1<=c1+1;
IF (c1>="1001") THEN c1<="0000";
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN