POWER6系统技术分析

POWER6 Technology OverviewIBM POWER™ SYSTEMSƒ ƒ ƒ ƒ 经过近20年POWER处理器技术持续不断的发展和进步 研发第六代POWER处理器 – POWER6 第五颗双核(Dual Core)芯片 IBM在过去十多年一直遵守承诺, 按时发布 POWER2007 2006 2004 2003 2001POWER4™ POWER4+™ POWER5™ POWER6™ POWER5+™Processor History 2001 - 2007Dual-Core 1 GHz Distribute Switch Multithreading Memory Controller on Chip Enhanced Multithreading Memory Controller on Chip >4 GHzPOWER4 414 mm2 1.1 – 1.3 GHzPOWER4+™ 267 mm2 1.5 – 1.9 GHzPOWER5 389 mm2 1.65 – 1.9 GHzPOWER5+™ 245 mm2 1.9 – 2.3 GHzPOWER6 341 mm2 3.5 – 4.7 GHz20012002200320042005200620072008IBM POWER处理器, 开创行业新标准1997 1999 2001 2001 2001 2001 2002 2004 2004 2005 2006 2007 2007 全世界第一枚处理器采用铜芯片(Copper)芯片制造技术 全世界第一枚处理器采用绝缘硅(SOI)芯片制造技术 全世界第一枚处理器采用双核(Dual Core)技术 全世界第一枚RISC处理器采用８核多芯片模块(MCM)技术 全世界第一枚RISC处理器超越 1GHz 主频 全世界第一枚RISC处理器支持逻辑分区(LPAR)技术 全世界第一枚RISC处理器支持动态逻辑分区(DLPAR)技术 全世界第一枚RISC处理器支持微分区(Mirco-Partition)技术 全世界第一枚RISC处理器支持并发多线程(SMT)技术 全世界第一枚处理器广泛应用于主要电视游戏机平台 全世界第一枚处理器采用Dual Stress芯片制造技术 全世界第一个厂商发布High-K(Hafnium)Metal Gate半导体技术 全世界第一枚处理器超过4GHz主频SiO2SOIPOWER 系统的性能价格比发展趋势图tpmC 3500000 3000000 $/tpmC$109.003,210,541 $120$100$89.002500000 2000000Cost$52.70$80Performance$43.00 1,025,486$601500000 1000000$40763,898 $17.80 403,255 220,807 $8.31$2050000018,6660 S70199734,139S7A1998135,815$5.42$5.19$0S801999S852000p6902001-2002p690+2002 2003p690++2004p5-5952005IBM POWER 芯片架构历代演变POWER4™POWER4 Core POWER4 CorePOWER5™POWER5 Core POWER5 CorePOWER6Alti POWER6 Vec CorePOWER6 Alti Core VecL2L3L3 CtlL2 L3L3 Ctrl4 MB L24 MB L2Distributed Switch L3 CntrlEnhanced Distributed SwitchMemory CntrlFabric Bus ControllerMemory Controller GX Bus CntrlL3 GX Bus Mem Ctl Memory Memory GX BusGX+ BridgeMemory+IBM 将于 2007 推出新一代 POWER 处理器技术 2007年5月22日 IBM POWER5+ 处理器技术仍然在 UNIX 市场领先 隆重推出 Systemp5 590/595First POWER6 16-way p570 systemNEW!ƒ The absolute best midrange performance in the industry! ƒ Compatible with existing software applications Systemp5 560Q Express System p5 550 & 550Q System p5 520 Express & 520Q ExpressSystem p5 570POWER6 p570System p5 510 & 510Q Express System p5 505Q ExpressSystem p5 575POWER6IBM BladeCenter™IBM IntelliStation™ POWER 185 and 285 ExpressPOWER5 / 5+ 设计回顾POWER5+ design 1.65, 1.9 ,2.2, 2.3GHz POWER5 design1.5, 1.65 and 1.9 GHz .09 micron .13 micronPOWER5 / 5+POWER5/5+P L3L3 Ctl并发多线程 SMT 微分区技术Sub-processor allocationP L2P L2PL3 CtlL3增强的分布式开关 增强的内存子系统Larger L3 cache: 36MB Memory controller on-chipDist. Switch Fab CtlMem CtlDist. Switch Fab CtlMem Ctl密集型计算能力进一步提高 动态节能模式Clock gatingGX BusGX BusMemoryMemoryPOWER5 / 5+的三种封装技术PP L2 PP L2 PP L2L3L3L3双核模块 (DCM) POWER5+ 双核芯片 + L3 cache chip (505,510,520, 550,570)四核模块 (QCM)两路 POWER5+ 双核芯片 + 双 L3 缓存芯片 (510Q,520Q,550Q,560Q)PP L2PP L2PP L2PP L2L3L3L3L3多核模块 (MCM)四个双核 POWER5 芯片 + 四个 L3 缓存芯片 - 8处理器核心 (590, 595)并发多线程技术(SMT，逻辑CPU)POWER4 (Single Threaded) POWER5 (simultaneous multi-threading)FX0 FX1 LSO LS1 FP0 FP1 BRZ CRL时钟周期 Logical CPU0 Logical CPU1Thread0 active No thread active Thread1 activeThread0 purr0Thread1 purr1Physical CPU timebase registerƒ 提高CPU执行单元的利用率 ƒ Presents symmetric multiprocessing (SMP) programming model to software ƒ 自动适应超标量执行指令无序性ƒ 每个处理器调度两个线程:“对应用和操作系统而言，CPU数量扩展了两倍.”ƒ 支持并发多线程（SMT）操作模式，在相同主频下，针对高吞吐量类型的商业数据库应用、 Web应用、Java应用等，POWER5服务器平均比以前的服务器提升15-40%的性能。

SMT 测试案例：SMT 技术使Oracle 9i 数据库处理能力提升42%!!!CPU Total eval-dom1 3/9/200410203040506070809010012:3412:3612:3812:4012:4212:4412:4612:4812:5012:5212:5412:5612:5813:0013:0213:0413:0613:0813:1013:1213:1413:1613:1813:2013:2213:2413:2613:2813:3013:3213:3413:3613:3813:4013:4213:44User%Sys%Wait%CPU Total eval-dom1 10/9/2004010203040506070809010014:5614:5714:5814:5915:0015:0115:0215:0315:0415:0515:0615:0715:0815:0915:1015:1115:1215:1315:1415:1515:1615:1715:1815:1915:2015:2115:2215:2315:2415:2515:2615:27User%Sys%Wait%CPU Total eval-dom1 10/9/200410203040506070809010010:4510:4710:4910:5110:5310:5510:5710:5911:0111:0311:0511:0711:0911:1111:1311:1511:1711:1911:2111:2311:2511:2711:2911:3111:3311:3511:3711:3911:4111:4311:4511:4711:49User%Sys%Wait%AIX 5.2 -8-way, 64 GB p570700 Users180 Transactions per Second< 0.05 sec response timeAIX 5.3 (SMT) –cached (low wait)1000 Users280 Transactions per Second< 0.05 sec response timeAIX 5.3 (SMT)700 Users~180 Transactions per Second< 0.05 sec response timeGartner Magic Quadrant 市场分析HP IntegrityChallengersLeadersNiche Players VisionariesCompleteness of VisionA b i l i t y t o E x e c u t eStratus ftServerIBM System p5Unisys ES7000HP 9000SUN Fire U/SPARC IV+IBM System zBull NovaScale HP Integrity NonStop Fujitsu PrimequestFujitsu PrimergySun Fire T2000Sun Fire x86HP BladeSystemIBM BladeCenter Dell PowerEdge IBM System xIBM System i HP ProLiantFujitsu Primepower Gartner, Magic Quadrant For Enterprise Servers 2006, August 10, 2006.; Philip Dawson, Jonathon Hardcastle, Andrew Butler, Donald Feinberg, PaulMcGuckin.ID Number: G0*******The Magic Quadrant is copyrighted 2006 by Gartner, Inc. and is reused with permission, which permission should not be deemed to be an endorsement of any company or product depicted in the quadrant. The Magic Quadrant is Gartner, Inc.'s opinion and is an analytical representation of a marketplace at and for a specific time period. It measures vendors against Gartner defined criteria for a marketplace. The positioning of vendors within a Magic Quadrant is based on the complex interplay of many factors. Gartner does not advise enterprises to select only those firms in the "Leaders" quadrant. In some situations, firms in the Visionary, Challenger, or Niche Player quadrants may be the right matches for an enterprise's requirements. Well-informed vendor selection decisions should rely on more than a Magic Quadrant. Gartner research is intended to be one of many information sources including other published information and direct analyst interaction. Gartner, Inc. expressly disclaims all warranties, express or implied, of fitness of this research for a particular purpose.Leverage our Leadership for the price premium it deserves处理器研发所遇到的瓶颈问题-Reduce transistor power-Reduce switching per function -More slower threads -Specialized function -More slower threads -Asynchronous loads1.Power Wall (耗电量的障碍)2.Frequency Wall (时钟主频的障碍)3.Memory Wall (内存吞吐量的障碍)Increase Concurrency(增加并发能力)Increase Specialization(增加专门功能)创新的芯片制造技术:Dual Stress & HIGH-K Metal Gate (Hafnium)What is Dual Stress Technology ?Technology incorporated into POWER5+ processor Strained Silicon on Silicon-on-Insulator technology Stretches & compresses transistors Stress film technologyProvides more efficient flow of electrons No special materials requiredBenefit :Increase transistor speeds by up to 20% without increasing power consumption Reduce electric current leaksGreater performance without increasing power & heatPOWER5+Stress film layerWhat is High-K Metal Gate Technology ?January 27, 2007, IBM and Intel had developed a new “high-k”material, based on the element Hafnium , that could be substituted for the traditional gate oxide used in the transistors that make up microchips using 45nm technologyPOWER DesignPOWER6 Characteristics4.7 / 4.2 / 3.5 GHz>750M transistors65nmPOWER6 处理器架构Ultra-high frequency dual-core chip: 4.7GHz 7-way superscalar, 2-way SMT core Eight execution units2LS, 2FP, 2FX, 1VMX, 1DP 790M transistors, 341 mm 2die2x4MB on-chip L2 –point of coherency On-chip L3 directory and controller TechnologyCMOS 65nm lithography, SOI CuHigh-speed elastic bus interface at 2:1 freq Full error checking and recovery Dynamic power savingAdvanced clock gatingMemory+GX+ BridgeGX Bus CntrlMemory ControllerFabric Bus ControllerPOWER6Core Alti VecL3CtrlL3POWER6CoreAlti Vec 4 MB L24 MB L2POWER6 芯片架构Dual Core chip2-way SMT coreUltra-high frequency4.7 / 4.2 / 3.5 GHz>750M transistorsSuperscalarLarge on-chip L2On-chip L3 directory & controller Two memory controllers on-chip TechnologyCMOS 65nm lithography, SOI Error checking and recoveryIFUSDUFXURU AltiVecFPUDFUL2Cache L2CacheL2Cache L2CacheLSUFPULSUIFUSDU RUFXUDFUAltiVecPOWER5+ 与POWER6 处理器之比较64 KB, 4-way 64 KB, 2-way ICache capacity, associativity L1 Cache64 KB, 8-way32 KB, 4-wayDCache capacity, associativity 8-way, LRU10-way, LRUAssociativity, replacement 2 x 4 MB, 128 B line1.9 MB, 128 B line Capacity, line size 8 TB maximum 4x DRAM frequency4 TB maximum 2x DRAM frequencyMemory Memory bus16-way, LRU 12-way, LRU Associativity, replacement 32 MB, 128 B line 36 MB, 256 B line Capacity, line size Off-chip L3 Cache L2 CachePOWER6POWER5+POWER5+ 与POWER6 处理器之比较Mostly in-order with special case out-of-order executionGeneral out-of-order executionStyle2FX, 2LS, 2FP, 1VMX, 1DP2FX, 2LS, 2FP, 1BR, 1CR UnitsTwo SMT threads Priority-based dispatchSimultaneous dispatch from two threads (up to seven instructions)Two SMT threads Alternate ifetch Alternate dispatch (up to five instructions)ThreadingPOWER6POWER5+POWER6* CorePOWER6 processor is ~2X frequency of POWER5 (4-5GHz)POWER6 instruction pipeline depth equivalent to POWER5Minimize powerScale performance with frequencyInstruction FetchInstruction Buffer/DecodeInstruction Dispatch/IssueData Fetch/ExecuteFXU Dependent execution Load Dependent executionPOWER6 extends functionality of POWER5 Core64K I Cache, 64K D Cache, 2 FXU, 2 FPU, 1 Branch execution unit Two way SMT with 7 instruction dispatch from 2 threads (maximum of 5 instructions per thread) Decimal Unit VMX UnitRecovery Unit~6ns/instr~3ns/instrFX0FX1LSO LS1FP0FP1Thread1 activeThread0 activeNo thread activeUtilizes unused execution unit cyclesReuse of existing transistors vs. Performance from additional transistors Presents symmetric multiprocessing (SMP) programming model to softwareDispatch two threads per processor: “It’s like doubling the number of processors.”Net result:–Better performance–Better processor utilizationAppears as four CPUsper chip to the operating system (AIX 5L™V5.3 andLinux®)S y s t e m t h r o u g h p u tPOWER5SMT STPOWER6 Enhanced Simultaneous Multithreading POWER6SMTPOWER5 Simultaneous MultithreadingPOWER6Delivers Improved System UtilizationThrough Enhanced Simultaneous MultithreadingDPVMXPOWER6* scales chip capabilities with core performanceCache highlights 4MB Private L2 Cache per Core 32MB Non-sectored L3 Cache per chip Fabric highlights Three Intra-Node SMP buses for 8-way Node Two Inter-Node SMP buses for up to 8 Nodes Multiplexed Address/Data SMP buses New prefetching capabilities Coherent Multi-Cacheline Data Prefetch Operations Prefetching on stores80GB/sCoronaCore(SMT+, VMX)2X2B A 2X8B D 2X8B DCore(SMT+, VMX)L3 Cache 32MBL3 Dir L3 Cntl Mem Cntl Mem CntlL2 Cache (8.0MB) GX+ Cntl FabricA/D A/D20GB/s4B 4B4X1B 4X1B 4X2B 4X1B 4X1B 4X2BA D D A D DGX+ BusA/D A/D A/D8B 8B75 GB/s Total = 300 GB/sA/D8B 8BA/D A/DA/D A/DA/D A/D 8B 8B8B 8B8B 8BIntra-Node 8W SMP Buses50GB/s80GB/sFlex System designed to help optimize low-end to high-end server designsSMP busses can be configured in two modes Cost/performance trade-offs On node busses are 8B or 2B Off node busses are 8B or 4B Numerous memory controller BW options 1 or 2 memory controllers are available Memory controllers can be configured to full width or ½ width L3 cache is supported in three configurations On module High Bandwidth configuration Optional off module configuration No L3 option Fully interconnected two-tier SMP fabric Reduced latencies vs. POWER5 New two tier memory coherency protocol2 socket4 socket32 socketPOWER5 and POWER6 Nodal TopologyPOWER5 and POWER6 System TopologyIBM p6 p570 Modular Architecture enhanced with new flex cables¾ POWER6 fabric bus connects processors together in separate drawers using a new SMP Flex cable ¾ Flex cable attaches directly to the CPU cards at the front of the drawer. ¾ To grow from 2 to 3 to 4 drawers only requires cable additions ---no “parts on the floor.”Designed for bullet-proof computingRecovery CapabilityArray error ƒ Error correction (ECC) ƒ Arrays with parity ™Processor restarts Instruction flow and Data flow Error ƒ Processor restarts Control Error ƒ Processor restartsCoreInstruction Fetch DecodeExecution UnitsCore error collectionLoad/ StoreRecovery unit Core restartSystem Resiliency Processor states are check pointed and protected with ECC Processor states can be moved from one processor to another upon unsuccessful recovery restartDesigned for bullet-proof computingSystem RAS with recovery unit Extensive measures taken to preserve application execution Retry soft errors Change hardware for hard errorsProcessor architected state check pointed Every 1 cycle ECC & Non-ECC protected circuitry checked Every cycleNo error found Error foundProcessor restarts from last saved checkpointError foundNo error foundSoft error caseProcessor workload moved to another CPUHard error caseDecimal Floating-pointDescription: New / more precise mechanism for Decimal Arithmetic Markets: DB servers, Financial Sector Applications, etc.Binary Floating-point problem….Add 5% sales tax to a $ 0.70 telephone call, rounded to the nearest cent 1.05 x 0.70 using binary double is exactly 0.73499999999999998667732370449812151491641998291015625 (should have been 0.735) rounds to $ 0.73, instead of $ 0.74Decimal Floating-point benefit…. True decimal processing; .735 BenefitsPerformance and AccuracyRequirement:AIX 5.3 TL06Decimal Floating Point AcceleratorsBinary floating-point unsuitable for commercial or human-centric applications Survey of numeric data in commercial databases is largely decimal data55% of numeric data in databases is BCD data The next 43% of data is integers, often held as decimal integersExample: performance improvement of decimal hardware vs. decimal softwareTelco billing application -- 1 million calls (2 minutes) read from file, priced, taxed, and printed:Java BigDecimal w/ DEC number % execution time in decimal operations Speedup with hardware DFP** IBM projectionC, C# packages 72 – 78% 4XInteger hand-tuned 45% 2X93.2% < 7XStandards & software rallying around DFP standardizationNumerous software and standards activities in flight inside and outside IBM  Java BigDecimal (compatible with 754r)  C# and .Net ECMA and ISO standards arithmetic changed to match 745r decimal128  XML Schema 1.1 draft now has pDecimal compatible with 754r  ISO C and C++ are jointly adding decimal floating-point as first-class primitive types  GCC almost complete  Cobal is adding a datatype to support 754r  ANSI/ISO SQL … new types accepted in principle (draft about to be submitted)  Strong support expressed by Microsoft, SHARE, academia, SAP and many othersPOWER6 AltiVec Vector TechnologyDramatic application performance gains SIMD (Single Instruction, Multiple Data) Extension to PowerPC Architecture™, jointly developed by Apple, Motorola, IBM  Targets High Performance Computing and Deep Computing applicationsBenefit to ISVs / clients: Provides highly parallel operations Dramatically better performance for highly “vectorized” codeDevelopment / test environment: Current support: IBM BladeCenter® JS21 or IBM IntelliStation® POWER™ 185 Express ƒ Supported by AIX® and Linux releases  IBM XL C/C++ Enterprise Edition V8.0 for AIX (October 2005) provides ƒ Support for the AltiVec instruction set ƒ Support for the AltiVec programming model and APIs  IBM XL Fortran Enterprise Edition V10.1 for AIX (October 2005) can ƒ Automatically enable SIMD vectorization at higher levels of optimization Additional compiler support for AltiVec™ vectorization extensions will be available in XL C/C++ V9.0, with Automatic SIMD vectorization  Redbook: /abstracts/redp3890.htmlPOWER6 System EnhancementsPowerExecutive Extensions for POWER6 Energy Management PoliciesExample Energy Management Policies: ƒ Energy cost management– Monitor System workloads/power consumption • If: System utilization reduces reduce system power/performance • If: Multiple Systems go below utilization threshold consolidate workloads • If: System power budgets exceed allocation cap powerPowerExecutiveƒ Acoustic enhancement– Monitor Systems temperature • If system temperatures go below threshold reduce fan speedsƒ Performance enhancement– Monitor system temperature/power consumption • If temperatures/power consumption go below threshold increase performanceEnergy management policies designed to enable clients to maximize the compute capability of their data center or minimize energy costsEMPATH System Control planned for POWER6* Extended System Functions For PowerExecutive PoliciesThermal / Power MeasurementHardware Management ModuleIBM Director PowerExecutiveRead thermal data from processor chip thermal sensors Measure power data from system level sensors Report data via PowerExecutivePower CappingIBM POWER6 Service ProcessorPower Control Firmware AME API Power Mgmt Policies EMPATH ControllerUse of Hardware controls to keep system power under a specified limitPower SavingOperation at reduced power when workload and policy allowsƒ Can be a static policy (e.g. overnight reduction) ƒ Can be dynamic (when absolute max performance is not always required)System health monitoringPower ModulesPower Measurement CircuitsUse of hardware sensors to help ensure system is operating within safe predefined boundsPerformance-Aware Power ManagementUse of dedicated performance counters to guide power and thermal management tradeoffsSummary and conclusionsPOWER6* doubles frequency and bandwidth of POWER5 Same pipe depth Same power envelope POWER6* scales chip/system performance with core performance POWER6* provides new capabilities Decimal Floating Point Processor recovery System p will begin delivery of system power management with POWER6* POWER6* is on track to deliver high frequency capabilities。