51.2 A New Low Power PMOS Poly-Si Inverter and Driving Circuits

51.2 / S.–H. Jung1396 • SID 03 DIGEST 51.2: A New Low Power PMOS Poly-Si Inverter and Driving Circuitsfor Active Matrix DisplaysSang-Hoon Jung, Woo-Jin Nam, Chang-Wook Han and Min-Koo HanSchool of Electrical Engineering, Seoul National University, Seoul, KOREAAbstractA new low power inverter employing only p-type poly-Si TFTs is proposed for driving circuits of AMLCD and AMOLED. The proposed PMOS inverter, employing asymmetric feed through and bootstrapping, successfully eliminates troublesome through current and exhibits a wide output swing from V DD to V SS. PMOS level shifter and PMOS shift register have been successfully designed by employing the proposed PMOS inverter.1. IntroductionLow temperature poly-Si (LTPS) thin film transistor (TFT) allows for peripheral integration of driving circuits with pixel panel due to a high current driving capability. Gate driving circuits and data sampling circuits, which consist of LTPS-TFTs, are widely considered for active matrix liquid crystal displays (AMLCDs) or active matrix organic light emitting diode (AMOLED) displays. Recently, PMOS technology rather than CMOS has attracted a considerable attention for the system on panel integration [1]. Because the stability of p-type poly-Si TFTs due to the hot carrier stress is much better than n-type TFTs, PMOS poly-Si circuits may be considerably stable compared with CMOS poly-Si circuits [1,2,3]. Furthermore, PMOS technology enables to simplify the fabrication process of integrated driving circuits and pixel switching circuits on glass or plastic substrates although it is rather simple to design the system in CMOS technology.It has scarcely been reported that any PMOS inverter would function comparable with push-pull CMOS inverter. It is well known that inverters with an active load or a current sink load usually exhibit the troublesome through current and the output swings of them are not determined from V DD to V SS but determined by the size of TFTs (Fig. 1).VV V V DDV V DDInputSS (a)V DDSS (b)SS (c)Fig. 1 (a) push-pull CMOS inverter, (b) PMOS inverter with a current sink load, (c) PMOS inverter with an active register.The purpose of our work is to propose a new low power PMOS inverter, which completely suppresses the through current and has wide output swing from V DD to V SS just like push-pull CMOS inverter, by employing asymmetric feed through and bootstrapping. We also propose a new low power PMOS level shifter and shift register by employing the proposed PMOS inverter2. Low Power PMOS InverterThe proposed inverter that uses only p-type TFTs is shown in Fig.2. P1, P2 and P3 are employed for the inverting circuit and P4 and P5 are used for the buffer. When the proposed inverter operates like push-pull CMOS inverter, the range of output would be obtained from –10V to 0V with input swing from 0V to –10V. When input signal is –10V, P1, P2 and P4 are turned on and P3 and P5 are turned off. Then the output voltage is equal to V DD (0V) at this time.VDD -10 V-20 VFig. 2 the proposed inverter that uses only p-type TFTsIt is rather difficult that the output voltage becomes V SA . Because the voltage of node B should be less than V SA in order to turn on P5 and the voltage of node A should be less than V SS in order to turn on P3. However, P3 cannot be turned on by any other voltage source because V SS is the lowest voltage in the circuit.In order to overcome this problem, the proposed inverter employs asymmetry feed through and bootstrapping at the rising edge of the input signal. When the input signal changes from –10 V to 0 V, the node A and the node B are affected by feed-through of the input signal. In Fig. 2, the size of P2 is much larger than that of P1, so that the node B is affected much more than the node A by feed through. It means the voltage of the node B is higher than that of the node A. When the voltage difference of the node A andISSN/0003-0966X/03/3402-1396-$1.00+.00 © 2003 SID51.2 / S.-H. JungSID 03 DIGEST • 1397B exceeds the threshold voltage of P3, P3 would be turned on. Then, the voltage of the node B is rapidly lowered to V SS and the voltage of the node A is also lowered by ‘bootstrapping’. Finally, P3 and P5 would be turned on and P1, P2 and P4 would be turned off so that the output voltage is reached to V SA without any through current. The voltages of node A, B, input and output are shown in Fig. 3.Input Node ANode B OutputFig. 3 Simulated waveforms: Input, output, node A and BFig. 4 Simulated result: Through current of P2Fig.4 shows the drain current of P2 for the clock signal. In the conventional PMOS inverter (with an active load or current sink load), the TFTs that act as the active load or current sink load are always turned on. It means that the stable through current is exhibited, so that power loss problem cannot be avoided. In the proposed PMOS inverter, there is no stable through current as shown Fig.4. Only transition current is observed like CMOS inverters and the current is controlled by the size of the TFTs. It may be noted that the size of P2 should be much larger than that of P1 (about 100 times in simulation) in order to induce the asymmetric capacitive coupling. However, it should be noted that any severe area problem is not occurred because total area generally depends on large TFTs used for the buffer of the driving circuit.3. Low Power PMOS Level shifterIt is well known that the inverter is a building block of digital logic gates, so that PMOS digital logic gates can be also embodied by the proposed inverter. Furthermore, widely used circuits in active matrix display panel such as level shifter and shift register, which consist of only p type TFT, are easily obtained by employing the proposed inverter.In Fig. 2, when V SA is –15V, the output is easily obtained as a level shifted inverting signal. When the cascade configuration is employed as shown in Fig. 5, a low power PMOS level shifter is obtained and the level shifted output voltage follows V SB . The simulation results of the proposed level shifted inverter and level shifter are shown in Fig. 6 and verify that the proposed circuits operate successfully.V SS -30 VDDFig. 5 Low power PMOS level shifter (cascaded configurationof the level shifted inverter)Inverting signalInput signalLevel shifted Level shifted signalFig. 6 Simulation results of the proposed level shifter and levelshifted inverter.51.2 / S.–H. Jung 1398 • SID 03 DIGEST4.Low Power PMOS Shift RegisterA PMOS shift register has been reported for the gate driver of AMLCD or AMOLED [1]. It requires 4-phase clock signals. Another 2 kinds of PMOS shift register have been also reported, which requires only 2-phase clock signal [4,5]. However, plural clock signals would induce the clock skew problems.In this work, a new low power shift register, which consists of only p type TFTs and requires only 1 clock signal, is also proposed. Comparing reported PMOS shift registers, the proposed 1 clock PMOS shift register would not make any clock skewproblem or any overlapping gate scanning. Especially, for AMOLED, it is a merit that there is sufficient time to change the data current between scan pulses.The neighboring 2 cells of the proposed shift register are shown in Fig. 7, and Fig. 8 shows the timing diagram. P7, P8, P9 and P10 are used for output buffer and P1, P3, P5 and P6 operate like the proposed PMOS inverter. P2 and P4 work for the reset. The driving mechanism is that the rising output edge of the Nth cell would enable the (N+1)th cell and disable the Nth cell through the inverter of the (N+1)th cell..ClockOutput Output P7 of 0 ~ –20 VNN+1Stage N+2Stage N+2Fig. 7 The proposed 1 clock PMOS shift register cellsStart CLK 1StartOut 1Out 2Out 3Out 4Fig. 9 Simulation result of 1 clock PMOS shift registerFig. 8 Timing diagram51.2 / S.-H. JungSID 03 DIGEST • 1399For the details, when the start signal is –20V, P3 and P6 are turned on and P7 and P8 are turned off, the output remains as previous state ( 0V ). When the start signal changes from –20V to 0V (rising edge), P5 is turned on by the proposed inverting mechanism and P6 is turned off. From this time (‘enabling state’), the clock signal passes through P7 and the output signal is obtained. The proposed shift register employs the dual buffer structure. P7-P8 pair is used for the large output load and P9-P10 pair is adopted for the start signal of the next cell. Because the driving mechanism of the proposed circuit is capacitive coupling, the output signal delayed by the large output load is not sufficient for the start signal for the next cell so that P9-P10 pair is adopted for the fresh start signal. When the next cell is enabled, the gate voltage of P17 is transferred to the previous cell through P2 and the previous cell is disabled (P1, P4 and P8 are turned on and output is 0V).It was verified by the SPICE simulation that the proposed shift register operates successfully when the load capacitance is 100 pF (Fig. 9). The SPICE parameters have been extracted from fabricated the p-type poly-Si TFTs. The mobility and the threshold voltage of the poly-Si TFT were 65 cm 2/Vs and −2V5. PMOS Integration on the panelThe integration of gate driver on the panel, which consists of only p-type poly-Si TFTs, may be easily achieved by employing the proposed PMOS level shifter and the proposed PMOS shift register. The basic block diagram is shown in Fig. 10.Fig. 11 shows the schematic diagram of PMOS data driver. For the basic analog driving method, the PMOS integration of data driver is also possible by employing the proposed PMOS circuits (Fig. 11(a)). In the case of the digital driving method, another unit circuits are needed for the integration of data driver (Fig. 11(b)). However, these unit circuits are also possible to be embodied with only PMOS by using the proposed PMOS inverter. Consequently, it means that fully integration of p-type peripheral driving circuits is possible.Fig. 10 Schematic diagram of gate-driver which consists ofonly p-type TFTs(a)(b)Fig. 11 Schematic diagram of PMOS data-driver; (a) analogdriving method (b) digital driving method6. ConclusionWe have proposed a new low power inverter, which consists of only p type poly-Si TFTs. The proposed inverter, employing asymmetry feed through and bootstrapping, eliminates troublesome through current and exhibits wide output swing range. We have also proposed the low power PMOS level shifter and the shift register by employing the proposed inverter. The proposed PMOS circuits may be suitable for low power AMLCD and AMOLED display panel.6. Reference[1] Y. M. Ha, “P-type Technology for Large Size LowTemperature Poly-Si TFT-LCDs”, SID 2000, pp.1116~1119, 2000 [2] J.R. Ayres et al., “Analysis of drain field and hotcarrier stability of poly-Si thin film transistors”, Jpn. J. Appl. Phys . Vol. 37 pp. 1801-1808, 1998[3] Y. Uraoka et al., “Reliability of Low TemperaturePoly-Silicon TFTs Under Inverter Operation”, IEEE Trans. on Electron Devices, Vol. 48, No. 10, p. 2370, 2001[4] W. J. Nam et al., “A Novel Shift Register DrivingScheme For Active Matrix Displays “, AMLCD, pp.187-190, 2002[5] S. H. Jung et at., “2 Clock Shift Register byEmploying P-type Poly-Si TFTs for Active Matrix Displays”, ASID, pp.309~312, 2002。