导航模块芯片的PCB设计指导文件(SiRF)

PCB Design Guidelines for SiRFstarIII Implementation (Preliminary)Document Number APNT3002Revision 0.110/01/04PROPRIETARY NOTEThis document contains proprietary information to SiRF Technology, Inc. and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without expressed written consent of SiRF Technology, Inc.SiRF Application Note:PCB Design Guidelines (SSIIxFamily)APNT0006Revision 3.0 7/16/04Table of Contents1INTRODUCTION (1)1.1G ENERAL PCB G UIDELINES (1)2RF DESIGN ISSUES (2)2.1T RACKS,P ADS, AND G ROUND P LANES (2)2.2RF C OMPONENTS (3)2.3G AIN,S TABILITY AND B Y-P ASSING (4)2.4C RYSTAL O SCILLATOR R EQUIREMENTS (5)2.5RF&P OWER S UPPLIES IN G ENERAL (5)3SIRF RECEIVER LAYOUT GUIDELINES (6)3.1PCB F ABRICATION R EQUIREMENTS (6)3.2P LACEMENT OF C OMPONENTS (6)3.2.1Layer Stacking (7)3.3R OUTING I SSUES (8)3.4H IGH D ENSITY L AYOUTS AND T EST A CCESS (9)4ANTENNA PLACEMENT CONSIDERATIONS (9)5COMMON PROBLEMS TO AVOID (10)6SUMMARY (11)7DOCUMENT MAINTENANCE (11)7.1R EQUIRED A PPROVAL FOR C HANGES (11)7.2R EVISION H ISTORY (11)Revision 3.0 7/16/041INTRODUCTIONThis document will present some of the critical issues that arise when laying out a new GPS design based on the SiRFstarIII chipset with integrated FLASH memory. Since the RF characteristics of the receiver are generally the most critical, they will be discussed in detail followed by suggested SiRF GPS layout guidelines. All new designs based on the SiRFstarIII chipset should follow these guidelines. SiRF Applications Engineering is also available to review new designs before they are released for PCB fabrication.1.1General PCB GuidelinesBefore discussing the critical RF concerns it is worthwhile summarizing some very basic issues when starting a new layout, since proper connector and component placement is the critical first step to generating a new design.•SiRF reference designs are typically done on a 4-layer or 6-layer, 2-sided, standard FR4 board.•All parts should be surface mount (if possible).•Connector locations should be placed to avoid noisy system interconnect cables from running across the GPS board. Smaller connectors are recommended, with proper grounding and/or contact isolation.•All RF components should be placed to minimize trace lengths and crossovers.This is the key to a successful RF design.•For RF, pins should please refer to reference schematic. All other power pins on all IC’s should have a minimum of a 0.01uF decoupling capacitor (for approximately every two power pins if feasible) placed as close to the IC as possible and connected directly to the power and ground planes of the board.Additional capacitors may help to reduce the switching noise that could occur if this is anticipated.•Reserve space for shielding of the RF and the baseband (adequate shielding is necessary to isolate the sensitive RF section and antenna from other noise-generating circuitry) Shields should be continuously soldered to the board, not simply tacked down. Shields solder rings require via grounding at 100mil spacing, minimum.•The RF and digital circuitry should be grouped in separate sections on the board •All RF grounds should be tied directly to the ground plane using a dedicated vias or multiple vias and minimal trace interconnects.•High pin-count digital components should be placed to minimize routing of multi-trace bus lines.Revision 3.0 7/16/04•TCXO and crystal oscillator circuits should be well isolated from high slew-rate digital signals, and thermal isolation should be maximized for best performance.This requirement MUST be followed for proper performance!•The designer should always follow the manufacturer’s DFM/DFT requirements.Test access points are highly recommended and usually required during system development.•Attempt to use the same components that SiRF specifies as a part of the reference design bill of materials. Alternate parts should be fully characterized for compatibility before considering design substitution.•Keep the RTC section away from the digital and RF circuitry. The RTC circuitry should be routed over the ground plane if possible. Otherwise, avoid any digital signals underneath the RTC. Use of cylindrical can crystals is not suggested. Although very basic, if these guidelines are adhered to during the initial parts placement then a majority of the PCB related problems can be avoided.2RF Design IssuesRF circuits present new challenges to designers of lower-frequency digital circuits. RF circuits usually deal in nano-volts (<-140dBm) and the stability of oscillators has to be in the parts-per-billion! Signals will not be contained on lines they are supposed to and components do not act as they are expected to. To be able to actually build circuits correctly it is important to have an understanding of the basic properties of circuits from an RF point of view. The following section discusses some of the basic RF design issues that were addressed in developing SiRFstarIII consisting of the GRF3f reference design.2.1Tracks, Pads, and Ground PlanesMost RF circuits are built over a solid, continuous ground plane to provide better control of parasitic coupling and electrical grounding. All tracks, pads, and components are capacitively coupled by their physical proximity to each other. If a ground plane is used there is a large capacitive element to ground, which reduces the coupling between parts. It also provides for a well-controlled return path for currents, which helps keep signals localized.Component pads also generate a capacitance to ground, which effectively adds small capacitors to ground each time a pad is used. This is usually not a big problem for capacitors greater than 100pF, but it can be if the capacitors are physically large enough. This occurs if the pads are physically large, or the dielectric (the circuit board material) is very thin. RF engineers strive to keep these capacitances small enough to not have much effect. Unfortunately, there are other parasitic elements formed by just the copper lines on the board. Any trace over a ground plane actually forms transmission lines and should be kept as short as possible.Revision 3.0 7/16/04Vias connecting through the board (to ground) will have a small amount of inductance which could be a problem for RF signals. RF signals require very good grounding. If an IC has numerous ground pins they should all be grounded separately (i.e. with their own vias) to minimize inductance. It is also possible for signals to crosstalk through common vias, so it is good practice to ground everything separately with multiple vias.2.2RF ComponentsSiRF has designed a family of GPS reference receivers using our preferred component vendors but new designers may choose to substitute non-critical parts. When doing this, the RF and parasitic performance of each component should be considered.Chip Resistors: Chip resistors have many parasitic elements, but in general the resistance of the resistor masks most of these effects. The most important RF characteristic of chip resistors is the series inductance due to its physical length. For 0603 and 0402 components at GPS frequencies this is usually not a serious problem. If (U.S. sized) 0402 or 0201 resistors are used, the designer MUST heed the thermal derating characteristics of this size part.Chip capacitors: The series inductance mentioned above for resistors is also the most important characteristic in capacitors which generally cannot be ignored. The capacitor and this inductance resonate at some frequency, and engineers have to be careful of this property. A 12 pF 0603 capacitor (with pads and trace inductance) can resonate at GPS frequencies, and this can be used to bypass power lines to stop the GPS signal from going where we don’t want it. It can also be used to block DC and pass GPS signals with no degradation. On the other hand a 0.1uF chip capacitor resonates at about 30 MHz and above resonance is quite inductive, so it will not bypass signals above 100 MHz very well and this is why it is not sufficient to use this as a bypass for GPS frequencies.Chip inductors: These are the most difficult components to model. Their main parasitic component is the parallel resonances formed by their inter-winding capacitance, capacitance to ground and their own inductance plus interconnect inductance. The parallel capacitance can vary widely from manufacturer to manufacturer, so if the inductor is used near its parallel resonance, it is important to ensure that any inductor from a new manufacturer is similar to the original, or properly characterized. Usually the only time this parallel resonance is used is to act as an RF open-circuit, while allowing DC to pass (such as in bias-T’s when it is needed to introduce DC into an RF cable). Inductors of the 0603 size and with a very small number of turns can cause wide variations in circuit performance, especially when different manufacturer’s inductors are compared. If the inductor is used in a matching network there may be large variations in RF performance depending on how the inductor is built, and how it is mounted.Revision 3.0 7/16/04High Q inductors (>50~60, if possible) should be used on the inputs of LNA’s. It is also important to minimize noise coupling into inductors by either shielding them or placing them as far away from the noise sources as possible. Placement of close proximity inductors at right angles will help to minimize adjacent coupling effects.2.3Gain, Stability and By-PassingToo much gain at RF frequencies is hard to control and can cause stability problems if not managed correctly. The GPS signal at 1575.42 MHz is hard to contain on all signal traces, even using a ground plane. Each of the components acts as small antennas that can talk to each other and cause amplifiers to oscillate. A general rule to control this is to keep gain stages at any one frequency below about 25 dB, and follow a straight path signal flow. Consult with our FAE team if this is not possible. It is highly recommended to place a shield over the circuitry to reduce undesired feedback and/or signal coupling and keep thermal air currents for the TCXO or crystal to a minimum. The SiRFstar typical reference design uses a single 15dB gain stage in front of the GRF3w and a single shield over the entire RF section. Proper matching of any pre or post filter is critical for successful, high volume performance. If new, small package SAW filters are considered for use, adding a row of vias (3 to 5) under the SAW filter between the input and output pins may help rejection performance. Contact the SAW manufacturer datasheet for more information.It is important to keep all RF signals and digital noise off the power lines. If RF signals get onto the power lines then circuits can oscillate, or mis-behave in other ways. Series resonant capacitors can be used to bypass the power, but they are only good at one frequency and therefore broadband bypassing techniques should be used. If it is necessary to stop more than one frequency it is possible to use 2 different capacitors (e.g.0.01uF and 100pF), but there is a drawback. Above the resonance of the large capacitor it will look inductive, while the smaller capacitor is still capacitive. This can form a parallel resonator that actually performs worse for certain frequencies between the two individual resonant frequencies. If it is sometimes possible to put a resistor, ferrite bead, or inductor between the two capacitors then it is possible to fashion a better bypass than that made with the two capacitors alone.Ferrite beads have very complicated equivalent circuits, so it is important to understand them before using them. There are many different types that act quite differently. The typical one used in the 0603 size is usually like a parallel resonant inductor, and becomes a resistive element at GPS frequencies. This can make for a fairly good element for a bypass network, when paired with suitable capacitors. There are currently a number of chip components available that look like a capacitor, but also have a grounded center pin. These are feed-through capacitors, and are very good for bypassing signals and minimizing RF coupling.Revision 3.0 7/16/042.4Crystal Oscillator RequirementsThe crystal oscillator needs to have virtually no noise on it for a high sensitivity GPS system and also have minimal variation over temperature. It is therefore critical that the crystal/TCXO be placed close to the oscillator IC and be isolated from noise-generating circuits. It should also be placed away from IC’s that dissipate a lot of power which can cause large temperature gradients at turn-on.Placing the TCXO a considerable distance away from the GRF3w chip requires well planned signal routing. Small quarts elements are very sensitive to temperature changes. Thermal isolation for this part should be an initial requirement for any new GPS design.In a GPS receiver, the system can track with crystal oscillators that vary smoothly over 10 to 15 parts per million (ppm) at stronger signal levels, but if the oscillator signal is jittering back and forth (even as little as 5 parts per billion), the receiver will have trouble. Therefore it is necessary to keep the oscillator as clean as possible. Short traces, and careful layout, keeping any signal, especially digital ones, away from the RF related circuitry, are important. The oscillator will also be prone to proximity and air current effects, such as waving your hand near it;therefore it should always be shielded! In addition, properly designing the oscillator mounting for vibration related effects should be addressed to avoid detrimental performance. Speakerphone behavior and the effect on the TCXO should also be addressed.2.5RF & Power Supplies in GeneralAnother source of noise is from the power supply. Ensure the supply is well bypassed for both low and high frequencies. The TCXO or oscillator generally needs a VERY LOW NOISE, linear-regulated supply voltage to function well enough in a GPS system. This implies a very high degree of ripple rejection out to 3MHz plus. The combination of a good linear regulator and good bypassing ensures that the oscillator supply is as clean as it can be. For bypassing, you only require one tantalum or ceramic capacitor as close to the regulator output as possible. Make certain the regulator is stable with the choice of capacitor used, and the resulting ESR. Additional capacitors will have little or no effect. Also, when routing the regulator output traces, the thicker the power trace from the regulator to the RFIC, the better the performance.The possibility of using a LOW EMI, higher efficiency switching power supply for the baseband receiver could be implemented, if reduced operating currents are desired. Use of a switcher well centered at 2MHz or 3MHz will most likely work better, but full characterization of this approach should be determined before any production designs are implemented. Each switching regulator has its own unique EMI characteristics. Proper shielding of the switcher is recommended for proper operation.Revision 3.0 7/16/043SiRF Receiver Layout Guidelines3.1PCB Fabrication RequirementsOn our S2AM reference designs we used a standard 4-layer, 0.062inch FR4 PCB with no special controlled-impedance requirements. This is possible if all RF routing is kept as short as possible, to avoid transmission line effects. When routing signals at 1575.42 MHz, if the track length must be longer than about 0.1inch, then its width should be chosen to implement a 50ohm microstrip transmission line. All other non-critical routing was with 5mil lines with 5mil spacing using 12mil diameter vias. Because RF performance can be sensitive to pad capacitance, the inner-layer dielectric spacing is critical and should adhere to the 8mil spec (between layers 1-2). If board size is critical then a new design should consider using a 6 to 8-layer board and possibly 0402 or 0201 chip components (although both of these may increase cost).With our SiRFstarIII reference designs, we used a 6-layer, 0.062inch FRF PCB. You can refer to the SiRF 1060-0122 and 0125 reference designs for further information on signal routing and hole sizes.Please note, that surface ground fill is also recommended, provided that the islands of fill are properly grounded with vias at each end of the islands. “Peppering” the surface ground fill plane with ground tie vias every ~0.1inch minimum is recommended. These fills, or “ground pours” will change the impedance of a standard 50 ohm microstrip transmission line. Consult with your PWB fabricator for estimated transmission line impedance changes due to neighboring ground pours.3.2Placement of ComponentsAs can be seen from our reference designs, the RF and digital sections are naturally separated. In our 4 layer designs, the RF section is completely shielded and no digital components (or routing) were placed beneath it. In our 6 layer designs, the RF section is on one side, while the digital is kept to the backside. We avoid routing noisy digital lines under our GPS and RTC clocks, as well as our RF loop filter lines. In fact, ACQCLK should have additional trace separation and ground isolation from other interconnect lines. With all of our reference designs, we attempt to keep the clock and data interfaces between the baseband and RF chip, short and straight. If you are required to route these lines around other components/traces, ensure that you change direction at 45 degree angles. Implementing long run CMOS clock and data lines with multiple direction changes can lead to low drive levels to the baseband as well as increase the chances of picking up noise. As an option, you may also want to consider placing a small resistor array (or individual resistors) in line with each CMOS interface for better noise immunity and test access. The actual resistor value utilized is somewhat dependent on the spacing between the RF and baseband and is typically 0 to 33 ohms for moderate distances of 2cm to 7cm max, and could be 0 ohms for very short distances (less than 1.5cm), but is not a preferred configuration. These resistors should be located as close as possible to theRevision 3.0 7/16/04output driving pin. Do not locate this resistor more than 0.5cm away from the GRF3w driving pins. Ideally, ~3mm is preferred. This is somewhat layout dependent, and may need adjustment after the first prototypes are evaluated.Use of a connector on the output of the GRF3w is risky, and should always be characterized before attempting this with a proposed design.NOTE: Elimination of the series resistor should mean the designer should allow for a short length of surface interconnect trace (<2mm) from the outputs of the RF chip before the trace is dropped to inner layer routing. This will allow for measurement access when troubleshooting is required.3.2.1Layer StackingWith respect to past SiRF 4 layer designs, we recommend the following:Note: For in-depth information, refer to the S2AM reference design, as well as Application Note #0021.Layer 1 is the component (i.e. top) side where SiRF places the baseband and flash memory (from the digital section) alongside the RF chip. The entire RF section is shielded with a small hole in the top to attach an RF cable.Layer 2 is the ground plane. It should be placed directly below the RF components for best isolation. SiRF uses a common ground plane for the digital and RF sections. We highly recommend that you do not split your ground planes. One common ground for the RF and digital should suffice.Layer 3 is a power plane with typically two different VCC voltages. The RF section runs on 2.85V while the digital circuits run mostly off of 3.3V. For upgrading to the SiRFstarIIeLP/2f, you may also require the addition of a 1.8V plane, but this can be avoided very easily. We do not recommend any other signal routing in this plane.Layer 4 is typically the solder side where additional memory and non-critical components are usually placed. No digital circuits should be placed under the RF section.With respect to previous SiRF 6 layer designs, we recommend the following:Layer 1 is the component (i.e. top) side where SiRF placed the entire RF circuitry, from the SiRF RF chip to the RF regulator. The entire RF section is shielded with a small hole in the top to attach an RF cable.Layer 2 is the ground plane. It should be placed directly below the RF components for best isolation and grounding performance. SiRF uses a common ground plane for theRevision 3.0 7/16/04digital and RF sections. We highly recommend that you do not split your ground planes. One common ground for the RF and digital should suffice.Layer 3 and 4 are inner signal routing. This area should be used for routing all digital signals which interface to memory, reset supervisor’s, etc. Do not route any RF signals in the inner layers because of higher interconnect loss effects.Layer 5 is a power plane with typically two different VCC voltages. The RF section runs on 2.85v while the digital circuits run mostly off of 3.3V. For upgrading to the SiRFstarIIeLP/2f, you may also require the addition of a 1.8V plane, but this can be avoided very easily. We do not recommend any other signal routing in this plane. Layer 6 is utilized as the baseband, memory and supporting circuitry layer. If feasible, try to avoid routing any digital components, or heat sources directly under the GPS crystal or TCXO.3.3 Routing IssuesWith proper component placement routing can usually be straight-forward. A few items to adhere to during routing are;•Keep all digital lines away from the RF section•Avoid routing between components (to prevent undesirable coupling)•RF routing longer than about 0.1inch should be 50ohm transmission lines•RF and bypass grounding should be direct to the ground plane through its own via Isolate the digital noise from the RF section by using separate power planes. This can be quite useful, but care must be taken in how the power and ground signals cross the gap between the two sections. For simplicity and reliability, we recommend using one uniform ground plane, assuming no additional digital noise from other sources is present. Multiple layouts may need to be addressed and evaluated if a considerable amount of additional digital noise is present.Usually all signal and power lines are bypassed as well as possible, and the ground is connected with a trace at a spot that has been shown to be optimum (usually near the edge of the board). In the case of the SiRF product, if you choose to split ground planes, you should connect them near the differential outputs of the RF chip. It can be quite tricky to accomplish this ground connection to satisfy all the operating conditions. Do not use an inductor or bead to connect the grounds, because when a cable is hooked up to the board a great deal of 60 Hz and other radiated signals appears across this inductor, and causes the RF section to be totally jammed by noise.If the board is going to be mounted in an enclosure, noise can radiate around the split and effectively cancel out the isolation. If the whole unit is going to be shielded this also cancels out the split because the shield has to connect to both the RF and digital groundsRevision 3.0 7/16/04to be effective. For most applications, SiRF has found that the most practical method of building a GPS receiver is to use the same ground for both the RF and digital sections, but to build a good shield around the RF section.Manufacturability should also be considered when placing and routing components. This includes trace width, trace spacing, component spacing, tooling holes, edge-clearances, testpoints, etc.3.4 High Density Layouts and Test Point AccessIn extremely dense layouts, test access should be planned for in advance and thought thru very carefully. If the goal is to make a very compact and miniature design, then SiRF recommends that OEMs proceed with a dual layout approach. One layout is for the desired compactness and size efficiency. A companion layout is designed and fabricated in parallel that is perhaps 50% larger in size, with slightly longer trace lengths, but accessibility to virtually all pins or nodes is made possible. Perhaps a high density logic analyzer connector is used for JTAG, enable, address and data line probing. If this is implemented, the interconnect stub to the connector should be <1cm, if possible. We urge that your team consider this approach, to assist in software debugging, and general HW debugging that may be required in the future. This approach can offer considerable time savings should any difficulties arise. If layout allows, implement as many test points as reasonably possible to assist in system debugging, should this be needed.4Antenna Placement ConsiderationsNext behind the TXCO in placement considerations, is the placement is the antenna. Every dB of antenna gain can translate into several dB worth of signal processing gain. Therefore, one of the best places to spend a little more time and effort on is the antenna. That it where the best value for your money spent will occur.If the design will allow for a ceramic RHCP patch antenna with an appropriately sized ground plane, and the patch is normally oriented towards the sky, then that particular solution usually works the best. Please note that if the patch antenna ground plane is less than 60x60mm, then compromises to the beam width and gain pattern could result. Usually the gain becomes very directional, and looses several dB of performance. Since results can vary, measuring the antenna radiation pattern in the final housing in an appropriate anechoic chamber will be required.Some customers do not have the size availability to implement a patch antenna approach. In that instance, use of a Linear Polarized (LP) antenna is the next best alternative. There are new ceramic LP antennas on the market that exhibit reasonable gain characteristics once properly mounted in the housing, and when mated to an appropriate sized ground. That is the key point to consider here. “When mated to an appropriate sized ground”.Revision 3.0 7/16/04Usually, the ground plane requirements are smaller for a LP antenna when compared to a patch, but once again, proper testing in an anechoic chamber is a mandatory requirement. These ceramic elements will need to be located near the end of the ground plane, and will require several mm of clearance between the closest component.It is important to note that use of a LP antenna will result in a minimum of 3dB of gain loss when compared to a RHCP antenna at a defined elevation. This is due to the right hand gain rule of antenna propagation.Use of PIFA antenna is another LP possibility, but the PIFA usually exhibits a considerable amount of gain nulls, or “holes” in the radiation pattern. This will be undesirable for obtaining a low circular error probability (CEP), since the antenna may not allow the receiver to capture the desired satellite at the ideal orientation due to these noted gain nulls.Once again, careful testing in an appropriate anechoic chamber is required.5Common Problems to AvoidThe most common reason for a GPS receiver not functioning (when first integrated), is because the receiver is jammed by digital noise or analog harmonics, usually in band. The receiver is so incredibly sensitive that harmonics of the digital signals are much larger than the signals being processed. It cannot be over-stressed too much that seemingly inconsequential design violations can cause digital noise to get into the front end and degrade system performance. Some mistakes that have caused problems in the past are: •Not designing the PCB with the required layer1-2 dielectric spacing.•Allowing the RF power plane to extend beyond the RF shield region.•Passing digital signals near the RF front-end via holes.•Passing un-bypassed power into the RF section.•Placing the IF filter inductors too close to noisy circuits.•Routing RF ground points using long traces.•Using alternate components which do not have the same RF or analog characteristics.•Improper or inadequate shielding.•Excessively long CMOS interface between the RF and BB•Not bypassing any digital outputs to the outside world with 12pF capacitors Therefore, it is the designers’ responsibility to keep unwanted interference out of the GPS passband, and at the band edges. Ideally and in general, keeping the spurious interference of a CW signal at levels below ~ -140dBm in a +/-6MHz BW (TBD) should eliminate the potential for any navigation related errors due to interference.。