L3- Embedded OS - ver.2009

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高质量DXT压缩使用CUDA技术（2009年）说明书

March 2009High Quality DXT Compression using OpenCL for CUDAIgnacio Castaño*******************Document Change HistoryVersion Date Responsible Reason for Change0.1 02/01/2007 Ignacio Castaño First draft0.2 19/03/2009 Timo Stich OpenCL versionAbstractDXT is a fixed ratio compression format designed for real-time hardware decompression of textures. While it’s also possible to encode DXT textures in real-time, the quality of the resulting images is far from the optimal. In this white paper we will overview a more expensivecompression algorithm that produces high quality results and we will see how to implement it using CUDA to obtain much higher performance than the equivalent CPU implementation.MotivationWith the increasing number of assets and texture size in recent games, the time required to process those assets is growing dramatically. DXT texture compression takes a large portion of this time. High quality DXT compression algorithms are very expensive and while there are faster alternatives [1][9], the resulting quality of those simplified methods is not very high. The brute force nature of these compression algorithms makes them suitable to be parallelized and adapted to the GPU. Cheaper compression algorithms have already been implemented [2] on the GPU using traditional GPGPU approaches. However, with the traditional GPGPU programming model it’s not possible to implement more complex algorithms where threads need to share data and synchronize.How Does It Work?In this paper we will see how to use CUDA to implement a high quality DXT1 texturecompression algorithm in parallel. The algorithm that we have chosen is the cluster fit algorithm as described by Simon Brown [3]. We will first provide a brief overview of the algorithm and then we will describe how did we parallelize and implement it in CUDA.DXT1 FormatDXT1 is a fixed ratio compression scheme that partitions the image into 4x4 blocks. Each block is encoded with two 16 bit colors in RGB 5-6-5 format and a 4x4 bitmap with 2 bits per pixel. Figure 1 shows the layout of the block.Figure 1. DXT1 block layoutThe block colors are reconstructed by interpolating one or two additional colors between the given ones and indexing these and the original colors with the bitmap bits. The number of interpolated colors is chosen depending on whether the value of ‘Color 0’ is lower or greater than ‘Color 1’.BitmapColorsThe total size of the block is 64 bits. That means that this scheme achieves a 6:1 compression ratio. For more details on the DXT1 format see the specification of the OpenGL S3TCextension [4].Cluster FitIn general, finding the best two points that minimize the error of a DXT encoded block is a highly discontinuous optimization problem. However, if we assume that the indices of the block are known the problem becomes a linear optimization problem instead: minimize the distance from each color of the block to the corresponding color of the palette.Unfortunately, the indices are not known in advance. We would have to test them all to find the best solution. Simon Brown [3] suggested pruning the search space by considering only the indices that preserve the order of the points along the least squares line.Doing that allows us to reduce the number of indices for which we have to optimize theendpoints. Simon Brown provided a library [5] that implements this algorithm. We use thislibrary as a reference to compare the correctness and performance of our CUDAimplementation.The next section goes over the implementation details.OpenCL ImplementationPartitioning the ProblemWe have chosen to use a single work group to compress each 4x4 color block. Work items that process a single block need to cooperate with each other, but DXT blocks are independent and do not need synchronization or communication. For this reason the number of workgroups is equal to the number of blocks in the image.We also parameterize the problem so that we can change the number of work items per block to determine what configuration provides better performance. For now, we will just say that the number of work items is N and later we will discuss what the best configuration is.During the first part of the algorithm, only 16 work items out of N are active. These work items start reading the input colors and loading them to local memory.Finding the best fit lineTo find a line that best approximates a set of points is a well known regression problem. The colors of the block form a cloud of points in 3D space. This can be solved by computing the largest eigenvector of the covariance matrix. This vector gives us the direction of the line.Each element of the covariance matrix is just the sum of the products of different colorcomponents. We implement these sums using parallel reductions.Once we have the covariance matrix we just need to compute its first eigenvector. We haven’t found an efficient way of doing this step in parallel. Instead, we use a very cheap sequential method that doesn’t add much to the overall execution time of the group.Since we only need the dominant eigenvector, we can compute it directly using the Power Method [6]. This method is an iterative method that returns the largest eigenvector and only requires a single matrix vector product per iteration. Our tests indicate that in most cases 8iterations are more than enough to obtain an accurate result.Once we have the direction of the best fit line we project the colors onto it and sort them along the line using brute force parallel sort. This is achieved by comparing all the elements against each other as follows:cmp[tid] = (values[0] < values[tid]);cmp[tid] += (values[1] < values[tid]);cmp[tid] += (values[2] < values[tid]);cmp[tid] += (values[3] < values[tid]);cmp[tid] += (values[4] < values[tid]);cmp[tid] += (values[5] < values[tid]);cmp[tid] += (values[6] < values[tid]);cmp[tid] += (values[7] < values[tid]);cmp[tid] += (values[8] < values[tid]);cmp[tid] += (values[9] < values[tid]);cmp[tid] += (values[10] < values[tid]);cmp[tid] += (values[11] < values[tid]);cmp[tid] += (values[12] < values[tid]);cmp[tid] += (values[13] < values[tid]);cmp[tid] += (values[14] < values[tid]);cmp[tid] += (values[15] < values[tid]);The result of this search is an index array that references the sorted values. However, this algorithm has a flaw, if two colors are equal or are projected to the same location of the line, the indices of these two colors will end up with the same value. We solve this problem comparing all the indices against each other and incrementing one of them if they are equal:if (tid > 0 && cmp[tid] == cmp[0]) ++cmp[tid];if (tid > 1 && cmp[tid] == cmp[1]) ++cmp[tid];if (tid > 2 && cmp[tid] == cmp[2]) ++cmp[tid];if (tid > 3 && cmp[tid] == cmp[3]) ++cmp[tid];if (tid > 4 && cmp[tid] == cmp[4]) ++cmp[tid];if (tid > 5 && cmp[tid] == cmp[5]) ++cmp[tid];if (tid > 6 && cmp[tid] == cmp[6]) ++cmp[tid];if (tid > 7 && cmp[tid] == cmp[7]) ++cmp[tid];if (tid > 8 && cmp[tid] == cmp[8]) ++cmp[tid];if (tid > 9 && cmp[tid] == cmp[9]) ++cmp[tid];if (tid > 10 && cmp[tid] == cmp[10]) ++cmp[tid];if (tid > 11 && cmp[tid] == cmp[11]) ++cmp[tid];if (tid > 12 && cmp[tid] == cmp[12]) ++cmp[tid];if (tid > 13 && cmp[tid] == cmp[13]) ++cmp[tid];if (tid > 14 && cmp[tid] == cmp[14]) ++cmp[tid];During all these steps only 16 work items are being used. For this reason, it’s not necessary to synchronize them. All computations are done in parallel and at the same time step, because 16 is less than the warp size on NVIDIA GPUs.Index evaluationAll the possible ways in which colors can be clustered while preserving the order on the line are known in advance and for each clustering there’s a corresponding index. For 4 clusters there are 975 indices that need to be tested, while for 3 clusters there are only 151. We pre-compute these indices and store them in global memory.We have to test all these indices and determine which one produces the lowest error. In general there are indices than work items. So, we partition the total number of indices by the number of work items and each work item loops over the set of indices assigned to it. It’s tempting to store the indices in constant memory, but since indices are used only once for each work group, and since each work item accesses a different element, coalesced global memory loads perform better than constant loads.Solving the Least Squares ProblemFor each index we have to solve an optimization problem. We have to find the two end points that produce the lowest error. For each input color we know what index it’s assigned to it, so we have 16 equations like this:i i i x b a =+βαWhere {}i i βα, are {}0,1, {}32,31, {}21,21, {}31,32 or {}1,0 depending on the index and the interpolation mode. We look for the colors a and b that minimize the least square error of these equations. The solution of that least squares problem is the following:∑∑⋅∑∑∑∑= −i i i i i ii i i i x x b a βαββαβαα122 Note: The matrix inverse is constant for each index set, but it’s cheaper to compute it everytime on the kernel than to load it from global memory. That’s not the case of the CPU implementation.Computing the ErrorOnce we have a potential solution we have to compute its error. However, colors aren’t stored with full precision in the DXT block, so we have to quantize them to 5-6-5 to estimate the error accurately. In addition to that, we also have to take in mind that the hardware expands thequantized color components to 8 bits replicating the highest bits on the lower part of the byte as follows:R = (R << 3) | (R >> 2); G = (G << 2) | (G >> 4); B = (B << 3) | (B >> 2);Converting the floating point colors to integers, clamping, bit expanding and converting them back to float can be time consuming. Instead of that, we clamp the color components, round the floats to integers and approximate the bit expansion using a multiplication. We found the factors that produce the lowest error using an offline optimization that minimized the average error.r = round(clamp(r,0.0f,1.0f) * 31.0f); g = round(clamp(g,0.0f,1.0f) * 63.0f); b = round(clamp(b,0.0f,1.0f) * 31.0f); r *= 0.03227752766457f; g *= 0.01583151765563f; b *= 0.03227752766457f;Our experiment show that in most cases the approximation produces the same solution as the accurate solution.Selecting the Best SolutionFinally, each work item has evaluated the error of a few indices and has a candidate solution.To determine which work item has the solution that produces the lowest error, we store the errors in local memory and use a parallel reduction to find the minimum. The winning work item writes the endpoints and indices of the DXT block back to global memory.Implementation DetailsThe source code is divided into the following files:•DXTCompression.cl: This file contains OpenCL implementation of the algorithm described here.•permutations.h: This file contains the code used to precompute the indices.dds.h: This file contains the DDS file header definition. PerformanceWe have measured the performance of the algorithm on different GPUs and CPUscompressing the standard Lena. The design of the algorithm makes it insensitive to the actual content of the image. So, the performance depends only on the size of the image.Figure 2. Standard picture used for our tests.As shown in Table 1, the GPU compressor is at least 10x faster than our best CPUimplementation. The version of the compressor that runs on the CPU uses a SSE2 optimized implementation of the cluster fit algorithm. This implementation pre-computes the factors that are necessary to solve the least squares problem, while the GPU implementation computes them on the fly. Without this CPU optimization the difference between the CPU and GPU version is even larger.Table 1. Performance ResultsImage TeslaC1060 Geforce8800 GTXIntel Core 2X6800AMD Athlon64 DualCore 4400Lena512x51283.35 ms 208.69 ms 563.0 ms 1,251.0 msWe also experimented with different number of work-items, and as indicated in Table 2 we found out that it performed better with the minimum number.Table 2. Number of Work Items64 128 25654.66 ms 86.39 ms 96.13 msThe reason why the algorithm runs faster with a low number of work items is because during the first and last sections of the code only a small subset of work items is active.A future improvement would be to reorganize the code to eliminate or minimize these stagesof the algorithm. This could be achieved by loading multiple color blocks and processing them in parallel inside of the same work group.ConclusionWe have shown how it is possible to use OpenCL to implement an existing CPU algorithm in parallel to run on the GPU, and obtain an order of magnitude performance improvement. We hope this will encourage developers to attempt to accelerate other computationally-intensive offline processing using the GPU.High Quality DXT Compression using CUDAMarch 2009 9References[1] “Real-Time DXT Compression”, J.M.P. van Waveren. /cd/ids/developer/asmo-na/eng/324337.htm[2] “Compressing Dynamically Generated Textures on the GPU”, Oskar Alexandersson, Christoffer Gurell, Tomas Akenine-Möller. http://graphics.cs.lth.se/research/papers/gputc2006/[3] “DXT Compression Techniques”, Simon Brown. /?article=dxt[4] “OpenGL S3TC extension spec”, Pat Brown. /registry/specs/EXT/texture_compression_s3tc.txt[5] “Squish – DXT Compression Library”, Simon Brown. /?code=squish[6] “Eigenvalues and Eigenvectors”, Dr. E. Garcia. /information-retrieval-tutorial/matrix-tutorial-3-eigenvalues-eigenvectors.html[7] “An Experimental Analysis of Parallel Sorting Algorithms”, Guy E. Blelloch, C. Greg Plaxton, Charles E. Leiserson, Stephen J. Smith /blelloch98experimental.html[8] “NVIDIA CUDA Compute Unified Device Architecture Programming Guide”.[9] NVIDIA OpenGL SDK 10 “Compress DXT” sample /SDK/10/opengl/samples.html#compress_DXTNVIDIA Corporation2701 San Tomas ExpresswaySanta Clara, CA 95050 NoticeALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, “MATERIALS”) ARE BEING PROVIDED “AS IS.” NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, OR OTHERWISE WITH RESPECT TO THE MATERIALS, AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT,MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE.Information furnished is believed to be accurate and reliable. However, NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or otherrights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of NVIDIA Corporation. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. NVIDIA Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of NVIDIA Corporation.TrademarksNVIDIA, the NVIDIA logo, GeForce, and NVIDIA Quadro are trademarks or registeredtrademarks of NVIDIA Corporation in the United States and other countries. Other company and product names may be trademarks of the respective companies with which they are associated. Copyright© 2009 NVIDIA Corporation. All rights reserved.。

博世安全系统-法拉登VIVIDIO应用程序步骤配置说明书

From Nuremberg BT-VS/MKP-XPT Product Management 20.04.2023Release LetterProduct: VIDEOJET decoder 7000 VJD-7513Version: Firmware 10.40.0055This letter contains latest information about the above-mentioned product.1. GeneralThis firmware release 10.40.0055 is a feature release based on FW 10.31.0005.Changes since last release FW 10.31.0005 are marked in blue.VIDEOJET decoder 7000 uses robust, fan-less technology designed for ambitious environmental conditions while providing maximum performance on minimum space in a nicely designed industrial housing.VIDEOJET decoder 7000 displays video from Standard Definition (SD), High Definition (HD), 4K Ultra High Definition (UHD), and Megapixel (MP) cameras and encoders using H.265, H.264 or MPEG-4 encoding at up to 60 frames per second over IP networks.VIDEOJET decoder 7000 is the successor of VIDEOJET decoder 8000 (VJD-8000, VJD-8000-N). It is using the same housing but comes with different video output interfaces and provides improved performance and functionality.Notes:•Firmware update may take several minutes due to a large cumulative Microsoft patch.•This firmware includes OpenSSL.From NurembergBT-VS/MKP-XPT Product Management 20.04.20232. Applicable products•VIDEOJET decoder 7000, VJD-75133. New Features•SRTP for encrypted multicast traffic is supported. This allows fully secured communication with and video streaming from CPP13 and CPP14 cameras in multicast environments.•SNMPv3 trap service has been added, including the support of SNMP-related RCP+ commands for configuration.• A JPEG snapshot is now possible from each of the displays, including JPEG quality settings parameter.•Display order can be re-arranged in case Windows display detection differs from mechanical order.•The default layout is depending on the display number to simplify the identification of display order. The number of video windows per display increases as square of the display number.•The web interface of the decoder has been updated to the latest style guide and re-structured to ease usage for installation, licensing, and integration purposes.o The new web pages provide links to documentation and include a live preview.o Maintenance log file creation and download is supported by a workflow mechanism.o A keyboard emulator supports initial setup for IP Matrix even without keyboard connected.From NurembergBT-VS/MKP-XPT Product Management 20.04.20234. Changes•The Video SDK as one of the core components for the decoder firmware has been updated to latest version 6.40, providing a great number of improvements and fixes, mainly aroundONVIF and RTSP support, increasing the overall robustness.•An issue is fixed for banner upload when banners are activated.•An issue is fixed for zooming out in client dewarping mode of panoramic camera streams.•An issue is fixed where client dewarping was not working on line 1 of a panoramic camera in onboard dewarping mode. Onboard dewarping is only available for lines 2 and higher, line 1 always provides the full warped image circle.•An issue with DNS server configuration is fixed.•An issue is fixed where CPP13 and CPP14 cameras were not correctly connected in camera sequences.•Maintenance log file download is improved, supported by the new web interface structure.•An issue is fixed where daylight saving time was incorrectly reflected in time zone offset calculation.5. System RequirementsFor configuration purposes:•Configuration Manager 7.61 or newerFor operation purposes:•Bosch Video Management System 12.0 or higherNote that not all features may be supported by BVMS yet.Please refer to BVMS release notes.From NurembergBT-VS/MKP-XPT Product Management 20.04.20236. Restrictions; Known Issues•Connecting encrypted streams without proper signalling may result in crashing the software decoder instance, resulting in black video displayed.•Alarms will not be signaled with a red border around the cameo if connection was established using CONNECT_PRIMITIVE.•Using CONNECT_PRIMITIVE via TCP is not possible.•CONNECT_PRIMITIVE does not support "first available" feature.•Audio may remain audible despite layout change to other than single view.•RCP+ command CONF_ALARM_CONNECT_TO_IP is not supported.•Alarm connection does not support audio, nor does it include metadata.•Maximum password length is 19 characters.•With “Reconnect last devices” active camera connections are stored and automatically reconnected after reboot. To avoid deadlock in case of an overload situation the automaticreconnect will be deactivated after the decoder was forced into reboot for ten times within 10 minutes.•Monitors may be swapped after update. Swap back is possible using Configuration Manager.•IP Matrix pre-requisites for multi-decoder clustering:o Fixed IP addresses must be assigned; DHCP configuration is not functional.o Passwords for service level must be same on all clustered decoders.o Passwords for user level must be same on all clustered decoders.•After removing a slave decoder from the IP Matrix master, both decoders must be restarted.•Camera sequences are paused when picture-in-picture mode is activated.•Time related settings may appear in Configuration Manager only with delay or after a reboot.•Monitors connected to the Display Port via USB-C may not always be detected during booting.In this case, unplug and reconnect the adapter or cable to the monitor. If only one monitor isused it is recommended to connect to the direct HDMI output.•Log file download stability may be affected by workload of decoder. As a workaround, the download may need to be repeated, or the workload of the decoder may need to be reduced (disconnect all camera streams).•Time zone configuration is only supported via TIME_ZONE_STRING.•The KBD-DIGITAL keyboard is locked automatically during start-up of the decoder, or with re-connect. It will be unlocked after entering the PIN but the lock screen will remain until the next action on the keyboard.•Certificates used with the decoder must not have any Windows policies defined.•DNS resolution is not implemented yet, thus time server entry only works with IP addresses.•Dewarping zoom does not work correctly for panoramic cameras in on-board dewarping mode for camera line 1.•Overload messages and traps may appear too sensitive in cases where display refresh rates are lower than video stream frame rates.From NurembergBT-VS/MKP-XPT Product Management 20.04.20237. Previous Revisions7.1. New Features with 10.31.0005•Support for HOST_NAME to get and set the device’s hostname; only supported in extended configuration mode.•Support for DNS_SERVER_IP_STRING to get and set primary and secondary DNS server IPv4 addresses.7.2. Changes with 10.31.0005•Optimized transparent data processing time to allow adequate transparent data pass-through for serial PTZ keyboard.•An issue is fixed to apply e-PTZ presets correctly in camera sequences.•Feature loss due to suppressing encrypted UDP multicast connections for Bosch IP cameras with firmware 8 and higher, and fall back to TCP, tunneled via HTTPS control connection.(This feature will be added again with FW 10.40.)From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.3. New Features with 10.30.0005•The default setting for Automatic IPv4 address assignment is set to “DHCP plus Link-Local”.Though this might seem a small change, it may have an impact:The former default IP address 192.168.0.200 will virtually become obsolete.Instead, the camera will assign itself an auto-IP address out of the range 169.254.1.0 to169.254.254.255 as long as there is no other IP address assigned by a DHCP server.(https:///wiki/Link-local_address)The advantage is that there are no more duplicate IP addresses, which is consideredprohibited in a network.•Network authentication 802.1x with EAP/TLS has been added.Please note that the server certificate needs to get the usages ‘Trust’ and ‘EAP_TLS_Trusted’ assigned.The client certificate will get the necessary usages assigned automatically.•The possibility of large banner overlays has been introduced.o Banners can be uploaded as images that can be displayed over three areas: top, center and bottom. The images are scaled to fill the area and cropped wherenecessary.o Banners can be sequenced with a configurable dwell time.o Configuration Manager 7.60 is supporting this with upload and banner sequence configuration, including banner previews.•Set and recall prepositions for moving cameras (AUTODOME, MIC) as well as for ONVIF PTZ cameras via keyboard has been added to the IP Matrix functionality.•Images can be uploaded to the decoder for two purposes, using Configuration Manager. The images shall be in JPG format and must be named as follows:o‘monitor background’ image, shown as background of an empty video window: ‘Logo.jpg’o‘’no camera’ image, shown on connection failure: ‘NoCamLogo.jpg’7.4. Changes with 10.30.0005•An issue was fixed where uploading a new video loss image did not break the software seal.From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.5. Changes with 10.23.0002• A security vulnerability has been fixed where a crafted configuration packet sent by an authenticated administrative user can be used to execute arbitrary commands in systemcontext (CVE-2021-23862).For more details refer to our Security Advisory BOSCH-SA-043434-BT, published at ourSecurity Advisory web pagehttps:///xc/en/support/product-security/security-advisories.htmlor visit our PSIRT website at https://.7.6. New Features with 10.22.0038•APIPA (link-local address, Auto-IP) is used instead of a default IP address when DHCP is on and no DHCP server responded.•Transparent data pass-through for serial PTZ keyboard (SERIAL_PORT_APP_VAL and TRANSFER_TRNSPARENT_DATA) has been added.•Support of RCP+ via CGI (including WRITE commands) has been added.•HTTP digest authentication is supported for RCP+ via CGI.•Display orientation can be changed per line via RCP+.•RCP+ WRITE command MONITOR_NAME now supported for custom monitor names.•Updated RCP+ documentation is now available via the VIDEOJET decoder webpage.•Download of screen and tile snapshots via snap.jpg is now supported (requires at least user privileges).•Firmware update on-screen countdown dialog now shows a heartbeat whenever a single update step takes longer.•Support of CONNECT_URL read queries to get current video connection details, including current digital and dewarping zoom settings, has been added.•Support of various digital and dewarping zoom persistence modes(DIGITAL_ZOOM_PERSISTENCE_MODE) has been added.•Support of SYSTEM_DATETIME_V2 to read/write UTC system time has been added.•Support for new Sentinel RMS licenses has been added. Legacy licenses can now also be based on new installation code (lock code from Sentinel RMS).From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.7. Changes with 10.22.0038•IP Matrix initialization is now working also for camera lines larger than 1.•RCP+ response for query on connected cameras is now working correctly.•URL extension for camera configuration in IP Matrix is no longer truncated.•An issue with an unexpected application restart has been fixed.•The DECODER_GROUP command is no longer supported when decoder IP address is not static. This disables the whole IP matrix configuration pages in Configuration Manager until a static IP is configured in the decoder’s network settings.•Improvements were made for log export via webpage and via Configuration Manager.•KBD-DIGITAL keyboard PIN is now used immediately without application restart.•KBD-DIGITAL keyboard PIN is now required whenever keyboard is attached and at application start.•Display orientation is now working for further monitor types.•Support of further USB to serial COM port adapters for KBD-DIGITAL keyboard connectivity.o Current: Prolific PL2303 [hardware ID USB\VID_067B&PID_2303]o New: Prolific PL2303GT [hardware ID USB\VID_067B&PID_23C3]o New: ATEN UC232A [hardware ID USB\VID_0557&PID_2008]o New: Unitek Y-108 [hardware ID FTDIBUS\VID_0403+PID_6001]o CableCreation CD0489 (PL2303) [hardware ID USB\VID_067B&PID_2303] is compatible to the already supported Prolific PL2303 adapter.Please note that the KBD-DIGITAL keyboard connectivity requires continuous maintenance, since new or not listed USB-to-serial COM port adapters typically require the installation of a suitable driver on the VIDEOJET decoder and an adaption of the hardware ID filter in thekeyboard detection software module. Newer USB adapters may require a firmware update to become supported.From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.8. New Features with 10.01.0036Security• A protected configuration mode has been implemented, allowing too enable SSD encryption (BitLocker) and too disable USB ports, e.g. for installation of the decoder in public areas.•The configuration of the decoder can be protected by Software Sealing, similar to IP cameras.•The latest Microsoft Windows security updates have been included.Miscellaneous• A dewarped cutout from panoramic cameras can be defined with PTZ coordinates.• A new way to control and integrate the decoder into a management system has been added by a JSON RPC API. This allows to send commands and retrieve status information via JSON remote procedure calls. The API documentation is added to the distribution package.• A video output capture service (VOCS) has been implemented which could be activated via a license, applicable per display output. This service captures the memory of the video outputand encodes it into a camera-like video stream, which can be recorded via Video StreamingGateway (VSG) onto iSCSI storage.• A time server can be added to synchronize the decoder.•Decoder log file can be downloaded via Configuration Manager. This is especially recommended when download of the log file is not working correctly via web browser.7.9. Changes with 10.01.0036•Upload of background image and connection loss image to the decoder and reverting them to default is now also possible with service password set. The former restriction is obsolete.•Various minor bug fixes.From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.10. New Features with 9.60.0017IP Matrix enhancements•KBD-DIGITAL is supported in addition to KBD-UNIVERSAL XF.This keyboard requires a serial-to-USB adapter to connect to the decoder.Both keyboards can be mixed in a clustered multi-decoder IP Matrix, one keyboard perdecoder.•Playback from local recording is supported.Permission is configured via Configuration Manager for the whole IP Matrix, valid for all users.•Buttons for next and previous camera have been added to the KBD-UXF functions.•Audio can be switched on or off via keyboard.•Camera channels can be extended via license up to 64 cameras per decoder unit.Note:IP Matrix manual is now separated intoo One configuration manual for IP Matrixo One operation manual for IP Matrix using KBD-UXFo One operation manual for IP Matrix using KBD-DIGITALSecurity•The latest Microsoft Windows security updates have been included.Miscellaneous•Background image and connection loss image can be uploaded to the decoder, replacing the default images. Reverting them to default is done by uploading an empty image.Note: Upload is only possible in conjunction with an empty service password.7.11. Changes with 9.60.0017•Temperature control margin increased to improve maximum performance at the specified maximum temperature, covering component tolerances, and to ensure that all productsadhere fully to their specification.•Various minor bug fixes.Security SystemsFromNuremberg BT-VS/MKP-XPT Product Management 20.04.202311BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany 7.12. Features with initial release 9.51• VIDEOJET decoder 7000 displays video from Standard Definition (SD), High Definition (HD),4K Ultra High Definition (UHD), and Megapixel (MP) cameras and encoders using H.264 or MPEG -4 encoding at up to 60 frames per second over IP networks.• VIDEOJET decoder 7000 provides an HDMI and a DisplayPort (via USB-C connector) output, both capable of driving up to 4K UHD displays simultaneously.• Display settings are automatically discovered and set for optimal display performance. • Monitor layouts can be switched independently for each display.• Upright monitors (portrait mode) are supported.• Video window (cameo) aspect ratio can be set to 16:9, 9:16, 3:4, or 1:1.• Active camera connections and layout are stored and automatically reconnected after reboot if configured. To avoid deadlock in case of an overload situation the automatic reconnect will be deactivated after VIDEOJET decoder 7000 was forced into reboot for 3 times within 10 minutes.• Video smoothing can be configured.• RTSP connections are supported, enabling connectivity to 3rd party and ONVIF cameras. • Discovery port is configurable.• Cameo distance is configurable.• VIDEOJET decoder 7000 supports IP Matrix application as built-in feature.• VIDEOJET decoder 7000 is able to display VCA metadata.• VIDEOJET decoder 7000 provides bi-directional G.711 audio for the video stream shown in single view on the first monitor.• Configuration is done using the Configuration Manager.• The number of decoders presented in capabilities is configurable to regulate the consumption of VMS licenses. Default value is 30.• System access is password-protected with two levels.• The system firmware can be upgraded remotely.• System API is compatible to predecessor VIDEOJET decoder 8000 for easy plug-and-play integration.• Operating temperature iso 0 °C to +50 °C (+32 °F to +122 °F) ambient temperature, with airflow o 0 °C to +40 °C (+32 °F to +104 °F) ambient temperature, still airFor detailed functional description of inherited firmware features, please refer to the VIDEOJET decoder 8000 firmware 9.51 release notes.For detailed technical specification, please refer to the datasheet.。

Data Protector软件(解决方案、产品配置及注意事项)

HP Data Protector software:
HP Business Copy & Continuous Access
HP EVA and XP Disk Arrays
Disk-to-disk backup
(VTL, disk) HP Data Protector software:
Advanced Backup to Disk Virtual Tape Libraries (VTL) Disk Arrays
Windows（32/64 位）（Intel EM64T，AMD x64） HP-UX (HP-UX 11.31) Solaris Linux SuSE、Red Hat（Xeon64、AMD64）
磁盘代理
• • • • • • • • • • • • • • • •
11
介质代理
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重要
4 2009年6月23日星期二
如今保持业务连续运转的动力
以消费者版本的价格获得企业版本的功能
5
2009年6月23日星期二
HP Data Protector 软件的样板客户已逾 22,000 家...这一数字仍在不断增加
Teves AG
6
2009年6月23日星期二
B6963AA
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L3Harris 智能集成 C4ISR 系统部署指南说明书

6 Steps to Fielding Smart, Integrated C4ISR SystemsL3Harris TechnologiesTHIS INFORMATION IS NOT EXPORT CONTROLLED THIS INFORMATIONIS APPROVED FOR RELEASE WITHOUT EXPORT RESTRICTIONS INACCORDANCE WITH A REVIEW OF THE INTERNATIONAL TRAFFIC INTABLE OF CONTENTS Executive summary (3)Start with your end goal in mind (4)Design for ease-of-use and rapid deployment (5)Beware of introducing information overload (6)Build on your existing systems as you add new capabilities (7)Plan for post-acquisition training, support and maintenance (8)Demand a focus on sovereignty (9)6 Steps to Fielding Smart, Integrated C4ISR Systems EXECUTIVE SUMMARYPutting the necessary assets and infrastructure in place to create a real-time, multi-echelon Common Operational Picture (COP) is the desire of most militaries. But fielding these smart, integrated, cognitive systems can become overly complicated, costly and time-consuming—hindering their effective implementation in the short term and over time.Your ability to overcome the complexities, timelines and cost challenges associated with C4ISR system integration—and to ensure the integration is sustainable over time—is closely tied to the partner you choose to work with. Having a partner that serves as a trusted advisor with the experience and willingness to put your needs first (selling capability instead of products) is a critical success factor.L3Harris is the established leader in developing and deploying customized, integratedC4ISR systems and the infrastructure needed to gather, synthesize and share a diverse range of battlefield reconnaissance data. Our long history of being there “in field” with our customers through times of peace and conflict positions us to recommend solutions that help the world’s militaries put intelligence into action. Success can be fast-tracked, deploying pre-configured packages available for quick delivery as building blocks to an otherwise complex, bespoke system implementation.Here are the top 6 pre-purchase steps that should be considered when developing and implementing an integrated C4ISR system:1. Start with your end goal in mind2. Design for ease-of-use and rapid deployment3. Beware of introducing information overload4. Build on your existing systems as you add new capabilities5. Plan for post-acquisition training, support and maintenance6. Demand a focus on sovereignty1. Start with your end goal in mindOUR OBSERVATION: Choose a partner with direct access to the necessary technologies and proven experience in developing and deploying integrated military command systems. The best partner will understand and anticipate the specific needs of each user group from headquarters to the front line. Ensure your partner can demonstrate their understanding of how users will be impacted by the result, as well as the journey during implementation. That partner should play an advisory role throughout the process, helping you to:•Understand how you are operating today likely differs from what you will be doing tomorrow. It’s not enough to simply update systems. Commanders must understand and articulate the benefits of increased C4ISR awareness well before delivery so that new doctrine can be written, and end users can be trained prior to fielding. Following this type of implementation strategy will greatly reduce the time it takes to get from delivery to improved, real-time tactical decision making.•U se focused terms for what you’re trying to achiev e. It may not need to be a nationwide C4- or C5ISR system. The scale and scope of your migration should be based on your actual needs today—and not become overcomplicated by extra capabilities you may not use.•Develop specific, measurable goals and objectives for each stage of the project. The overall objective is to get the right information to the right personat the right time to enhance decision making. Plan a number of steps in yourdevelopment. New capabilities, delivered incrementally, allow for short-termsuccesses in pursuit of the greater goal.•Count on your partner to develop a vision that delivers on your specific measurable goals and objectives. You are purchasing experience, labor and services as much as technologies and equipment. Your partner should show how they plan to help you ensure forward and backward interoperability and avoid“analysis paralysis” by solving today’s mission while leaving room for futuregrowth and adaptation.L3Harris is ideally suited to guide you on your journey, given our decadesof experience in the international systems market, demonstrated customer relationships, in-country partnerships (175+) and reputation as cutting-edge integrators. This combination of reputation and knowledge drives us to have the right conversations with the right people—and to solve today’s mission challenges while planning for the requirements for future adaptation. Along with our position as a world leader in waveform development and fielding, we bring valuable real-life experiences to the implementation of C4 Battle Management Systems (BMS) and related solutions.2. Design for ease-of-use and rapid deploymentOUR OBSERVATION: Systems must be designed with your current end user’s capabilities in mind. The easier a system is to use, and the faster it can be deployed, the more likely it is to be adopted and implemented to its full potential. Highly effective system designs:•Understand that a soldier’s user experience is key to both the adoption and effectiveness of a given solution. The goal is to free up users so they can spend more time on valuable situational analysis and less on figuring out how to use agiven system.•Take an iterative approach. Start with what you have (tactical radios, for example) and build from there so new capabilities can be fielded quickly and more easily.Teach users how to adopt new technologies in iterative content blocks to avoidoverwhelming them all at once.•Include a cadence of new capability “quick wins.” Incremental successes will demonstrate a measurable return on investment to stakeholders up and down the command chain. They will also help to keep your users engaged in the development, design and delivery process, while building consensus regarding next stepsduring fielding.•Stay focused on the need. Since new program phases are often budget-driven, put your resources into what is most critical for sovereign protection, rather thanadditional advanced features you may not be ready for, or able to implement totheir full potential.L3Harris takes the user experience seriously, and our 50 years in the field—combined with a workforce comprising 15% ex-military personnel—havehoned our understanding of how technologies are used in the real worldunder high-stress conditions. This extends even to small details, like how easyit is to operate a radio while wearing gloves, or how a piece of technology with extraneous light or sounds could inadvertently reveal locations at night.3. Beware of introducing information overloadOUR OBSERVATION: Relying on an ever-increasing number of battlefield sensors presents a significant challenge: how to process all the data collected by each sensor and deliver relevant situational understanding in real time to aid in decision making. Collecting the information from tens to hundreds of sensors in the field creates more information than the human mind can interpret; therefore, an effective system must provide some information processing and simplification:•Identify who needs what data, when. It will no longer be possible for everyone to know everything. Data will be delivered at different need and classification levels so that various decision makers will only receive what they need, when they need it. •Understand that Artificial Intelligence (AI) is not just hype, it is a requirement.Data collection, analysis and target identification need to be implemented in-fieldtoday. As your partner, we will help identify what data should be processed where, how it can be automated, when human input is necessary or desired, and whereto use each tool. For example, a warfighter engaged in combat often can’t readdetailed environmental information in real time. By presenting the data graphically using visualization tools, the same information becomes instantly actionable in atime-critical decision-making process.•To design for project success, start small and build gradually.Don’t change or replace everything at once. It’s better to make incremental changes to data collection and processing that will help users adapt and adopt more easily.L3Harris will implement systems that deliver relevant information to each operational role using machine learning and AI to control information overload and keep warfighters laser-focused on their tasks.4. Build on your existing systems as youadd new capabilitiesOUR OBSERVATION: Many vendors are more proprietary than they admit. Inevitably, lack of interoperability (or imperfect interoperability) can result in missed data—and even missed targets. True interoperability requires proactive effort on the part of the integrator. Although the industry claims to operate on an “open systems” architecture, the reality is that many aren’t there yet. Proactive, effective integrators will continually:•Invest in developing two-way, responsive relationships. Look for a partner witha record of industry collaboration and th e ability to leverage relationships to get whatthey need from other suppliers.•Take your own buying habits into account. Many purchasers buy for a specific mission, program, or end user, resulting in splintered acquisitions over time. Consider an evolving procurement approach with a focus on long-term program sustainability rather than a “big bang” single-need or one-off purchase.•Develop a phased plan that ensures each program investment solves both immediate problems and longer-term goals. Don’t sacrifice the future for a“right now” solution.•Steer away from partners who force a single-system approach, and who will hold you hostage to their products for future interoperability. You need to be able to plug new capabilities into your C4ISR solution—and they won’t necessarily come from the same vendor. Stressing the use of open standards eases this problem. L3Harris is relentlessly focused on open architecture and open systems.Our industry relationships and integration experience, along with our commitment to understanding and solving the specific challenges faced by our customers, translateto robust solutions and the ability to deliver advanced capabilities today without limiting the possibilities for tomorrow.5. Plan for post-acquisition training, support,and maintenanceOUR OBSERVATION: Purchasers often don’t consider the ongoing trainingand maintenance requirements—and costs—for the systems they buy. It’sup to us to be your partner and help ensure you plan accordingly and to the appropriate budget levels:• A system that lacks proper training/maintenance funding will not be used or usable. Plan for up to 15%–20% ongoing costs above and beyond the initial system investment.•Understand the emerging battlefield environment and develop new concepts of operation, as well as determine how these approaches will impactperformance. In a sense, your partner will need to understand the big picture as well as or better than you do, given duty rotations and other operationalrealities. They should provide a level of continuity to help maintain their corporate knowledge—and your institutional knowledge—as personnel come and go.L3Harris is known for industry-leading post-delivery support and sustainment packages tailored to specific customer needs. We offer a wide range of services, such as installation, maintenance support, sovereign maintenance capability, training, and in-field customer support. Every system, whether turnkey or custom-built, is delivered with detailed user documentation as well as maintenance schedules.6. Demand a focus on sovereigntyOUR OBSERVATION: This is only possible when a partner has an absolute commitment to their customers’ sovereignty—and is willing to make investments to support and develop local workforces in every region in which they operate. Having a sovereign-focused mindset will ensure you can:•Work with your partner to source labor and materials locally. For example, rather than ship shelters from an out-of-country vendor, find the shelters locally, fit them out locally, and you’ll be creating a trained workforce rather than simply importing finished products.•Plan for local delivery of training, service and maintenance over a period of time. This will help to create local jobs and build the local economy.•Identify a partner that uses local relationships that can be leveraged throughout the planning and implementation process, including thedevelopment of specific technologies that can further local capabilities.L3Harris is committed to local partnering and has a long history of partnershipin the countries we serve. This is a core element of our business process atL3Harris, and one of the reasons we are able to achieve such close customer relationships. For example, in Australia, L3Harris has created opportunitiesfor over 500 full-time local employees and fostered ongoing technology innovation. Formoreinformation,contactJakeWilliams(**************************).。

Windows Embedded Standard 2009 安装篇

[图文] Windows Embedded Standard 2009 安装篇[日期：2009-08-18] 来源：作者：宣震[字体：大中小]Windows Embedded Standard（WES）是Windows XP Embedded（就是很有名的XPE，相信大家都听说过或者使用过）的下一代产品，由WES Build 出来的XP 镜像（Runtime Image）是Windows XP SP3 版本。

WES 和XPE 相比较有如下优势：(1) 包含Microsoft Silverlight(2) 包含 .NET Framework 3.5(3) 支持Windows Vista 和Windows Server 2008 的新技术，主要是指RDP v6.1(4) 包含Windows Media Player 11(5) 包含Internet Explorer 7(6) 支持Windows Server Update Services (WSUS)(7) 支持System Center Configuration Manager(8) 包含MBSA (Microsoft Baseline Security Analyzer)(9)新平台技术和特性的迁移，主要是指Windows 7 和Windows Server 2008 R2下面我们就来看看WES2009 的安装过程：1）首先准备好一台安装有 Windows XP 或者Windows Server 2003 系统的计算机（虽然MS 说Windows Vista 和Windows Server 2008 也可以安装，但建议安装在Windows XP 或者Windows Server 2003 系统中）2) 加载下载好的WES2009 镜像，进行安装，我们来看看正式安装前的准备：WES2009 的运行需要SQL Server 2005 的支持，推荐安装SQL Server 2005 标准版或者企业版。

金雕雷达说明书2009-ver2

BERKUT （金雕）雷达测速仪说明书俄罗斯奥利维亚公司20091 成套性和构造说明BERKUT型/金雕型雷达测速仪成套性如下表测速仪为一种雷达设备，其工作原理为雷达所发射的高频信号从处于在其作用范围内的移动目标反射时改变频率值（多普勒效应）。

测速仪的构造包括高频发生器、用于信号接受和处理的微处理器单元，以上单元置于同一个牢固的外壳里面。

外壳表面上压有出厂序列号，仪器名称，制造商标牌和和计量器具认证号。

测速仪外壳上有专用封条，拆下该封条会导致该封条的破坏。

封条上有保护罩，避免偶然性的破坏。

雷达测速仪 (雷达头)测速仪没有控制或显示部件，设计配合外部设备仪器使用（手柄，支架）。

与外部设备的连接通过通讯接口进行。

数据交换用RS 232标准接口.测速仪按照外部设备发出的命令进行车速的检测。

检测完毕之后测速仪把检测结果发送至外部设备。

测速仪具备自检模式和数据交换测试模式。

图1.BERKUT金雕雷达测速仪手柄模式交警使用测速仪时，握着其手柄。

手柄上有测速仪控制组件，测速显示，供电。

手柄包括测速通讯接口，控制键盘，图像显示屏（屏幕有加热功能，低温时自动启动），蓄电池和充电器。

手柄有供电具有手腕带。

.蓄电池蓄电池在雷达手柄的蓄电池室舱内，为手柄和雷达头工作供电，可使用手柄供电线缆进行充电。

手柄供电电缆手柄供电电缆为绞合线，总长为5 – 7 m, 具有接通手柄的插座以及接通点火器或充电器的插座。

电缆内设有保护器和正负电极错误接通保护装置。

充电器充电器利用民用供电网对蓄电池进行充电。

支架模式支架用于变压稳压电源，以及传输串口通讯信号。

支架配套的供电和RS232综合电缆其中有电源连接线和串口通讯连接线（RS232）2 主要技术指标∙测速仪在平直路段上对俄产日古里牌小客车的作用距离应不小于400m 。

测速仪有分档调整作用距离功能；∙测速仪按不同车速对车辆进行识别时，要求车速相差在3km/h以上；∙测速仪按不同反射信号强度对车辆进行识别时，要求反射信号强度在1:10以上；.∙测速仪具有自动识别监控目标车所行使方向功能；∙测速仪有静态和动态测速模式。

L3 通信系统 - 西部 (CSW) 的电子电路卡组装工艺标准说明书

Circuit Card Assembly Workmanship Standard – Level I Document Number: WS-020Revision: 05 Effective Date: 9/12/2023 Point of Contact: Mike MalloryTitle: Technical ExpertTABLE OF CONTENTSPURPOSE & SCOPE (1)WORKMANSHIP STANDARD (1)1.CONNECTOR CONTACTS – BRUSH TYPE (1)2.EXPENDABLE FEATURES (5)3.SMPM (SUB MINIATURE PUSH-ON MINIATURE) CONNECTOR ACCEPTABILITY CRITERIA (8)4.PRESSFIT CONNECTOR CONTACTS (9)RECORDS (10)DOCUMENT INFORMATION (11)PURPOSE & SCOPEThis Workmanship Standard supplements the IPC-A-610 Acceptability of Electronic Assemblies and/or other specified documents. It provides requirements and acceptance criteria applicable to the assembly of circuit cards that are not currently addressed in IPC-A-610 (in some cases may be outside its’ scope) or may be unique to L3 Communication Systems - West (CSW) products or processes.WORKMANSHIP STANDARD1.CONNECTOR CONTACTS – BRUSH TYPE1.1.Brush ContactsThis section describes the acceptance criteria necessary to inspect connectors with brush contacts after the connectors are assembled in the end application. The contacts illustrated are made up of seven (7)gold plated wires (bristles) 0.007 inches in diameter. The brush contact is either sleeved or non-sleeved depending on the connector type. These bristles are supported and crimped into a holder. The holder has the termination tail attached to it. There are various tail types; compliant pin, PC through-hole andsurface mount are common types. The only difference in the mating interfaces of the contact types is the sleeved contact has the addition of a stainless-steel sleeve.Discoloration (patina) of the brush (bristles) wire tips is an acceptable Condition. This condition is nothing out of the ordinary that will affect performance. The seven (7) brush wires are cut/cleaved prior toassembly into the main contact body therefore exposing the base alloy BeCu. By mil-spec, the brush wire tips need not be plated (Ref. MIL-DTL-55302/166 thru 170). Due to the self-cleaning ability of the brush contact and multiple points of electrical engagement there will be no effect on reliable performancethrough environments.Warning:Severe Damage can result if a brush contact is mated (probed) with anything other than a special brush contact probe or a mating brush contact.The figure below identifies the component parts of typical brush contacts. The top contact illustrates atypical sleeved contact with a compliant tail and the bottom contact illustrates un-sleeved contact with a through-hole tail.Note: All photos in this document are examples and intended to provide visual directive and are not specific to any part or program.1. Sleeve (Brush inside)2. Holder3. Compliant Tail4. Contract Brush5. Holder6. Through-Hole Tail1.2.Brush Contacts – Sleeved – Sleeve Damage1.2.1.Target•Sleeve (1) not damaged•Sleeve•Imaginary Circle•Wire (bristle) Diameter1.2.2.Defect•Sleeve is nicked, chipped, or marred.•Sleeve is bent or smashed.1.3.Brush Contacts – Sleeved – (Bristle) Positioning1.3.1.Target•Brush contact is approximately centered in the contact sleeve.•Bristles of the brush are not bent splayed or crushed.•Bristles of the brush are within the imaginary circle located one wire diameter from the inner sleeve wall.1.3.2.Acceptable•Four (4) bristles are within the imaginary circle, located one wire diameter from the inner sleeve wall.•The other three (3) bristles may be located anywhere else within the sleeve but may not contact the inner sleeve wall.1.3.3.Defect•Poor bristle centering, more than three (3) wires are located closer that one (1) bristle to the sleeve inner wall.•Any bristle in contact with the sleeve inner wall.1.4.Brush Contacts – Un-sleeved – (Bristle) – Positioning1.4.1.Target•Brush contact is approximately centered in the cavity opening (not shown).•Bristles of the brush are not bent, splayed, or crushed.•Bristles of the brush are within the imaginary circle located one bristle diameter from the inner cavity wall.1. Cavity Hole2. Imaginary Circle3. Wire Brush Diameter1.4.2.Acceptable•Brush not centered in cavity.•Bristles are splayed (separated) but are no closer than one bristle diameter to the inner cavity wall.1. Cavity Hole2. Imaginary Circle3. Wire Brush DiameterNote: Bristles closer than one bristle diameter to the cavity wall may cause damage to the mating sleeve or contact brush.1.4.3.Defect•Poor bristle centering, any bristle that is closer than one bristle diameter to the inner cavity wall.•Any bristle in contact with the inner cavity wall.1.5.Brush Contacts – (Bristle) End DamageNote: Criteria apply to both sleeved and un-sleeved brush contacts.1.5.1.Target•No damage to bristle ends.•No damage to pins, exposing base metal.1.5.2.Defect•Blunt or burred bristle end.•Damage to pins exposing base metal.2.EXPENDABLE FEATURESThis section addresses certain features found on components and PCBs, printed circuit boards that serve a purpose prior to, or during CCA, circuit card assembly build and or test but have little value once thecomponent is installed or the CCA has passed functional testing.When fit, function and reliability are not impacted, the feature is deemed expendable and as such its absence is not a defect.Note: all photos in this section are examples and intended to provide visual directive and are not specific to any part or program.ponents•Components may have features that aid or enhance storage and handling, including automated placement equipment. However, these features once the component is installed on a CCA have littleor no usefulness. In fact, they become a detriment if they are missing as this may appear as a defectreceiving attention and rework labor that is not required.•Other components not specifically addressed in this section having similar type features or characteristics may be considered expendable after installation on the CCA.2.2.PCBs•PCBs may have additional circuitry or pads designed to facilitate RF, radio frequency tuning. These pieces of circuitry sometimes referred to as “confetti” are used to tune RF circuits but are oftenunused or have material soldered to them only to be later removed during the tuning process. Giventhe size and bond strength between these small pieces of circuitry and the dielectric material,(laminate) they can be easily lifted from the PCB surface when heated or stressed. At times a CCAwith these missing pieces of circuitry can still be tuned and function properly. When this is the caseand the CCA has passed functional test, the absence of this circuitry is not considered a defect.•BGA, Ball Grid Array sites may have nonfunctional, unsupported/unconnected pads. These pads serve as a point for solder attach for the nonfunctional or otherwise not used solder balls on the BGA.Since these pads are not connected to any circuit traces or via holes they can easily lift from thelaminate if the BGA is replaced as part of a rework process. When some of these nonfunctional pads become lifted it shall not be considered a defect.ponent Expendable Features Pick and Place Aids2.3.1.Target – General•Covers and housing on components that facilitate pick and place equipment are securely fastened to the component and exhibit no cracks or missing pieces.2.3.2.Acceptable – Pick and Place Covers Completely Missing•After solder attachment of the component, the cover or housing is completely missing with no residual materials left on the CCA and no damage to the component body, core, or windings,etc.•Adhesives, if used to secure the cover are missing completely or are securely bonded to the component or PCB surface.2.3.3.Acceptable – Pick and Place Cover Partially Missing•After solder attachment to the PCB, the cover or housing is partially missing but the remainingportion is firmly attached to the component with no residual materials left on the CCA and nodamage to the component body, core, or windings, etc.•Cover or housing may or may not be bonded to the PCB surface.2.3.4. Defect•Loose cover or partially attached cover. • Cover debris left on the CCA.• Component or PCB surface damage beyond limits (Ref WS-002).2.4. PCB Expendable Features RF Tuning Circuitry2.4.1. Target•RF tuning circuitry (confetti) is attached to the PCB dielectric. • No loose or missing circuitry.2.4.2. Acceptable•Pieces of RF tuning circuitry (confetti) are missing. •No PCB surface damage beyond limits (Ref WS-002). •No loose pieces of RF tuning circuitry (confetti) present on the PCB. • The CCA is properly tuned and passes test.2.4.3. Defect•Damage to base laminate beyond limits (Ref WS-002). •Loose piece(s) of RF tuning circuitry (confetti) present on the PCB. • Regardless of CCA is properly tuned and passes test.2.5.PCB Expendable Features Nonfunctional BGA Pads2.5.1.Target•All nonfunctional BGA pads are attached to the PCB.2.5.2.Acceptable•Nonfunctional BGA pads are lifted.•Lifted nonfunctional BGA pada do not exceed 10% of the total BGA pad count.•PCB surface damage is not beyond limits (Ref WS-002).•No loose pad material present.2.5.3.Defect•Damage to base laminate beyond limits (Ref WS-002).•Functional BGA pads lifted.•Lifted nonfunctional BGA pads exceed 10% of the total BGA pad count.•Loose piece(s) of BGA pads present on the PCB (not shown).3.SMPM (SUB MINIATURE PUSH-ON MINIATURE) CONNECTOR ACCEPTABILITY CRITERIA3.1.Purpose and Scope: This section describes the acceptance criteria for SMPM (Sub Miniature Push-onMiniature). (May also be known as GPPO® or SSMP® connectors, example part number: 40012161-000 & 40011782-000.) SMPM interface defined in MIL-STD-348, GPPO® is a registered trademark of Corning(Gilbert) and SSMP® is a registered Trademark of Carlisle (Tensolite).3.2.Magnification: SMPMs shall be inspected at the appropriate magnification for the wire size of the SMPM’spin (see IPC-610 Table 1-3 or IPC/WHMA-A-620 Table 1-1).3.3.Product Features/Conditions:Knit Lines (also known as weld lines/meld lines) can occur during the manufacturing of these connectors depending on the manufacturing method used.3.3.1.Acceptable (see Figure 1)• Knit line is visible but does not have a gap.• Center contact is fully restrained.Figure 1: Acceptable Knit Line Example3.3.2.Defect•Knit line has a gap.•Center contact is not being held in place (is not concentric or titled at an angle) due to a knit line gap.3.4.FOd (Foreign Object Debris)3.4.1.Acceptable•Dielectric burr is attached (see Figure 2).•Burr does not interfere with the electrical ground path (see Figure 2 for an example of this type of burr, the electrical ground path is shown in red in Figure 3).3.4.2.Defect•Dielectric burr is loose/not attached.•Burr is in/interferes with the electrical ground path (the electrical ground path is shown in red in Figure 3).Figure 2: Dielectric Burr Figure 3 Electrical Ground path (shown in red)4.PRESSFIT CONNECTOR CONTACTS4.1.Pressfit Ground ContactsThis section describes the acceptance criteria necessary to inspect pressfit connectors with groundcontacts after the connectors are installed onto the PCB. The pressfit connector ground contacts contain a bend to allow for a spring effect. This bend is susceptible to damage through handling or processing ofthe CCA or during test where mating connectors are installed for functional evaluation.Minimal to light damage to these ground contacts is an acceptable condition . These conditions provide full contact to the mating connector.Note : All photos in this document are examples and intended to provide visual directive and are not specific to any part or program.4.1.1. Target•No damage to the ground contacts of pressfit connectors4.1.2. Acceptable•Slight to moderate bending of the ground contact •Allows for mating at test/NHA4.1.3. Process Indicator• Contact is moderately bent.4.1.4. Defect• Severe or extreme damage to the ground contact likely causing damage at test/NHA.RECORDSThere are no records associated with this document. END OF DOCUMENTWS-020, Rev. 05 – Page 11 of 11 Printed versions of this document are considered obsolete. DOCUMENT INFORMATIONResponsible Organization:Operations Function/Sub-function:Workmanship Standards Governing Document(s):IPC-A-610, Acceptability of Electronic Assemblies Subordinate Document(s):J-STD-001, Requirements for Soldered Electrical; and Electronic Assembly Related Document(s): IS-003, Workmanship Acceptability of Electronic Assemblies P-047, Inspection WS-000, Workmanship Standards Introduction WS-002, IPC-A-610 Acceptance of Electronic AssembliesRelated Training: N/AApproval Requirements: Associate Manager, Manufacturing EngineeringReview Requirements:Supervisor, Quality Management Associate Manager, Mechanical Engineering Revision History Summary Revision # Description of Change Date New Initial release. (20.1 replaces QB-153) 05/26/2011 01 Added a paragraph to 20.1.1, allowing discoloration (patina) to the brush wire ends. 02/09/2015 NA Added records section. No revision upgrade necessary. 03/16/2017 NAReformatted in accordance with new template format. Update L3 naming throughout. No revision upgrade necessary. 05/23/2017 02Added expendable features section. Reformatted by adding links to various sections instead of defining criteria in this document. 12/05/2018 03 Added new section 4.3, Material Military Interface. 04/05/2021 04 Incorporated subsections (separate files) into this single document. Removed reference to wire (bristle) ends illustrations from second paragraph in section 1.1. 11/10/2022 05Added section 4, accept/reject criteria for pressfit connector ground contacts. 9/12/2023。

Intel 64和IA-32架构软件开发人员手册第三卷(3A,3B,3C和3D) 系统编程指南说明书

Intel® 64 and IA-32 ArchitecturesSoftware Developer’s ManualVolume 3 (3A, 3B, 3C & 3D):System Programming GuideNOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of four volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-Z, Order Number 325383; System Programming Guide, Order Number 325384; Model-Specific Registers, Order Number 335592. Refer to all four volumes when evaluating your design needs.Order Number: 325384-065USDecember 2017Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at , or from the OEM or retailer.No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses.You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifica-tions. Current characterized errata are available on request.This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmapsCopies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or by visiting /design/literature.htm.Intel, the Intel logo, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries.*Other names and brands may be claimed as the property of others.Copyright © 1997-2017, Intel Corporation. All Rights Reserved.CONTENTSPAGECHAPTER 1ABOUT THIS MANUAL1.1INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3NOTATIONAL CONVENTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.1Bit and Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.2Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.3.3Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.3.4Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.3.5Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.3.6Syntax for CPUID, CR, and MSR Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.3.7Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4RELATED LITERATURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10CHAPTER 2SYSTEM ARCHITECTURE OVERVIEW2.1OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1Global and Local Descriptor Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.1.1Global and Local Descriptor Tables in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.2System Segments, Segment Descriptors, and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.2.1Gates in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.3Task-State Segments and Task Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.3.1Task-State Segments in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.4Interrupt and Exception Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.4.1Interrupt and Exception Handling IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.5Memory Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.5.1Memory Management in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.6System Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.6.1System Registers in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.1.7Other System Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2MODES OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.1Extended Feature Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.1System Flags and Fields in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 2.4MEMORY-MANAGEMENT REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.4.1Global Descriptor Table Register (GDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 2.4.2Local Descriptor Table Register (LDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 2.4.3IDTR Interrupt Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 2.4.4Task Register (TR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13 2.5CONTROL REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.5.1CPUID Qualification of Control Register Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19 2.6EXTENDED CONTROL REGISTERS (INCLUDING XCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.7PROTECTION KEY RIGHTS REGISTER (PKRU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.8SYSTEM INSTRUCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.8.1Loading and Storing System Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23 2.8.2Verifying of Access Privileges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23 2.8.3Loading and Storing Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-24 2.8.4Invalidating Caches and TLBs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-24 2.8.5Controlling the Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-25 2.8.6Reading Performance-Monitoring and Time-Stamp Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-25 2.8.6.1Reading Counters in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26 2.8.7Reading and Writing Model-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26 2.8.7.1Reading and Writing Model-Specific Registers in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26 2.8.8Enabling Processor Extended States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26Vol. 3A iiiCONTENTSiv Vol. 3A PAGECHAPTER 3PROTECTED-MODE MEMORY MANAGEMENT3.1MEMORY MANAGEMENT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2USING SEGMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.1Basic Flat Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.2Protected Flat Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.3Multi-Segment Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.4Segmentation in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.5Paging and Segmentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3PHYSICAL ADDRESS SPACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.3.1Intel® 64 Processors and Physical Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4LOGICAL AND LINEAR ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1Logical Address Translation in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2Segment Selectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.3Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.4Segment Loading Instructions in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.5Segment Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.5.1Code- and Data-Segment Descriptor Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 3.5SYSTEM DESCRIPTOR TYPES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.5.1Segment Descriptor Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14 3.5.2Segment Descriptor Tables in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16CHAPTER 4PAGING4.1PAGING MODES AND CONTROL BITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1Three Paging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2Paging-Mode Enabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.1.3Paging-Mode Modifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.4Enumeration of Paging Features by CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.332-BIT PAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4PAE PAGING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.4.1PDPTE Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13 4.4.2Linear-Address Translation with PAE Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14 4.54-LEVEL PAGING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.6ACCESS RIGHTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4.6.1Determination of Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29 4.6.2Protection Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-31 4.7PAGE-FAULT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.8ACCESSED AND DIRTY FLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 4.9PAGING AND MEMORY TYPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4.9.1Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium II Processors). . . . . . . . . . . . . .4-34 4.9.2Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent Processor Families). . . . . . . . . .4-34 4.9.3Caching Paging-Related Information about Memory Typing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-35 4.10CACHING TRANSLATION INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 4.10.1Process-Context Identifiers (PCIDs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-35 4.10.2Translation Lookaside Buffers (TLBs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-36 4.10.2.1Page Numbers, Page Frames, and Page Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-36 4.10.2.2Caching Translations in TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-37 4.10.2.3Details of TLB Use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-37 4.10.2.4Global Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-38 4.10.3Paging-Structure Caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-38 4.10.3.1Caches for Paging Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-38 4.10.3.2Using the Paging-Structure Caches to Translate Linear Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-40 4.10.3.3Multiple Cached Entries for a Single Paging-Structure Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-41 4.10.4Invalidation of TLBs and Paging-Structure Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-41 4.10.4.1Operations that Invalidate TLBs and Paging-Structure Caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-41 4.10.4.2Recommended Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-43 4.10.4.3Optional Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-44 4.10.4.4Delayed Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-45 4.10.5Propagation of Paging-Structure Changes to Multiple Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-46 4.11INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (VMX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 4.11.1VMX Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-47CONTENTSPAGE 4.11.2VMX Support for Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-474.12USING PAGING FOR VIRTUAL MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 4.13MAPPING SEGMENTS TO PAGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48CHAPTER 5PROTECTION5.1ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2FIELDS AND FLAGS USED FOR SEGMENT-LEVEL ANDPAGE-LEVEL PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1Code-Segment Descriptor in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3LIMIT CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3.1Limit Checking in 64-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4TYPE CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.1Null Segment Selector Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.4.1.1NULL Segment Checking in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.5PRIVILEGE LEVELS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.6PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.6.1Accessing Data in Code Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.7PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.8PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS . . . . . . . . . . . . . . . . 5-10 5.8.1Direct Calls or Jumps to Code Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.8.1.1Accessing Nonconforming Code Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.8.1.2Accessing Conforming Code Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.8.2Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.8.3Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.8.3.1IA-32e Mode Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.8.4Accessing a Code Segment Through a Call Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.8.5Stack Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.8.5.1Stack Switching in 64-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.8.6Returning from a Called Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.8.7Performing Fast Calls to System Procedures with theSYSENTER and SYSEXIT Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.8.7.1SYSENTER and SYSEXIT Instructions in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.8.8Fast System Calls in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.9PRIVILEGED INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.10POINTER VALIDATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.10.1Checking Access Rights (LAR Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.10.2Checking Read/Write Rights (VERR and VERW Instructions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.10.3Checking That the Pointer Offset Is Within Limits (LSL Instruction). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.10.4Checking Caller Access Privileges (ARPL Instruction). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.10.5Checking Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.11PAGE-LEVEL PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.11.1Page-Protection Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.11.2Restricting Addressable Domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.11.3Page Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.11.4Combining Protection of Both Levels of Page Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.11.5Overrides to Page Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.12COMBINING PAGE AND SEGMENT PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.13PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.13.1Detecting and Enabling the Execute-Disable Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.13.2Execute-Disable Page Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.13.3Reserved Bit Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.13.4Exception Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32CHAPTER 6INTERRUPT AND EXCEPTION HANDLING6.1INTERRUPT AND EXCEPTION OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2EXCEPTION AND INTERRUPT VECTORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.3SOURCES OF INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.3.1External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.3.2Maskable Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3.3Software-Generated Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4Vol. 3A v。

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Embedded System Software Development
Windows CE（2）

主要模块

内核模块：支持进程和线程处理及内存管理等基本服务内核系统调用接口模块：运行应用程序访问操作系统提供的服务文件系统模块：支持dos，fat等格式的文件系统图形窗口和事件子系统模块：控制图形显示，并提供windows GUI界面通信模块：运行同其他设备进行信息交换
Slide 26
Embedded System Software Development
VxWorks的评价

Vxworks是一款非常出色的嵌入式实时操作系统，但是它是不公开源码的商业化操作系统，价格比较高为追求系统的实时性而设计的，并不是以通用OS为设计目标。

去掉了一些OS模块，因为这些模块在某种程度上会影响系统的实时性（如在内存管理中没有采用页面管理模式，采用的是平板式内存）。
Embedded System Software Development

内核是针对实时系统的要求来设计实现的，相对比较简单，可以满足较高的实时性要求但是没有网络功能和文件系统，对于像媒体播放、需要网络和图形界面支持的应用就比较差
Slide 13
Embedded System Software Development
Slide 28
Embedded System Software Development

资源共享和优先级继承机制采用最优化的上下文切换和中断返回机制. 内核从不禁止非屏蔽中断 NMI (non-maskable interrupts)
Slide 29
Embedded System Software Development
可调度性

实时任务具有时限要求，调度实时任务时，需要判断是否每个任务的执行都能够在其截止期限内完成。如果每个任务的执行都能够在其截止期限内完成，则称该调度是可行的可调度性判定(或称调度可行性判定)就是判定给定的n 个实时任务在应用某种调度算法的前提下能否产生一个可行的调度。调度算法的设计要尽可能满足任务可调度性的要求
Embedded System Software Development

虚拟内存模块VxVMI： VxVMI主要用于对指定内存区的保护，如内存块只读等共享内存模块VxMP：主要用于多处理器行运行任务之间的共享信号量、消息队列、内存块管理板级支持包BSP：提供各种硬件的初始化、中断的建立、定时器、内存映象
VxWorks缺点

缺少某些OS特性保证时限要求是设计者自己的任务(系统的灵活性带来的弊端) 不支持很多应用和APIs(只支持部分POSIX标准的函数集) 尽管采用了平板式内存管理，但是由于内存的动态分配，仍然存在内存段，这样仍然存在时间上的不可预测性
Slide 30
Embedded System Software Development
• 移动控件
笔记本PC
• 复杂的文档编辑和读写 • 桌面键盘输入
• 键盘和鼠标输入法 • 完整的.NET framework 支持
Windows CE
Slide 17
Windows Mobile
Embedded System Software Development
Windows XP/XPE
常见嵌入式非实时操作系统

Microsoft公司的windows CE、Embedded windows xp Palm公司的Palm OS symbian公司的EPOC 一些嵌入式linux系统
几款典型的嵌入式操作系统介绍

uC/OS II ThreadX Windows系列的嵌入式操作系统 VxWorks 嵌入式Linux
微软的移动平台
Pocket PC
• 信息消费 • 浏览和输入数据 • 把电话融入PDA
• 可以与Office, 信息消费 Exchange和SQL Server交互基本数据浏览把PDA融入电话 • .NET Compact Framework 可以与Exchange • 移动控件交互 • .NET Compact Framework
Slide 5
Embedded System Software Development
强负载下的稳定性

实时稳定性随着系统的负载有所不同当系统的负载变得很大时，如果系统不能保证所有任务的时间要求，应当能使其中一部分关键任务始终满足时限要求
Slide 6
Embedded System Software Development

I/O处理系统： Vxworks提供与ANSIC兼容的I/O处理系统，主要包括

UNIX缓冲I/O处理系统，和面向实时的异步I/O处理系统

本机文件系统网络处理模块： Vxworks网络处理模块能与许多运行其他协议的网络进行通信，如TCP/IP、NFS、UDP、SNMP、FTP等
Slide 25
uC/OS II

免费的公开源码实时操作系统内核提供任务调度和管理、时钟管理、任务间同步与通信、内存管理和中断服务等功能最多支持64个任务，分别对应优先级0～63，其中0为最高优先级可剥夺实时多任务内核调度工作的内容分为两部分：最高优先级任务的寻找和任务切换
Slide 12

应用领域主要局限在对实时性要求较严格的硬实时系统中带给用户最大的控制权的同时，用户对系统的实时性调度责任也更大
Slide 31
Embedded System Software Development
Tornado —— 集成开发环境
Slide 32
Embedded System Software Development
Slide 20
Embedded System Software Development
几款典型的嵌入式操作系统介绍

uC/OS II ThreadX Windows系列的嵌入式操作系统 VxWorks 嵌入式Linux
Slide 21
Embedded System Software Development
Emedded Operating Systems
Zhang Chunkai, HITSZ, ckzhang@ Embedded System Software Development
嵌入式操作系统分类

硬实时系统

确保系统中的关键任务在确定的时间得到响应，不能有失败的情况，否则会出现严重后果设计的时候是有响应时间要求的，但是偶尔某些任务的响应时间超过这个限制也不会有严重的后果无响应时间的要求
VxWorks

Vxworks的基本构成模块包括以下部分：

高效实时微内核wind： Vxworks实时微内核wind以灵活性和可配置性为设计目标，它主要包括

基于优先级的任务调度任务同步和通信中断处理定时器内存管理

兼容POSIX实时系统标准
Slide 24
Embedded System Software Development
Slide 15
Embedded System Software Development
几款典型的嵌入式操作系统介绍

uC/OS II ThreadX Windows系列的嵌入式操作系统 VxWorks 嵌入式Linux
Slide 16
Embedded System Software Development
VxWorks嵌入式实时操作系统

VxWorks 是风河（WindRiver）公司开发的一款商用硬实时操作系统支持主流的32位CPU，包括

x86、 68K、PowerPC、MIPS、ARM等
基于微内核结构，由400多个相对独立的，短小精悍的目标模块组成，可裁剪性和可配置性相当出色
Slide 22

软实时系统

非实时系统

Slide 2
Embedded System Software Development
实时系统的几个指标

预测反应时间可调度性强负载下的稳定性
Slide 3
Embedded System Software Development
预测反应时间

在工业控制系统中，实时可定义为系统对某事件响应时间的可预测性。一个事件发生后，系统须在一个可准确预见的时间范围内作出反应。
嵌入式操作系统一览
Slide 7
Embedded System Software Development
常见嵌入式实时操作系统

RTlinux及其他嵌入式实时Linux uC/OS II wind river systems公司的Vxworks QNX software systems公司的QNX。 pSOS OS/9

uC/OS II ThreadX Windows系列的嵌入式操作系统 VxWorks 嵌入式Linux
Slide 14
Embedded System Software Development
ThreadX操作系统

只需要很小的存储器容量（最低5k）硬实时的处理能力有功能强大的专门的开发调试支持工具支持了市场上绝大部分的CPU 同样也是商业化的操作系统
• • • •
Smartphone
平板电脑