信号完整性研发测试攻略2.0
信号完整性测试
信号完整性测试硬件电路测试中非常重要的一项是信号完整性测试，特别是对于高速信号，信号完整性测试尤为关键。
完整性的测试手段种类繁多，有频域，也有时域的，还有一些综合性的手段，比如误码测试。
不管是哪一种测试手段，都存在这样那样的局限性，它们都只是针对某些特定的场景或者应用而使用。
只有选择合适测试方法，才可以更好地评估产品特性。
本文将讲解常用的一些测试方法和使用的仪器。
一、波形测试使用示波器进行波形测试，这是信号完整性测试中最常用的评估方法。
主要测试波形幅度、边沿和毛刺等，通过测试波形的参数，可以看出幅度、边沿时间等是否满足器件接口电平的要求，有没有存在信号毛刺等。
波形测试也要遵循一些要求，比如选择合适的示波器、测试探头以及制作好测试附件，才能够得到准确的信号。
下图是DDR在不同端接电阻下的波形。
常见的示波器厂商有是德科技、泰克、力科、罗德与施瓦茨、鼎阳等等。
二、时序测试现在器件的工作速率越来越快，时序容限越来越小，时序问题导致产品不稳定是非常常见的，因此时序测试是非常必要的。
一般，信号的时序测试是测量建立时间和保持时间，也有的时候测试不同信号网络之间的偏移，或者测量不同电源网络的上电时序。
测试时序基本都是采用的示波器测试，通常需要至少两通道的示波器和两个示波器探头（或者同轴线缆）。
下图是测量的就是保持时间：三、眼图测试眼图测试是常用的测试手段，特别是对于有规范要求的接口，比如USB、Ethernet、PCIE、HDMI和光接口等。
测试眼图的设备主要是实时示波器或者采样示波器。
一般在示波器中配合以眼图模板就可以判断设计是否满足具体总线的要求。
下图是示波器测试的一个眼图：四、抖动测试抖动测试现在越来越受到重视，常见的都是采用示波器上的软件进行抖动测试，如是德科技示波器上的EZJIT。
通过软件处理，分离出各个分量，比如总体抖动（TJ）、随机抖动（RJ）和固有抖动（DJ）以及固有抖动中的各个分量。
对于这种测试，选择的示波器，长存储和高速采样是必要条件，比如2M以上的存储器，20GSa/s的采样速率。
信号完整性常用的三种测试方法
信号完整性常用的三种测试方法信号完整性是指在传输过程中信号能够保持原始形态和准确性的程度。
在现代高速通信和数字系统中，信号完整性测试是非常重要的工作，它能够帮助工程师评估信号的稳定性、确定系统的极限速率并发现信号失真的原因。
下面将介绍三种常用的信号完整性测试方法。
一、时域方法时域方法是信号完整性测试中最常见和最直观的方法之一、它通过观察信号在时间轴上的波形变化来评估信号的完整性。
时域方法可以检测和分析许多类型的信号失真，如峰值抖动、时钟漂移、时钟分布、幅度失真等。
时域方法的测试设备通常包括示波器和时域反射仪。
示波器可以显示信号的波形和振幅，通过观察波形的形状和幅度变化来判断信号完整性。
时域反射仪可以测量信号在传输线上的反射程度，从而评估传输线的特性阻抗和匹配度。
二、频域方法频域方法是另一种常用的信号完整性测试方法。
它通过将信号转换为频域表示，分析信号的频谱分布和频率响应来评估信号完整性。
频域方法可以检测和分析信号的频谱泄漏、频谱扩展、频率失真等。
频域方法的测试设备通常包括频谱分析仪和网络分析仪。
频谱分析仪可以显示信号的频谱图和功率谱密度，通过观察频谱的形状和峰值来评估信号完整性。
网络分析仪可以测量信号在不同频率下的响应和传输损耗，从而评估传输线的频率响应和衰减特性。
三、眼图方法眼图方法是一种特殊的信号完整性测试方法，它通过综合时域和频域信息来评估信号的完整性。
眼图是一种二维显示，用于观察信号在传输过程中的失真情况。
眼图可以提供信号的时钟抖动、峰值抖动、眼宽、眼深、眼高等指标。
眼图方法的测试设备通常包括高速数字示波器和信号发生器。
高速数字示波器可以捕捉信号的多个周期，并将其叠加在一起形成眼图。
通过观察眼图的形状和特征，工程师可以评估信号的稳定性和传输质量。
总结起来，时域方法、频域方法和眼图方法是常用的信号完整性测试方法。
它们各自具有独特的优势和适用范围，可以互相协作来全面评估信号的完整性。
在实际应用中，根据具体需求和测试对象的特点，选择合适的测试方法是非常重要的。
信号质量测试资料
产生 原因 解决 建议
匹配不当（例如匹配阻抗过大、过小）。 更改为合适的匹配电阻/阻抗。
回勾（台阶）
类型 上升沿回勾 振铃
图例
危害
1）主要是时钟类信号上的回勾有危害，可能会使得采样到多余的数据（相当于多 了一拍时钟），影响了时钟信号上升沿和下降沿的单调性； 2）对于电源信号，上电边沿的回勾可能导致系统死机，需要结合复位信号判断是 否可以接受； 3）数据信号由于一般是在数据的中间采样，回勾的影响不是很大（除非速率很高， 建立保持时间1～2ns，这时需要考虑回勾对数据的影响）。
延）。探头和示波器的带宽要超过信号带宽的3~5倍以上；
示波器选择与使用要求：
4)示波器的采样速率：表示为样点数每秒（S/s），指数字示波器
对信号采样的频率。为了准确再现信号，根据香农（Shannon）定
律，示波器的采样速率至少需为信号最高频率成分的2倍； 5)量程应尽量小，波形尽量展开，以方便观察波形变化的细节， 并准确测量其幅值； 6)测量信号边沿时，应选用合适的边沿触发；
保持时间不够，读写数据处理过程中同 样可能读写到错误数据
产生 原因 解决 建议
设计时没有考虑清楚，设计出错。或者没有考虑到设计容限范围，在某些异常情 况下（例如温度变化使得器件参数漂移）建立、保持时间不够。 1、设计时把时钟从FPGA/CPLD中引出，在设计裕度不够时可以调节； 2、对于时钟边沿采样信号，尽量使得采样时钟边沿在数据的中间，这样尽管器件 参数漂移，设计上还是有较大的裕度。
信号质量测试人员要求：
1)熟悉逻辑电平的基本知识，熟练掌握示波器的使用方法； 2)对被测单板的原理电路有深刻认识，对信号分类有清楚 认识，了解板上器件的工作速度和工作电平。
示波器选择与使用要求：
(完整word版)信号完整性研发测试攻略2.0
信号完整性测试指导书——Ver 2.0编写：黄如俭（sam Huang）钱媛（Tracy Qian）宋明全（Ivan Song）康钦山（Scott Kang）目录1. CLK Test (4)1.1 Differential Signal Test (4)1.2 Single Signal Test (7)2. LPC Test (8)2.1 EC Side Test (8)2.2 Control Sidse Test (9)3. USB Test (12)3.1 High Speed Test (12)3.2 Low Speed Test (13)3.3 Full Speed Test (13)3.4 Drop/Droop Test (14)4. VGA Test (16)4.1 R、G、B Signal Test (16)4.2 RGB Channel to Channel Skew Test (17)4.3 VSYNC and HSYNC Test (17)4.4 DDC_DATA and DDC_CKL Test (18)5. LVDS Test (19)5.1 Differential data signals swing Test (19)5.2 Checking Skew at receiver Test (20)5.3 Checking the offset voltage Test (21)5.4 Differential Input Voltage Test (23)5.5 Common Mode Voltage Test (24)5.6 Slew Rate Test (25)5.7 Data to Clock Timing Test (27)6. FSB Test (30)7. Serial Data（SATA/ESATA, PCIE, DMI,FDI）Test (33)8. HD Audio Test (35)8.1 Measurement at The Controller (35)8.2 Measurement at The Codec (36)9. DDR2 Test (39)9.1 Clock (39)9.2 Write (40)9.3 Read (42)10.Ethernet Test (44)11.SMbus Signal Test (45)12. HDMI Test (47)13. DisplayPort Test (48)1. CLK Test1.1 Differential Signal Test测试设备：示波器，两个差分探头，鼠标，键盘测试软件：3D MARK，负载测试步骤：（1）开启示波器预热30分钟，运行测试软件。
安捷伦信号完整性测试全面解决方案_zh
安捷伦信号完整性测试 高速数字线缆 和 PCB 全面解决方案 的应用
安捷伦科技中国有限公司 电子测试部
高育财 应用工程师
Friday, March 02, 2012
1
课程目的
• 市场发展趋势和使用 E5071C 对高速串行无源互联器件进行测试的应用 • 使用网络分析进行测试的原理 • 使用网络分析仪012/3/16
TDR 示波器测量结果和矢量网络分析仪测量结果的比较
使用 TDR 示波器和矢量网络分析仪对 USB 3.0 测试夹具进行阶 跃响应测试结果的比较
1.10E+02
Impedance [Ohm]
1.00E+02
9.00E+01
8.00E+01
VNA Oscilloscope
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ENA-C TDR 2012/3/16
测试高速无源互联器件/电缆的单台仪表解决方案 E5071C 和时域测量软件 TDR
得到行业官方认可的测量 USB 3.0/DisplayPort/HDMI1.4 电缆的仪表
注: 在 2009 年 12 月，E5071C 被 HDMI 标准组织推荐为进行频域测量的唯一的 矢量网络分析仪
矢量网络分析仪 的测量速度比
TDR 快 200 倍！
使用矢量网络分析仪进行测试，显示的是实时的测量结果!
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ENA-C TDR 2012/3/16
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3/16/2012
Agilent E5071C Option TDR
Agilent ENA Series Network Analyzer
E5071C ENA option TDR
与 TDR 相比，矢量网络分析仪 的测试动态范围要高出 60dB
信号完整性的三种测试方法
广播百科停机 如何解决忨距离网络传输？汶两种方式爵有效 广播百科001 — 100期 广播百科101 — 200期 广电术语词汇（ 一 ） 广电术语词旷（二）
信号完整性的测试手段主要 可以分为三大类，下面对这些手段进行一些说明。
1. 抖动测试
抖动测试现在越来越受到重视，因为专用的抖动测试仪器，比如TIA(时间间隔分析仪） 、 SIA3000, 价格非常昂贵，使用得比较少。 使用得最多是示波器加上软件处理，如TEK的 TDSJIT3软件。 通过软件处理，分离出各个分量，比如RJ和DJ I 以及DJ中的各个分量。 对 千这种测试，选择的示波器，长存储和高速采样是必要条件，比如2M以上的存储器， 20GSa/s 的采样速率。 不过 目前抖动测试，各个公司的解决方案得到结果还有相当差异， 还没有哪个是权威或者行业标准。
利用分析软件，可以对眼图中的违规详细清况进行查看，比如在MASK中落入了—些采样 点，在以前是不知道哪些情况下落入的，因为所有的采样点是累加进去的，总的效果看起来 就象是长余晖显示。 而新的仪器，利用了其长存储的优势，将波形采集进来后进行处理显 示，因此波形的每 一 个细节都可以保留，因此它可以查看波形的违规清况，比如波形是 000010还是101010, 这个功能可以帮助硬件工程师查找问题的根源所在。
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USB2.0信号测试指导
USB 2.0 Compliance Testing with Agilent Infiniium OscilloscopesApplication Note 1400Who Should Read This Application Note?Digital designers and developers working towards USB 2.0 compliance.IntroductionUniversal Serial Bus (USB) burst on the scene in 1995 delivering a revolutionary way to connect personal computers and devices. Allowing hot-plug capability, USB has introduced ease-of-use to the PC device market by providing a simple connection scheme and protocol for a wide variety of computer devices, ranging from keyboards and mice to high-bandwidth devices such as printers, scanners, and cameras.USB has now successfullyreplaced aging serial and parallel ports as the connection of choice for both device manufacturers and end users. Whereas cable length and device expansionwere limitations with older serial and parallel connections, they are no issue for USB. Amazingly,it allows devices to exist up to 30-meters away from the host, and allows up to 127 devices to be connected to a single host and port at once through a series of USB hubs. The ability to talk directly to devices or to devices through hubs allows for this incredible expansion B 1.1 worked best for slower human-interface devices such as mice and keyboards, with low-speed operating at 1.5-Mb/s and full-speed operating at12-Mb/s. Higher-bandwidth devic-es were severely limited by these relatively slow data transfer rates. As a result, the USB-Implementers Forum (USB-IF) introduced the fully backward compatible USB 2.0 in May 2000, which resulted in a 40-fold increase in datathroughput for hi-speed over full-speed. USB 2.0 operates at 480-Mb/s—ideal for devices such as video-conferencing cameras and high-resolution printers. For more information, see the official USB-IF (USB Interoperability Forum) website at .Basic SpecificationsAs listed previously, USB 2.0 comprises three different data transfer rates—low-speed,full-speed, and hi-speed.Four wires compose the cable system—V BUS, D+, D-, and ground. Devices may be either bus-powered, with 500-mA maximum bus current withdraw, or self-powered, meaning they have their own power supply.D- and D+ is a differential signal pair that serves as the primary information carrier between the host, hubs, and devices. USB 2.0 supports three different types of data transfer: interrupt, bulk, or isochronous. Control packets containing commands or query parameters may also be sent by the host.The flexibility inherent in USB is a direct result of the specifica-tions above and the stringent regulations and compliance testing mandated by the USB-IF. There are three kinds of compliance tests: framework test,interoperability test, and electri-cal test. This document onlydiscusses Infiniium’s electricaltest solution.Low, full, and hi-speed USBrequire compliance with thesignal quality, in-rush currentcheck, droop/drop and backdrive voltage electrical tests. Hi-speed requires compliance withan additional suite ofelectrical tests—hi-speed sig-nal quality, receiver sensitivity,CHIRP timing, and packetparameters. Older methods ofcompliance testing included firstcapturing the signals on a scope,then moving the data to a PC so itcould be cropped, stored in a .tsvformat, and finally analyzed inMATLAB®. The Agilent InfiniiumUSB Test Option is the first scopesolution in the industry that uti-lizes the official USB-IF MATLABscript. As the result, it providesan affordable, trustworthy, single-box, compliance solution—allow-ing you to say, as did one of ourcustomers, “I know I’m going topass!”23Full/Low-Speed Test SuiteAgilent test equipment has beenapproved by the USB-IF.Figure 1. Agilent Infiniium at official USB-IF Plugfest.The basic USB 2.0 electrical test suite includes signal quality,in-rush current check, and droop/drop tests. A SQiDD (Signal Quality inrush Droop Drop) fix-ture must be used for these tests. Agilent provides a SQiDD boardFull/Low-Speed Test Fixturethat is orderedseparately as part numberE2646A. The USB-IF exclusively uses the Agilent SQiDD board for official compliance testing.Figure 2. Agilent SQiDD board.Wire loopWire loop‘B’ Socket‘A’ Socket‘B’ Socket‘B’ Socket‘A’ Socket‘A’ SocketSwitchSwitch4Signal Quality TestUsing an oscilloscope to measure transceiver characteristics, the signal quality test looks at:• Signal eye• End of Packet (EOP) width • Signaling Rate • Rise/Fall Times• Cross-over Voltage Range • Consecutive Jitter • Paired JK Jitter • Paired KJ JitterSignal quality testing can beperformed for either upstream data or downstream data. In the case of upstream testing, signals travelling from the device to the host are captured and analyzed. Downstream testing performs just the opposite, capturing signals travelling from the host towards the device or terminating hub. Figure 3 shows a captured down-stream packet on the Infiniiumscope with the USB Test Option.Figure 3. Captured downstream packet.Signal Quality Test (continued)launched, other conditions mustalso be set in the software. Forsignal quality tests, these addi-tional conditions include tierand near end/far end. The tierrefers to the distance between thedevice and the host computer. Ifthe device is connected directly tothe host computer, the tier equals1. If the device is separated fromthe host computer by 3 hubs, thetier equals 4. Compliance testingmandates that testing occur ata minimum tier of 6; therefore,Agilent recommends that testsalways be performed with a tierFigure 4. Infiniium USB test menu.of 6. Test results may be storedin a data file on the Infiniium’sC: drive, or may also be stored toa USB flash drive.Infiniium displays all test resultsin an html format, including theeye diagram.Figure 5. Infiniium signal quality test results.5In-Rush Current Checkdictates that a surge of currentwill occur, followed by a lessersteady-state current level, whenpower is applied to a device.The hot-pluggable nature of USBrequires that the total inrushsurge current be tested to ensurethat it remains within the limitsfor the device. If the inrushcurrent does not remain withinits limits (100 mA), not only canit cause damage to the device, butit can also take power from otherdevices connected to the sameport.The USB 2.0 specification out-lines a total inrush surge currentlimit of 50-uC. A waiver is grant-ed at 150 μC.Figure 7. In-rush current spike.67Droop and Drop TestingBack-Drive Voltage TestDroop and drop testing proce-dures vary based on whether the device is self-powered or bus powered.Hosts and Self-Powered Hubs Drop testing measures the DC voltage drop across each load board attached to the SQiDD board. To get a good indication of voltage drop, the test is per-formed under two conditions—no load and load. Under no load testing, all downstream ports remain open, while the V BUS voltage test points on the SQiDD board are probed. Load testing tests the V BUS voltage test points with 500-mA loads applied to all downstream ports. The lowest measured loaded value should be used for the droop test.Droop testing involves measuring the AC voltage drop on V BUS that occurs when all but one port are under 500-mA loads; The unload-ed port is then connected to the SQiDD board. Once the instantan-cous AC voltage drop is captured on the display, markers are used to bracket the area between the lowest point and steady-state voltage point of V BUS . Infiniium then uses the bracketed data toperform the droop test.Figure 8. Droop setup for hosts and self-powered hubs.The droop test for bus-powered hubs again uses the 100-mA-load board. This load board is con-nected to all but one port on the bus-powered device. The SQiDD board is then attached to the unloaded port. Once again,markers are used to bracket the area between the lowest point on the captured data and the steady-state voltage. TheInfiniium then uses the bracketed data to run the drop test.Bus-Powered HubsDrop tests for bus-powered hubs use 100-mA load boards instead of the 500-mA load boards used in the self-powered hub proce-dure. These 100-mA boards are connected to all downstream ports. The V BUS voltage is then measured at the hub upstream port and at each downstream port. The lowest measured downstream value is used for the drop test.The back-drive voltage test is performed to ensure that a device only draws and does not sourcecurrent from V BUS on its upstream facing port at all times. If a device supplies current at this port, a number of consequences can occur, including hub enumerationfailure, PC boot failure, and motherboard failure. This test measures the DC voltages ofV BUS , D+, and D- before and after device enumeration. The voltages are then recorded on the back-drive voltage fixture. Any voltage exceeding 400-mV is considered a failure.8On the hi-speed USB Test Bed Computer, the USB hi-speedElectrical Test Tool is required.Figure 9. USB-IF hi-speed electrical test tool.Hi-Speed Electrical Test SuiteAn additional suite of tests was added to the USB 2.0 compliance procedure to accommodate the new hi-speed mode. These tests include hi-speed signal quality, receiver sensitivity, CHIRP timing, and packet parameter.Hi-Speed Electrical Test Tool9The hi-speed signal quality test utilizes the hi-speed signal quality board, as shown in Figure 10.The nomenclatures of the test points differ between the Agilent hi-speed test fixture and the Intel test fixture. The official USB test procedure is written with reference to Agilent’s test fixtures. Refer to Table 5, the cross-reference chart, whenusing Intel’s test fixture.Figure 10. Hi-speed signal quality boards (Agilent fixture andIntel fixture—device signal quality test).Hi-Speed Test Fixture10Hi-Speed Signal Quality TestInvoke the Hi-speed Electrical Test Tool software on Electrical Test bed computer and select TEST_PACKET to perform the sig-nal quality test. Figure 11 shows a hi-speed test packet captured on an Infiniium oscilloscope.Prior to testing, it must be deter-mined if the device incorporates a captive cable, or if it contains a series B or mini-B connector. During upstream tests, captive cables require that tests be run at the far end. B-connector cables require that tests be run at the near end. Figure 12 shows a hi-speed eye pattern result displayed on an Infiniiumoscilloscope.Figure 11. Hi-speed test packet.Figure 12. Hi-speed signal quality eye diagram.MonotonicityMonotonicity tests if a transmit-ted signal increases or decreases in amplitude without reversal in the opposite direction. The monotonicity characteristic of a signal can be viewed using the hi-speed signal quality eye template (Figure 12). There is no indepen-dent monotonicity test mandated by the USB-IF.Receiver SensitivityThe receiver sensitivity tests verify sensitivity of the receivers of a device on both the upstream and downstream data ports in noisy environments. The Agilent 81130A/81134A Pulse/Pattern Generator is used to emulate IN commands from the port to the device address 1. IN commands are sent from the computer to the device under test, which should be in an unsquelched mode. The noise is represented by a pre-set level, whereby a signal meeting and exceeding this level responds to the IN command with anNAK. All packets from the data generator must be NAK’d by the port under test. The amplitude of the data generator packets is then reduced in 20-mV increments as the test is run. The amplitude of these packets should be reduced until the NAK packets become infrequent. The data generator amplitude is then immediately increased to the point where the Figure 14. Receiver sensitivity test.Data generator packet Device responsegenerator packetPacket Parameters TestAnother test using the hi-speedsignal quality board tests thedevice packet parameters. Thehi-speed signal quality test boardallows for better reception of thepackets coming from the device.This test measures parameterssuch as sync field length, end ofpacket (EOP) width, and inter-packet gap.Figure 13. Device inter-packet gap.NAK packets are not intermittent. This indicates the points of minimum receiver sensitivity levels before squelch.When the device receives IN packets with a signal amplitude in excess of 150-mV, all packets should be NAK’d. When the device receives IN packetswith a signal amplitude below 100-mV, all packets should be squelched. A waiver is granted for squelch at +/- 50-mV for each level.11CHIRP Timing TestThe CHIRP test utilizes thehi-speed signal quality test fixture to measure timing and voltage on both upstream and downstream ports. The deviceis hot-plugged to the port andis immediately enumerated to capture the CHIRP handshake. Within the handshake, the CHIRP-K duration is measured to verify that it is within the 1.0-ms and 7.0-ms allowable latency. After the CHIRP K-J, K-J, K-J sequence, the device responds by turning on its hi-speed termina-tions. A drop of amplitude from800-mV nominal to 400-mV nominal occurs. The time between the beginning of thelast J in the CHIRP K-J, K-J, K-J sequence and the time whenthe device turn on initiates its hi-speed terminations must be mea-sured to verify that it is less than or equal to 500-μs.In addition to measuring thetime between the last J in CHIRP and the initiation of hi-speed termination, the CHIRPtest also measures device suspend/resume/reset timing as well as the K and J amplitudes.Figure 15. CHIRP test.Device’s chip latency(2.5 µs <-> 3 ms)Device hi-speedtermination ONFigure 16. Time between last J in CHIRP and hi-speed termination initiation.CHIRP K(1 ms <-> 7 ms)12Impedance Measurements In this test, differential time domain reflectometer (TDR) mea-surements are taken tomeasure the impedance of the hi-speed signaling path andactive terminations of the device under test. The TDR measure-ments are compared with the USB-IF specification require-ments. The device under testis powered, placed in SE0-NAK mode, and isolated from the system. D+ and D- are measuredto verify that they are 0-V ±10-mV.A 400-ps edge is then driven into the device. The resulting wave-form indicates whether or not the termination impedance and the through impedance meet the requirements. The TDR measure-ment is not required for compli-ance testing. A PASS signal quality test will suffice for the TDR measurement.Figure 17. TDR measurement.USB connectorTermination resistor1314SummaryAgilent provides a comprehen-sive, easy-to-use solution for USB compliance testing. The compli-ance testing that once took days now takes only minutes. The indi-vidualized test boards provideflexibility and affordability for the laboratory choosing to test facets of the USB specification simultaneously.In conclusion, the AgilentInfiniium USB Test Option has been described this way:“The term ‘God Send’ comes to mind. Before the arrival of this scope, a USB test was something to be avoided! It often required half a day to set up the test and an additional 30 minutes to massage the numbers into anacceptable MATLAB format.Needless to say only the minimum number of tests required was ever actually performed.“In a nutshell, this product has revolutionized the way in which we look at USB. We now have a designated test system that is reliable and easy to use and fast. The main result is that we can now provide real-time feedback, and the amount of testing we perform is probably up 30-fold or more. And as you may have guessed, the additional testing has turned up a myriad of inter-esting opportunities for future improvements. Just for fun we have even started looking at our competitor’s products!”MATLAB ® is a U.S. registered trademark of Math Works, Inc.Windows ® is a U.S. registered trademark of Microsoft Corporation.Agilent Technologies OscilloscopesMultiple form factors from 20 MHz to >90 GHz | Industry leading specs | Powerful applications15Remove all doubtOur repair and calibration services will get your equipment back to you, performing like new, when promised. You will get full value out of your Agilent equipment throughout its lifetime. Your equipment will be serviced by Agilent-trained technicians using the latest factory calibration procedures, automated repair diagnostics and genuine parts. You will always have the utmost confidence in your measurements.Agilent offers a wide range of additionalexpert test and measurement servicesfor your equipment, including initialstart-up assistance, onsite educationand training, as well as design, systemintegration, and project management.For more information on repair andcalibration services, go to:/find/removealldoubt/find/openAgilent Open simplifies the process of connecting and programming test systems to help engineers design, validate and manufacture electronic products. Agilent offers open connectivity for a broad range of system-ready instruments, open industry software, PC-standard I/O and global support, which are combined to more easily integrate test system development./find/emailupdates Get the latest information on the products and applications you select./find/agilentdirect Quickly choose and use your test equipment solutions with confidence.Agilent Email UpdatesAgilent DirectLXI is the LAN-based successor to GPIB, providing faster, more efficient connectivity. Agilent is a founding member of the LXI consortium./fi nd/usb2_compliance For more information on Agilent Technologies’ products, applications or services, please contact your local Agilent office. The complete list is available at:/fi nd/contactusAmericasCanada (877) 894-4414 Latin America 305 269 7500United States (800) 829-4444Asia Pacifi c Australia 1 800 629 485China 800 810 0189Hong Kong 800 938 693India 1 800 112 929Japan 0120 (421) 345K orea 080 769 0800Malaysia 1 800 888 848Singapore 1 800 375 8100Taiwan 0800 047 866Thailand 1 800 226 008Europe & Middle EastAustria 01 36027 71571Belgium 32 (0) 2 404 93 40 Denmark 45 70 13 15 15Finland 358 (0) 10 855 2100France 0825 010 700* *0.125 €/minute Germany 07031 464 6333****0.14 €/minuteIreland 1890 924 204Israel 972-3-9288-504/544Italy 39 02 92 60 8484Netherlands 31 (0) 20 547 2111Spain 34 (91) 631 3300Sweden 0200-88 22 55Switzerland 0800 80 53 53United Kingdom 44 (0) 118 9276201Other European Countries: /fi nd/contactusRevised: July 17, 2008Product specifi cations and descriptions in this document subject to change without notice.© Agilent Technologies, Inc. 2008Printed in USA, August 1, 20085988-6219EN。
集成电路中电源完整性与信号完整性分析
集成电路中电源完整性与信号完整性分析哎呀，说起集成电路中的电源完整性和信号完整性分析，这可真是个让人又爱又恨的“家伙”。
就拿我之前经历的一件事儿来说吧。
有一次，我参与了一个小型电子设备的研发项目。
那时候，我们团队满心欢喜地设计好了整个集成电路的架构，觉得大功告成。
可谁知道，在实际测试的时候，问题接二连三地冒了出来。
先是电源方面，设备运行没多久，就出现了电压不稳定的情况。
这就好比你正在跑步，突然有人给你使绊子，让你的脚步变得踉踉跄跄。
我们开始仔细排查，发现是电源布线不合理，导致电流在传输过程中出现了损耗和波动。
再说说信号完整性。
明明发送出去的是清晰准确的信号，可接收端却总是出现误码和失真。
这感觉就像是你给朋友精心准备了一份礼物，结果快递给你弄破了包装，里面的东西也坏了。
那咱们先来说说电源完整性。
电源完整性简单来说，就是要确保集成电路中的电源供应稳定、干净，没有杂波和干扰。
这就像我们家里的电，如果电压一会儿高一会儿低，那电器能正常工作吗？肯定不行！在集成电路里也是一样，如果电源不稳定，那各个元器件就像失去了主心骨，没法好好干活。
比如说，在多层电路板的设计中，如果电源层和地层的间距不合理，就会产生寄生电容和电感。
这就好比在一条马路上，突然多了一些障碍物，让电流的通行变得不顺畅。
还有，电源分配网络的设计也至关重要。
如果电阻过大，电流就会遇到“堵车”，导致电压下降。
再讲讲信号完整性。
信号在集成电路中传播，就像是一场旅行。
如果路径不好，信号就会“迷路”或者“受伤”。
比如说，高速信号在传输线上传播时，如果传输线的特征阻抗不匹配，就会发生反射，这就像声音在空旷的山谷中回荡，影响了信号的质量。
还有串扰问题。
相邻的信号线就像住在隔壁的邻居，如果靠得太近，彼此之间就会互相干扰。
想象一下，你正在专心看书，旁边有人大声吵闹，你能静下心来吗？信号也是一样，被干扰了就没法准确传达信息。
为了保证电源完整性和信号完整性，我们在设计的时候要特别小心。
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信号完整性测试指导书——Ver 2.0编写：黄如俭（sam Huang）钱媛（Tracy Qian）宋明全（Ivan Song）康钦山（Scott Kang）目录1. CLK Test (3)1.1 Differential Signal Test (3)1.2 Single Signal Test (5)2. LPC Test (7)2.1 EC Side Test (7)2.2 Control Sidse Test (8)3. USB Test (11)3.1 High Speed Test (11)3.2 Low Speed Test (12)3.3 Full Speed Test (12)3.4 Drop/Droop Test (12)4. VGA Test (14)4.1 R、G、B Signal Test (14)4.2 RGB Channel to Channel Skew Test (14)4.3 VSYNC and HSYNC Test (15)4.4 DDC_DATA and DDC_CKL Test (15)5. LVDS Test (17)5.1 Differential data signals swing Test (17)5.2 Checking Skew at receiver Test (18)5.3 Checking the offset voltage Test (19)5.4 Differential Input Voltage Test (20)5.5 Common Mode Voltage Test (20)5.6 Slew Rate Test (21)5.7 Data to Clock Timing Test (23)6. FSB Test (26)7. Serial Data（SATA/ESATA, PCIE, DMI,FDI）Test (29)8. HD Audio Test (30)8.1 Measurement at The Controller (30)8.2Measurement at The Codec (31)9. DDR2 Test (34)9.1 Clock (34)9.2 Write (35)9.3 Read (37)10.Ethernet Test (39)11.SMbus Signal Test (40)12. HDMI Test (42)13. DisplayPort Test (43)1. CLK Test1.1 Differential Signal Test测试设备：示波器，两个差分探头，鼠标，键盘测试软件：3D MARK，负载测试步骤：（1）开启示波器预热30分钟，运行测试软件。
连接差分探头，鼠标，和键盘。
对示波器的probes和channals进行calibration和deskew。
（2）参照测试平台的芯片datasheet,使用Allegro SPB软件，在电路板上找出被测信号测试点,记录下过孔或芯片管脚的位置。
找出待测信号接收端的参数标准。
如图1.1图1.1（3）连接电路板的附属小板，显示屏，电源，将示波器和电路板共地。
开启电路板，正常进入系统，运行3D Mark。
（4）参照被测信号测试标准，在示波器（Agilent ）的菜单选项中选择对应的测试项Frequency/Period/ Duty Cycle/High Time/ Low Time/cyc-cyc-jitter .Spec中有约束条件的要进行条件设置。
如图1.2图1.2（5）用一个差分探头连接差分信号测试点，调节示波器，抓取所需要的波形，并保存。
（6）清除之前的测试选项和波形。
再次从菜单选项中选择测试项。
Rise time/Fall time/Overshoot/Undershoot/High level/Low level（7）根据测试标准的要求，选择相应的探头。
如果要求使用单端探头，将探头的“+”端接信号测试点，“-”端接地；如果要求使用差分探头，将探头连接差分信号的两个测试点，调节示波器，抓取所需要的波形，并保存。
（8）Vcross的测试：a.用两个单端探头的“+”极分别连接clk信号的P/N极，“—”极连接差分信号测试点最近的地。
在同一屏幕上显示两个通道的波形，调整参数使两个通道的OFFSET，单位幅值相同，抓取密集波形。
调出marker,用两条横向的坐标分别卡出两条信号线交点（同一信号相同的边沿）的最大值和最小值。
如图1.3图1.3b.使用无限累积功能，抓取一个交点的累积波形。
调出Marker,用两条横向坐标轴分别卡出交点的最大值和最小值。
两条横项坐标轴的值就是V_cross的值。
如图1.4图1.4（9）Vcross detal的测试：依照Vcross的测试方法，测出Vcross的最大值和最小值，两值的差（即两条Marker值差的绝对值）就是Vcross detal.测试标准：将测得的数据与测试标准对照，判断测试结果是否在标准之内。
若在，则测试结果合格，定为PASS。
若不在标准之内，则测试结果不合格，定为FAIL。
注意事项：(1)测试时，要将示波器与电路板共地。
(2)测试Rise time/Fall time/Overshoot/Undershoot/ High level/Low level时，依据给定的标准选择使用差分探头或时单端探头。
(3)对于测试标准中有约束条件的测试项，要按照标准更改示波器的条件设置，测得的数据才可与标准值比对。
比如，对高电平和低电平范围的规定。
(4)信号的测试标准参考接收芯片端 datasheet 的数据。
1.2 Single Signal Test测试设备：示波器，两个单端探头，鼠标，键盘测试软件：3D MARK，负载测试步骤：(1)-(3)同差分信号测试。
（4）参照信号在接收芯片端的测试标准，从示波器测试软件的菜单选项中选择测试项。
Spec中有约束条件的要进行条件设置。
Frequency/Period/High Time/Low Time/Rise time/Fall time/Overshoot/Undershoot/ Duty Cycle/ Cycle to cycle Jitter/High level/Low level（5）用单端探头探接测试点，调节示波器旋钮，抓取所需要的波形，并保存。
测试标准：将测得的数据与测试标准对照，判断测试结果是否在标准之内。
若在，则测试结果合格，定为PASS。
若不在标准之内，则测试结果不合格，定为FAIL。
注意事项：(1)对于测试标准中有约束条件的测试项，要按照标准更改示波器的条件设置，测得的数据才可与标准值比对。
比如，对高电平和低电平范围的规定。
(2)信号的测试标准参考接收芯片端 datasheet 的数据。
2. LPC Test2.1 EC Side Test测试设备：示波器，两个单端探头，鼠标，键盘测试步骤：（1）开启示波器预热30分钟，运行测试软件。
连接单端探头，鼠标，和键盘。
对示波器的probes和channals进行calibration和deskew。
（2）参照电路图,使用Allegro SPB软件，找出线路最长和最短的LPC数据信号LPC_AD,记录下待测信号的位置。
找出待测信号在EC芯片端的参数标准。
如图2.1。
图2.1 at receiver of EC（3）连接电路板的LCD和电源，将示波器和电路板共地。
开启电路板，正常进入系统.（4）用两个单端探头分别连接LPC_CLK信号和LPC_AD信号在EC芯片端的测试点，调节示波器旋钮，待设置完成后，重新启动计算机以抓取波形。
（5）调出Marker其mark point按照SPEC来定义，测出所需参数值。
如图2.2图2.2 at receiver of EC2.2 Control Sidse Test测试设备：示波器，两个单端探头，鼠标，键盘测试步骤：（1）开启示波器预热30分钟，运行测试软件。
连接单端探头，鼠标，和键盘。
对示波器的probes和channals进行calibration和deskew。
（2）参照芯片的datasheet,使用Allegro SPB软件，找出线路最长和最短的LPC数据信号LPC_AD,记录下待测信号的位置。
找出待测信号在Control端的参数标准。
如图2.3。
图2.3 at receiver of ISCH（3）连接电路的LCD和电源，将示波器和电路板共地。
开启电路板，正常进入系统.（4）用两个单端探头分别连接LPC_CLOUT信号测试点和LPC_AD信号测试点，调节示波器旋钮，待设置完成后，重新启动计算机以抓取波形。
（5）调出Marker其mark point按照SPEC来定义，测出所需参数值.如图2.4图2.4 at receiver of ISCH测试标准：将测得的数据与测试标准对照，判断测试结果是否在标准之内。
若在，则测试结果合格，定为PASS。
若不在标准之内，则测试结果不合格，定为FAIL。
注意事项：（1）对于测试标准中有约束条件的测试项，要按照标准更改示波器的条件设置，测得的数据才可与标准值比对。
比如测量波形的数据时，Test point 要根据datasheet设定。
（2）信号的测试标准参考接收芯片端芯片 datasheet 的数据。
3. USB Test3.1 High Speed Test测试设备：示波器（MSO90404A），1168A，E2678A，E2649（USB测试夹具），USB Cable（若干）。
测试软件：USB一致性测试软件，USBHSET software。
测试步骤：（1）打开示波器，预热30分钟左右。
（2）运行一致性测试软件，进入软件Set Up设置页面，将Device Test Point设置为Host，Test Method设置为Matlab。
图3.1（3）Select Tests设置，选择High Speed Test。
（4）Configure设置，选择测试通道，特征参数为High Speed Near End。
（5）按照Connect测试界面提示的连接方法，选择相应的测试夹具，进行连接。
（6）确认连接无误后，运行测试。
（7）查看测试报告，保存测试报告。
3.2 Low Speed Test测试设备：示波器（MSO90404A），2*N2873A，E2649（USB测试夹具），Low Speed Device，USB Cable（若干）。
测试软件：USB一致性测试软件测试步骤：（1）运行一致性测试软件，进入软件Set Up设置页面，将Device Test Point设置为Host，Test Method设置为Matlab。