2014佳木斯大学电子信息专业英语考试范围(作业题)(20140529)

作业1：14.02.27digital ↔ analog数字↔ 模拟hardware↔software↔firmware 硬件↔软件↔固化软件building block 标准部件development 开发debug 调试refer to as 称为random access 随机储存scale 规模passive ↔ active 有源的↔无源的component 元件Fig. figure 图Open 悬空，开路current ↔ voltage ↔ potential 电流电压电位transistor ↔ diode 三极管二极管anode ↔ negative pole 正极负极inversion ↔ non-invert 倒相正相stage 级circuitry 电路系统element 元件truth table 真值表positive ↔ negative 正↔ 负in terms of === take advantage of 利用power consumption === power dissipation 功耗property ↔ performance 性能inverter 反相器with respect to 关于specification 参数device 器件semiconductor 半导体* The second area empolys techniques that are quite different from those of conventional hardware design and also require a substantial investment in special test equipment for efficient development and debugging.第二个领域使用的技术与不传统硬件设计有较大的不同，为了有效的开发和调试也需要在一些特殊测试装备大量投入。

* It does not mean that the device can operate properly at that speed.那就意味着器件不能在那样的速度下恰当的工作作业2：14.03.04toggle frequency 触发频率in series ↔ in parallel 串联并联response 响应capacitance ↔inductance ↔ resistor 电容电感电阻pull-up resistor 负载电阻operating frequency 工作频率TTL: transistor transistor logic 晶体管晶体管逻辑MOS: metal-oxide-semiconductor 金属氧化物半导体ECL: emitter-coupled logic 射极耦合逻辑MSI : medium-scale integration 中等规模集成电路LSI : large-scale integration 大规模集成电路come in 分类power dissipation== power consumption 功耗tradeoff 折衷sensitive ↔ insensitive敏感↔不敏感spike ↔ glitch 尖脉冲↔短时脉冲act as 充当noise susceptibility 噪声敏感度breakdown voltage 击穿电压supply pin 电源引脚* It is essential in digital circuits that signal edges occur in a known order.在数字电路中信号边缘的已知顺序发生是至关重要的。

* If speed is not required, the Low Power class is a good choice, not only because of low power consumption, but because its low speed makes it insensitive to many high-frequency spikes and glitches.如果不考虑速度，低功耗好类是个好的选择，不仅仅是因为低功耗，而且它的低速度使得它对很多高频率尖脉冲和短时脉冲不敏感作业3：14.03.06microfarad 微法emitter input 射极输入pin compatible 引脚兼容flip-flop 触发器mediumspeed device 中等速度器件toggle frequency 触发频率superior to 优于noise immunity 抗噪drive capability 驱动能力input impedance 输入阻抗RAM: random-access memory 随机存储器ROM: read-only memory 只读存储器for short 简称output stage 输出级package 封装function generator 函数发生器square-wave 方波tunable 可调的signetics 芯片timer 定时器counter 计数器synchronous counter 同步计数器logical operation 逻辑运算block diagram 框图oscilloscope 示波器oscillator 振荡器symmetrical waveform 对称波形synchronous ↔ asynchronous同步异步synchronous counter 同步计数器latch 锁存器S-R: shift register 移位寄存器Divider 分频器programmable counter 可编程计数器* This differs from the other forms of logic in that the transistors are operated in a linear mode and not allowed to go into saturation.它不同于其它逻辑形式，因为晶体管工作在线性模式并且不允许进入饱和状态。

* If the speed limitations are acceptable, these devices are, on an all-around basis, clearly superior to the other families of logic.如果速度限制可以接受，总得来说，这些器件优于其他逻辑系列。

* There is really not much difference between ―basic circuits‖ and ―building blocks,‖ except that the term ―building blocks‖ implies th at the function is contained in one package and is generally more complex.基本电路和标准件之间没有太多差别，除了标准件的名称暗示着其功能包含一个封装内通常更复杂。

* Particular attention should be given to power consumption, which depends strongly on the operating frequency and load.在功耗方面特别注意，它很大程度上取决于工作频率和负载。

作业4：14.03.114-bit device 4位器件EOC: end of conversion 反转端multistage operation 多级运算P.E. : parallel enable 并行使能timing waveform 时序波形LSB: least significant bit 最低有效位MSB: most significant bit 最高有效位preset value 预设值Bi-direction 双向的parallel ↔ serial 并行串行coder ↔ decoder 编码器译码器BCD: binary coded decimal 二-十进制计数器Comparator 比较器Cascade 级联Monostable 单稳态trigger↔retrigger↔nonretrigger触发↔再触发↔非触发noise rejection 抗噪* The digital monostable puts out a pulse that is equal to the time required to count a given number of clock pulses and starts and finishes in synchronism with the clock.数字单稳态产生的脉冲等于计数所需给定时钟的时间，且随着时钟脉冲同步开始和结束。

* If all that is required is a division of the clock frequency, the Q inputs are not required.如果只对时钟频率分频，那么不需要输入。

* In digital circuits where wire wrap is used the timing components are commonly mounted on a cradle adjacent to the monostable.在线绕用于时序元件的数字电路中通常固定在靠近单稳态的支架上。

汉译英：数字电路↔模拟电路digital circuit ↔analog circuit电流↔电压current ↔voltage二极管↔三极管divide ↔transistor负载电阻↔功耗pull up resistor ↔power consumption逻辑器件↔真值表logical device ↔truth table软件↔硬件software ↔hardware大规模集成电路LIS: large scale intergration输入阻抗input impedance框图block diagram电容↔电感↔电阻capacitance ↔inductance ↔resistor作业5：14.03.13transmitter ↔ receiver 发射机↔接收机modulate ↔demodulate 调制↔解调filter 滤波器amplipy↔ amplifier放大↔放大器superheterodyne receiver 超外差接收机narrow bang 窄带incoming signal 接收信号local oscillator 本振difference frequency 差频IF:intermediate frequency 中频RF:radio frequency 射频block diagram 框图tuned circuit 调谐电路image signal噪声系数spurious signal 镜像信号reject =prevent=suppress 抑制intermoulate互调*In digital circuits where wire wrap is used the timing components are commonly mounted on acradle adjacent to the monostable.在线绕用于时序元件的数字电路中通常固定在靠近单稳态的支架上。