基于FPGA的SDRAM实验Verilog源代码
毕业设计(论文)-基于fpga的sdram控制器的实现(软件部分)[管理资料]
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毕业设计(论文)机械与电气工程学院电气工程及其自动化专业毕业设计（论文）题目基于FPGA的SDRAM控制器的实现（软件部分）学生姓名班级电气工程及其自动化学号指导教师完成日期2012 年 6 月 6 日基于FPGA的SDRAM控制器的实现（软件部分）The realization of SDRAM controller based on FPGA (software)总计毕业设计（论文） 41 页表格 6 个插图 21 幅摘要文中介绍了FPGA的开发流程、硬件开发语言及其开发环境QuartusII和SDRAM的结构特点和工作原理，根据SDRAM的工作原理、控制时序和指令特点，设计一种基于FPGA的SDRAM控制器的方案。
SDRAM控制器的设计主要由主控制模块、信号产生模块、数据路径模块和参数模块组成。
本设计解决SDRAM控制复杂、不方便的问题，并用Verilog给予仿真结果。
仿真结果表明使用该方法设计实现的控制器能够使系统方便，可靠的对SDRAM进行操作。
关键字：SDRAM控制器FPGA 控制模块软件仿真AbstractThis paper introduces the development process and FPGA hardware development language and the development environment of SDRAM QuartusII and structural characteristics and working principle, according to the working principle of SDRAM, sequence control and instruction characteristics, a scheme based on FPGA SDRAM controller is designed. SDRAM controller design mainly by the master control module, signal module, data path module and parameter module composition. This design solved a problem about the controlling complexity of SDRAM controller, and gives the simulation results by using Verilog. The simulation results show that using this method to design the controller can realize the system is convenient, reliable operation of SDRAM.Key words: SDRAM controller FPGA Control module Software simulation目录摘要 (I)Abstract (II)第一章绪论 (1)课题背景 (1)课题研究的意义 (1)第二章FPGA与Quartus II软件简介 (2)FPGA简介 (2)FPGA背景 (2)FGPA结构原理 (2)Quartus II软件简介 (3)硬件描述语言Verilog (4)FPGA开发过程 (5)第三章SDRAM的技术介绍 (6) (6)SDRAM简介 (6)SRAM和DRAM (6)SDRAM发展过程 (7)SDRAM工作原理和基本操作 (8)SDRAM存储的工作原理 (9)SDRAM 的引脚信号 (9)SDRAM基本命令 (10)SDRAM初始化 (10)SDRAM读、写操作 (11)终止操作 (12)第四章 SDRAM控制器设计 (12)SDRAM控制器 (13)主控制模块 (14)信号产生模块 (16)参数模块 (18)数据通路模块 (19)第五章SDRAM的读、写仿真 (19)SDRAM控制器时序仿真 (20)Quartus II (20)读仿真时序 (20)写仿真时序 (21)仿真结果分析 (22)结论 (24)参考文献 (25)致谢 (26)附录 (27)第一章绪论课题背景伴随着电子信息技术的飞速发展和其在通讯、工业、商业、医疗等方面的广泛应用，人们对信息的需求逐渐向着更快、更多、更准确发展。
基于FPGA的SDRAM控制器设计开发
Open Journal of Circuits and Systems 电路与系统, 2014, 3, 19-24Published Online March 2014 in Hans. /journal/ojcs/10.12677/ojcs.2014.31004Design of SDRAM Controller Based on FPGALingli Zhong, Xiaobo ZhouSchool of Electronic Science and Technology, Beijing Jiaotong University, BeijingEmail: 09214027@, xbzhou@Received: Feb. 26th, 2014; revised: Mar. 19th, 2014; accepted: Mar. 25th, 2014Copyright © 2014 by authors and Hans Publishers Inc.This work is licensed under the Creative Commons Attribution International License (CC BY)./licenses/by/4.0/AbstractThe paper briefly introduces the characteristics of SDRAM and the basic operation principle, then puts forward a design method of SDRAM controller based on FPGA. The controller was achieved by the language of Verilog. The paper analyses the overall design and the specific realization of the design scheme of each module. Finally, the image data should be stored in SDRAM, and then the reading control through SDRAM should be achieved, which sent the data to display on the VGA screen. When the colorful picture was displayed on the screen, it means the function of the SDRAM controller was achieved.KeywordsSDRAM Controller; FPGA; Verilog基于FPGA的SDRAM控制器设计开发仲玲利，周晓波北京交通大学电子信息学院，北京Email: 09214027@, xbzhou@收稿日期：2014年2月26日；修回日期：2014年3月19日；录用日期：2014年3月25日摘要在简要介绍SDRAM特点和基本操作原理的基础上，提出了一种基于FPGA的SDRAM控制器的设计方法，用Verilog硬件语言加以实现。
基于FPGA的双端口SDRAM控制器的实现
基于FPGA的双端口SDRAM控制器的实现康磊;雒明世【摘要】在实时图像处理系统中数据存储和共享是一项关键技术.SDRAM凭借其大容量、高数据传输速率和低成本优势,正在广泛的被应用于实时图像处理系统中,为此,提出了一种基于FPGA技术的具有两个独立读写端口的SDRAM控制器方案.详细介绍了SDRAM控制器的模块构成、实现过程及其仿真结果,控制器是采用Verilog HDL实现的.通过仿真测试和硬件实验说明设计方案可行,可应用于实时信号的采集和处理系统中.%Data storage and sharing is a key technology in the real-time image processing system.Owing to its large capacity,high data transfer rate and low cost,SDRAM is increasingly used in real-time image processing system.For this reason,this paper puts forward a SDRAM controller scheme which has two independent reading and writing data ports based on FPGA technology.This paper introduces the structure and implementation process of a SDRAM controller module,and also gives the simulation results.The SDRAM controller is implemented by using Verilog HDL.The simulation test and hardware experiments show that this design scheme is feasible,and can be applied to real-time signal collection and processing system.【期刊名称】《电气自动化》【年(卷),期】2013(035)004【总页数】3页(P97-99)【关键词】SDRAM;FPGA;控制器;双端口;Verilog【作者】康磊;雒明世【作者单位】西安石油大学计算机学院,陕西西安710065;西安石油大学计算机学院,陕西西安710065【正文语种】中文【中图分类】TP330 引言在视频图像实时处理系统中，在数据的采集和显示环节需要实现快速的大量数据访问，因而就需要大容量高速度的存储设备进行数据存取，SDRAM具有容量大、速度快、价格低的特点，同时还具有较低的功耗，因此目前已经广泛地应用于实时系统中。
基于FPGA的高效率SDRAM读写双口控制器设计
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基于FPGA的Verilog语言描述的SDRAM接口电路设计
基于FPGA的SDRAM存储器接口实现摘要随着信息科学的飞速发展，人们面临的信号处理任务越来越繁重，对数据采集处理系统的要求也越来越高。
单片机、DSP等微处理器内部RAM 有限，这就需要在微处理器的外部扩展存储器。
同步动态随机访问存储器具有价格低廉、密度高、数据读写速度快的优点，从而成为数据缓存的首选存储介质，在数据采集系统和图像处理系统等方面中有着重要和广泛的应用。
SDRAM 的读写逻辑复杂，最高时钟频率达100MHz 以上，普通单片机无法实现复杂的SDRAM 控制操作。
复杂可编程逻辑器件CPLD具有编程方便，集成度高，速度快，价格低等优点。
因此选用CPLD 设计SDRAM 接口控制模块, 简化主机对SDRAM 的读写控制。
通过设计基于CPLD 的SDRAM 控制器接口，可以在STM系列、ARM系列、STC系列等单片机和DSP等微处理器的外部连接SDRAM，增加系统的存储空间。
论文开始介绍了SDRAM接口设计研究的背景和研究的目的及意义，引出对SDRAM的研究，详细介绍了SDRAM的基本原理、内部结构、基本操作和工作时序，以及设计的重点及难点。
在这些理论基础上对SDRAM 接口进行模块化设计，了解设计中所使用的硬件和软件。
最后用Verilog语言在软件QuartusⅡ设计CPLD芯片，通过在硬件和软件上的调试基本实现了SDRAM接口的设计。
关键词SDRAM；接口；Verilog；CPLDThe Implementation of SDRAM MemoryInterface Based on the EPM570AbstractWith the rapid development of information science, people face more and more onerous task of signal processing, the requirements of data acquisition and processing system are getting higher and higher. Microprocessor such as single-chip microprocessor, DSP etc, their RAM is limited, which requires external expansion in the microprocessor memory. Synchronous Dynamic Random Access Memory has a low cost, high density, fast read and write data on the merits, thereby becoming the first choice for data cache storage medium, which paly an important role and widely used in the data acquisition system and image processing systems.SDRAM read and write logic is complex, the maximum clock frequency reaches above 100MHz, the ordinary microcontroller can not achieve complex SDRAM control operation. Complex programmable logic device has advantages such as programming convenience, high integrity, high speed and low cost etc. Therefore select CPLD to design control module of SDRAM interface , to simplify the host to read and write control of the SDRAM. Through the design of SDRAM controller interface based on CPLD, you can connect SDRAM in the external of STM series, ARM series, STC series single chip microprocessor and the DSP, increase system storage space.At the beginning of paper introduces the research background, research purpose and significance of the study of SDRAM interface design, leads to the study of SDRAM, detailed introduces information of SDRAM about the basic principles, the internal structure, the basic operation and timing of work, and the design emphasis and difficulty. Based on these theories, modularing the designof SDRAM interface, understanding hardware and software used in the design. Finally, it uses Verilog language in Quartus Ⅱsoftware to design CPLD chip, Through the hardware and the software realization SDRAM the commissioning of the basic design of the interface.Keywords SDRAM; Interface; Verilog; CPLD目录摘要 (I)Abstract (II)第1章绪论 (1)1.1 课题背景 (1)1.2 课题研究的目的及意义 (1)1.3 同步动态随机存储器简介 (2)1.4 论文的结构和框架 (3)第2章SDRAM的工作原理 (4)2.1 存储器的概述 (4)2.1.1 存储器的分类 (4)2.1.2 存储器的技术指标 (5)2.1.3 存储器的比较 (5)2.2 SDRAM的工作原理 (6)2.2.1 SDRAM存储的基本原理 (6)2.2.2 SDRAM的内部结构 (7)2.3 本章小结 (8)第3章SDRAM的基本操作 (9)3.1 SDRAM的基本操作 (9)3.1.1 芯片初始化 (9)3.1.2 行有效 (9)3.1.3 列读写 (10)3.1.4 读操作 (11)3.1.5 写操作 (12)3.2 SDRAM的工作特性 (13)3.2.1 模式寄存器的设置 (13)3.2.2 预充电 (14)3.2.3 刷新 (15)3.3 SDRAM接口设计的要求 (16)3.3.1 存储器接口解决数据存取的难点 (17)3.3.2 存储器接口在工作方式上的初步优化 (17)3.4 本章小结 (18)第4章系统结构及硬件设计 (19)4.1 SDRAM接口设计的整体结构 (19)4.1.1 控制接口模块 (19)4.1.2 CAS延迟模块 (20)4.1.3 突发长度模块 (22)4.1.4 地址转换模块 (22)4.2 EPM570芯片简介 (23)4.2.1 MAXⅡ系列芯片功能简介 (24)4.2.2 逻辑阵列 (25)4.2.3 全局时钟 (25)4.2.4 I/O端口结构 (26)4.3 MT48LC系列芯片简介 (26)4.4 本章小结 (28)第5章软件设计与实现 (30)5.1 利用QuartusⅡ进行设计的流程 (30)5.2 软件的设计 (31)5.2.1 Verilog语言的特点 (31)5.2.2 采用Verilog设计综合的过程 (32)5.2.3 SDRAM接口设计的仿真 (34)5.3 本章小结 (36)结论 (37)致谢 (38)参考文献 (39)附录A (41)附录B (46)附录C (51)第1章绪论1.1课题背景数据采集处理技术是现代信号处理的基础，广泛应用于雷达、声纳、软件无线电、瞬态信号测试等领域。
基于FPGA的DDR2 SDRAM控制器设计
基于FPGA的DDR2SDRAM控制器设计钱素琴，刘晶华(东华大学信息科学与技术学院,上海，201600)摘要：基于高速数据传输与存储的数据釆集记录仪对缓存模块高性能的需求，选择了读写速度快、低成本、大容量、运行稳定的DDR2SDRAM作为本地存储器,在其存储寻址原理和IP核的读写控制逻辑的基础上，借助硬件描述语言设计了一个DDR2存储控制器方案。
在Intel的FPGA Cyclone IV系列开发板上进行了整体方案的功能验证，完成了用户接口和控制器之间的多数据宽度、多突发长度的高效数据传输和读写操作，在166.7MHz时钟频率下实现了稳定读写的目标。
关键词：FPGA；DDR2SDRAM；IP核Design of DDR2SDRAM controller based on FPGAQian Suqin,Liu Jinghua(College of information science and technology,Donghua University,Shanghai,201600) Abstract；Based on the requirement of high-speed data transmission and storage data acquisition recorder for high performance of cache module,DDR2SDRAM with high read-write speed,low cost, large capacity and stable operation is selected as the local memory.Based on its storage addressing principle and the read-write control logic of IP core,a DDR2storage controller scheme is designed with the help of hardware description language.The functional verifiestion of the overall scheme is carried out on the FPGA cyclone IV series development board of Intel.The efficient datQ transmission and read-write operation of multipie data widths and burst lengths between the user interface and the cont r oller are comple t ed.The st a ble read-wr ite t a rge t is achieved a/t166.7MHz clock frequency. Keywords：FPGA;DDR2SDRAM;IP coreo引言随着数据采集系统的发展,应用于图像采集和数据传输等领域的产品对存储器的速度要求越来越高。
基于FPGA ad数据采集存储处理报告(含Verilog源代码)
基于FPGA AD数据采集存储处理项目报告(XILINX ALTEARA 都可用)组员：华、文、杰一、实验目的本次实验利用Basys2开发板完成一个开发小项目，即开发AD数据采集存储处理系统，旨在掌握FPGA开发基本方法以及锻炼解决开发过程中出现问题的能力。
二、关键词Basys2、FPGA、AD转换、RAM、串口通信、MATLAB处理三、方案设计要实现本次项目，首先确定器件，其次根据器件时序写出模块的使用程序，最后综合成一个工程，然后进行仿真，上板实验。
本次实验的器件：32M8位模数转换器、Basys2开发板、串口转RS232cp2102模块、基于三极管的电平转换电路。
选择好器件后，根据器件的时序完成模块的代码书写。
写好AD模块、串口通信模块后，现在就需要处理采样速率与串口通讯速率不匹配的问题了。
根据香农采样定理，采样频率得高于信号频率的两倍才能完成信号复现，我们这里使用25M的高速采样频率，而串口dps9600传送一个位104us 明显比采样慢许多。
所以这里需要解决速率不匹配的问题。
我们想到可以利用FPGA的RAM先存储采样来的数据，然后再提取数据经过串口通信送至PC经由MATLAB处理。
本次小项目最为关键的是控制好采样与串口通信的时序问题。
关于时序的控制，留到模块介绍里面说明。
方案小结：本次实验基于片内RAM存储AD采样过来的数据，然后待采样完成后提取数据串口通信至PC，最后经由matlab处理。
四、模块介绍1.Verilog开发程序介绍如下给出基于QuartusII绘制出的Block Diagram图，涵盖了所有的模块以及模块之间的连线。
图4.1 综合模块图如下给出程序目录（txt格式）：现在分别介绍各个模块的端口以及功能。
AD外设：电路图、实物图、接口这个外设提供最大32M采样速率，包括一个模拟信号输入和一个采样时钟输入以及八个数字信号输出。
在每个采样时钟的上升沿输出相应的采样数字信号。
ddrsdram（mt46v4m16）的fpga控制代码
ddrsdram（mt46v4m16）的fpga控制代码`timescale 1ns / 1psmodule mt46v4m16 (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm); parameter addr_bits = 12;parameter data_bits = 16;parameter col_bits = 8;parameter mem_sizes = 1048575;inout [data_bits - 1 : 0] Dq;inout Dqs;input [addr_bits - 1 : 0] Addr;input [1 : 0] Ba;input Clk;input Clk_n;input Cke;input Cs_n;input Ras_n;input Cas_n;input We_n;input [1 : 0] Dm;reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];reg [1 : 0] Bank_addr [0 : 6];reg [col_bits - 1 : 0] Col_addr [0 : 6];reg [3 : 0] Command [0 : 6];reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;reg [addr_bits - 1 : 0] Mode_reg;reg [data_bits - 1 : 0] Dq_dm, Dq_out;reg [col_bits - 1 : 0] Col_temp, Burst_counter;reg Act_b0, Act_b1, Act_b2, Act_b3;reg Pc_b0, Pc_b1, Pc_b2, Pc_b3;reg Dqs_int, Dqs_out;reg [1 : 0] Bank_precharge [0 : 6]; // Precharge Command Bankreg A10_precharge [0 : 6]; // Addr[10] = 1 (All Banks)reg Auto_precharge [0 : 3]; // RW AutoPrecharge Bankreg Read_precharge [0 : 3]; // R AutoPrecharge Commandreg Write_precharge [0 : 3]; // W AutoPrecharge Commandinteger Count_precharge [0 : 3]; // RW AutoPrecharge Counterreg Data_in_enable;reg Data_out_enable;reg [3 : 0] Rw_command;reg [1 : 0] Bank, Bank_dqs, Previous_bank;reg [addr_bits - 1 : 0] Row, Row_dqs;reg [col_bits - 1 : 0] Col, Col_dqs;reg [col_bits - 1 : 0] Col_brst, Col_brst_dqs;reg Dll_enable;reg CkeZ, Sys_clk;// Commands Decodewire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;wire Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & Ba[0] & ~Ba[1];wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1]; wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;// Burst Length Decodewire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];// CAS Latency Decodewire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];wire Cas_latency_25 = Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];wire Debug = 0; // Turn on Debug messageswire Dq_in = Dqs & Data_in_enable; // For checking Data-in Setup/Hold timeassign Dq = Dq_out;assign Dqs = Dqs_out;//Commands Operation`define ACT 0`define NOP 1`define READ 2`define READ_A 3`define WRITE 4`define WRITE_A 5`define PRECH 6`define A_REF 7`define BST 8`define LMR 9`define EMR 10// Timing Parametersparameter tMRD = 2; // 2 Clk Cycles parameter tRC = 70;parameter tRAS = 50;parameter tRCD = 20;parameter tRRD = 20;parameter tRP = 20;parameter tWR = 4; // 2 Clk Cycles (4 Dqs) parameter tWTR = 2; // 1 Clk Cycles (2 Dqs)// Timing Checkinteger MRD_chk, WTR_chk;integer WR_chk[0 : 3];time RC_chk, RRD_chk;time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; time RP_chk, RP_chk0, RP_chk1, RP_chk2, RP_chk3;initial beginCkeZ = 1'b0;Sys_clk = 1'b0;{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;Dqs_out = 1'bz;Dq_out = {data_bits{1'bz}};{Data_in_enable, Data_out_enable} = 2'b0;{MRD_chk, WTR_chk, RC_chk, RRD_chk} = 4'b0;{RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 4'b0;{RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 4'b0;{RP_chk, RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 4'b0;{WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 4'b0;//$readmemh("bank0.txt", Bank0);//$readmemh("bank1.txt", Bank1);//$readmemh("bank2.txt", Bank2);//$readmemh("bank3.txt", Bank3);$timeformat (-9, 1, " ns", 12);end// System Clockalways begin@ (posedge Clk) beginSys_clk = CkeZ;CkeZ = Cke;end@ (negedge Clk) beginSys_clk = 1'b0;endendalways @ (Sys_clk) begin// Internal Commamd PipelinedCommand[0] = Command[1]; Command[1] = Command[2]; Command[2] = Command[3]; Command[3] = Command[4]; Command[4] = Command[5];Command[5] = Command[6]; Command[6] = `NOP;Col_addr[0] = Col_addr[1]; Col_addr[1] = Col_addr[2];Col_addr[2] = Col_addr[3];Col_addr[3] = Col_addr[4];Col_addr[4] = Col_addr[5];Col_addr[5] = Col_addr[6];Col_addr[6] = 0;Bank_addr[0] = Bank_addr[1];Bank_addr[1] = Bank_addr[2];Bank_addr[2] = Bank_addr[3];Bank_addr[3] = Bank_addr[4];Bank_addr[4] = Bank_addr[5];Bank_addr[5] = Bank_addr[6];Bank_addr[6] = 2'b0;// Precharge PipelineBank_precharge[0] = Bank_precharge[1];Bank_precharge[1] = Bank_precharge[2]; Bank_precharge[2] = Bank_precharge[3]; Bank_precharge[3] =Bank_precharge[4]; Bank_precharge[4] = Bank_precharge[5]; Bank_precharge[5] = Bank_precharge[6]; Bank_precharge[6] = 2'b0;A10_precharge[0] = A10_precharge[1];A10_precharge[1] = A10_precharge[2];A10_precharge[2] = A10_precharge[3];A10_precharge[3] = A10_precharge[4];A10_precharge[4] = A10_precharge[5];A10_precharge[5] = A10_precharge[6];A10_precharge[6] = 1'b0;// tWR counterWR_chk[0] = WR_chk[0] + 1;WR_chk[1] = WR_chk[1] + 1;WR_chk[2] = WR_chk[2] + 1;WR_chk[3] = WR_chk[3] + 1;WTR_chk = WTR_chk + 1;// Commands Operation decodeif (Sys_clk === 1'b1) begin// Read or Write with Auto Precharge Counterif (Auto_precharge[0] === 1'b1) beginCount_precharge[0] = Count_precharge[0] + 1;endif (Auto_precharge[1] === 1'b1) beginCount_precharge[1] = Count_precharge[1] + 1;endif (Auto_precharge[2] === 1'b1) beginCount_precharge[2] = Count_precharge[2] + 1;endif (Auto_precharge[3] === 1'b1) beginCount_precharge[3] = Count_precharge[3] + 1;end// tMRD CounterMRD_chk = MRD_chk + 1;// Auto Refreshif (Aref_enable === 1'b1) beginif (Debug) $display ("at time %t AREF : Auto Refresh", $time);// Auto Refresh to Auto Refreshif ($time - RC_chk < tRC) begin$display ("at time %t ERROR: tRC violation during Auto Refresh", $time);end// Precharge to Auto Refreshif ($time - RP_chk < tRP) begin$display ("at time %t ERROR: tRP violation during Auto Refresh", $time);end// Precharge to Auto Refreshif (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin$display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);end// Record Current tRC timeRC_chk = $time;end// Extended Mode Registerif (Ext_mode_enable === 1'b1) beginif (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) beginif (Addr[0] === 1'b0) beginDll_enable = 1'b1;if (Debug) $display ("at time %t EMR : Enable DLL", $time);end else beginDll_enable = 1'b0;if (Debug) $display ("at time %t EMR : Disable DLL", $time);end// LMR/EMR to LMR/EMRif (MRD_chk < tMRD) begin$display ("at time %t ERROR: tMRD violation during Extended Mode Register", $time);end// Record current tMRD timeMRD_chk = 0;end else begin$display ("at time %t ERROR: all banks must be Precharge before Extended Mode Register", $time); endend// Load Mode Registerif (Mode_reg_enable === 1'b1) begin// Decode DLL, CAS Latency, Burst Type, and Burst Lengthif (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin Mode_reg = Addr;if (Debug) begin$display ("at time %t LMR : Load Mode Register", $time);// Operating modeif (Addr [11 : 7] === 5'b00000)$display (" Normal Operation");else if (Addr [11 : 7] === 5'b00010)$display (" Normal Operation / Reset DLL");else$display (" Invalid Operating Mode");// CAS Latencyif (Addr[6 : 4] === 3'b010)$display (" CAS Latency = 2");else if (Addr[6 : 4] === 3'b110)$display (" CAS Latency = 2.5");else if (Addr[6 : 4] === 3'b011)$display (" CAS Latency = 3");else$display (" CAS Latency not supported");// Burst Lengthif (Addr[2 : 0] === 3'b001)$display (" Burst Length = 2");else if (Addr[2 : 0] === 3'b010)$display (" Burst Length = 4");else if (Addr[2 : 0] === 3'b011)$display (" Burst Length = 8");else$display (" Burst Length not supported");// Burst Typeif (Addr[3] === 1'b0)$display (" Burst Type = Sequential");else$display (" Burst Type = Interleaved");endend else begin$display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); end// LMR/EMR to LMR/EMRif (MRD_chk < tMRD) begin$display ("at time %t ERROR: tMRD violation during Load Mode Register", $time);endMRD_chk = 0;end// Active Block (Latch Bank Address and Row Address)if (Active_enable === 1'b1) beginif (Ba === 2'b00 && Pc_b0 === 1'b1) begin{Act_b0, Pc_b0} = 2'b10;B0_row_addr = Addr [addr_bits - 1 : 0];RCD_chk0 = $time;RAS_chk0 = $time;if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d",$time, Addr);// Precharge to Activate Bank 0if ($time - RP_chk0 < tRP) begin$display ("at time %t ERROR: tRP violation during Activate bank 0", $time);endend else if (Ba === 2'b01 && Pc_b1 === 1'b1) begin{Act_b1, Pc_b1} = 2'b10;B1_row_addr = Addr [addr_bits - 1 : 0];RCD_chk1 = $time;RAS_chk1 = $time;if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d",$time, Addr);// Precharge to Activate Bank 1if ($time - RP_chk1 < tRP) begin$display ("at time %t ERROR: tRP violation during Activate bank 1", $time);endend else if (Ba === 2'b10 && Pc_b2 === 1'b1) begin{Act_b2, Pc_b2} = 2'b10;B2_row_addr = Addr [addr_bits - 1 : 0];RCD_chk2 = $time;RAS_chk2 = $time;if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d",$time, Addr);// Precharge to Activate Bank 2if ($time - RP_chk2 < tRP) begin$display ("at time $t ERROR: tRP violation during Activate bank 2", $time);endend else if (Ba === 2'b11 && Pc_b3 === 1'b1) begin{Act_b3, Pc_b3} = 2'b10;B3_row_addr = Addr [addr_bits - 1 : 0];RCD_chk3 = $time;RAS_chk3 = $time;if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d",$time, Addr);// Precharge to Activate Bank 3if ($time - RP_chk3 < tRP) begin$display ("at time $t ERROR: tRP violation during Activate bank 3", $time);endend else if (Ba === 2'b00 && Pc_b0 === 1'b0) begin$display ("at time %t ERROR: Bank 0 is not Precharged.", $time);end else if (Ba === 2'b01 && Pc_b1 === 1'b0) begin$display ("at time %t ERROR: Bank 1 is not Precharged.", $time);end else if (Ba === 2'b10 && Pc_b2 === 1'b0) begin$display ("at time %t ERROR: Bank 2 is not Precharged.", $time);end else if (Ba === 2'b11 && Pc_b3 === 1'b0) begin$display ("at time %t ERROR: Bank 3 is not Precharged.", $time);end// Activate Bank A to Activate Bank Bif ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin$display ("at time %t ERROR: tRRD violation during Activate bank = %0d", $time, Ba); end// AutoRefresh to Activateif ($time - RC_chk < tRC) begin$display ("at time %t ERROR: tRC violation during Activate bank %d", $time, Ba);end// Record variable for checking violationRRD_chk = $time;Previous_bank = Ba;end// Precharge Blockif (Prech_enable === 1'b1) beginif (Addr[10] === 1'b1) begin{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111;{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;RP_chk0 = $time;RP_chk1 = $time;RP_chk2 = $time;RP_chk3 = $time;if (Debug) $display ("at time %t PRE : Bank = ALL",$time);// Activate to Precharge all banksif (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) ||($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin$display ("at time %t ERROR: tRAS violation during Precharge all bank", $time); end// tWR violation check for Writeif ((WR_chk[0] < tWR) || (WR_chk[1] < tWR) ||(WR_chk[2] < tWR) || (WR_chk[3] < tWR)) begin$display ("at time %t ERROR: tWR violation during Precharge all bank", $time); endend else if (Addr[10] === 1'b0) beginif (Ba === 2'b00) begin{Pc_b0, Act_b0} = 2'b10;RP_chk0 = $time;if (Debug) $display ("at time %t PRE : Bank = 0",$time);// Activate to Precharge Bank 0if ($time - RAS_chk0 < tRAS) begin$display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time); endend else if (Ba === 2'b01) begin{Pc_b1, Act_b1} = 2'b10;RP_chk1 = $time;if (Debug) $display ("at time %t PRE : Bank = 1",$time);// Activate to Precharge Bank 1if ($time - RAS_chk1 < tRAS) begin$display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time); endend else if (Ba === 2'b10) begin{Pc_b2, Act_b2} = 2'b10;RP_chk2 = $time;if (Debug) $display ("at time %t PRE : Bank = 2",$time);// Activate to Precharge Bank 2if ($time - RAS_chk2 < tRAS) begin$display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time); endend else if (Ba === 2'b11) begin{Pc_b3, Act_b3} = 2'b10;RP_chk3 = $time;if (Debug) $display ("at time %t PRE : Bank = 3",$time);// Activate to Precharge Bank 3if ($time - RAS_chk3 < tRAS) begin$display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time);。
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// megafunction wizard: %ALTPLL%// GENERATION: STANDARD// VERSION: WM1.0// MODULE: altpll// ============================================================ // File Name: clk_ctrl.v// Megafunction Name(s):// altpll//// Simulation Library Files(s):// altera_mf// ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!//// 11.0 Build 208 07/03/2011 SP 1 SJ Full Version// ************************************************************//Copyright (C) 1991-2011 Altera Corporation//Your use of Altera Corporation's design tools, logic functions//and other software and tools, and its AMPP partner logic//functions, and any output files from any of the foregoing//(including device programming or simulation files), and any//associated documentation or information are expressly subject//to the terms and conditions of the Altera Program License//Subscription Agreement, Altera MegaCore Function License//Agreement, or other applicable license agreement, including,//without limitation, that your use is for the sole purpose of//programming logic devices manufactured by Altera and sold by//Altera or its authorized distributors. Please refer to the//applicable agreement for further details.// synopsystranslate_off`timescale 1 ps / 1 ps// synopsystranslate_onmoduleclk_ctrl (areset,inclk0,c0,c1,c2,locked);input areset;input inclk0;output c0;output c1;output c2;output locked;`ifndef ALTERA_RESERVED_QIS// synopsystranslate_off`endiftri0 areset;`ifndef ALTERA_RESERVED_QIS// synopsystranslate_on`endifwire [5:0] sub_wire0;wire sub_wire2;wire [0:0] sub_wire7 = 1'h0;wire [2:2] sub_wire4 = sub_wire0[2:2];wire [0:0] sub_wire3 = sub_wire0[0:0];wire [1:1] sub_wire1 = sub_wire0[1:1];wire c1 = sub_wire1;wire locked = sub_wire2;wire c0 = sub_wire3;wire c2 = sub_wire4;wire sub_wire5 = inclk0;wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};altpll altpll_component (.areset (areset),.inclk (sub_wire6),.clk (sub_wire0),.locked (sub_wire2),.activeclock (),.clkbad (),.clkena ({6{1'b1}}),.clkloss (),.clkswitch (1'b0),.configupdate (1'b0),.enable0 (),.enable1 (),.extclk (),.extclkena ({4{1'b1}}),.fbin (1'b1),.fbmimicbidir (),.fbout (),.fref (),.icdrclk (),.pfdena (1'b1),.phasecounterselect ({4{1'b1}}),.phasedone (),.phasestep (1'b1),.phaseupdown (1'b1),.pllena (1'b1),.scanaclr (1'b0),.scanclk (1'b0),.scanclkena (1'b1),.scandata (1'b0),.scandataout (),.scandone (),.scanread (1'b0),.scanwrite (1'b0),.sclkout0 (),.sclkout1 (),.vcooverrange (),.vcounderrange ());defparamaltpll_component.clk0_divide_by = 1,altpll_component.clk0_duty_cycle = 50,altpll_component.clk0_multiply_by = 5,altpll_component.clk0_phase_shift = "0",altpll_component.clk1_divide_by = 1,altpll_component.clk1_duty_cycle = 50,altpll_component.clk1_multiply_by = 1,altpll_component.clk1_phase_shift = "0",altpll_component.clk2_divide_by = 1,altpll_component.clk2_duty_cycle = 50,altpll_component.clk2_multiply_by = 5,altpll_component.clk2_phase_shift = "5000",altpll_pensate_clock = "CLK0",altpll_component.gate_lock_signal = "NO",altpll_component.inclk0_input_frequency = 50000,altpll_component.intended_device_family = "Cyclone II",altpll_component.invalid_lock_multiplier = 5,altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_ctrl", altpll_component.lpm_type = "altpll",altpll_component.operation_mode = "NORMAL",altpll_component.port_activeclock = "PORT_UNUSED",altpll_component.port_areset = "PORT_USED",altpll_component.port_clkbad0 = "PORT_UNUSED",altpll_component.port_clkbad1 = "PORT_UNUSED",altpll_component.port_clkloss = "PORT_UNUSED",altpll_component.port_clkswitch = "PORT_UNUSED",altpll_component.port_configupdate = "PORT_UNUSED", altpll_component.port_fbin = "PORT_UNUSED",altpll_component.port_inclk0 = "PORT_USED",altpll_component.port_inclk1 = "PORT_UNUSED",altpll_component.port_locked = "PORT_USED",altpll_component.port_pfdena = "PORT_UNUSED",altpll_component.port_phasecounterselect = "PORT_UNUSED", altpll_component.port_phasedone = "PORT_UNUSED",altpll_component.port_phasestep = "PORT_UNUSED",altpll_component.port_phaseupdown = "PORT_UNUSED", altpll_component.port_pllena = "PORT_UNUSED",altpll_component.port_scanaclr = "PORT_UNUSED",altpll_component.port_scanclk = "PORT_UNUSED",altpll_component.port_scanclkena = "PORT_UNUSED",altpll_component.port_scandata = "PORT_UNUSED",altpll_component.port_scandataout = "PORT_UNUSED",altpll_component.port_scandone = "PORT_UNUSED",altpll_component.port_scanread = "PORT_UNUSED",altpll_component.port_scanwrite = "PORT_UNUSED",altpll_component.port_clk0 = "PORT_USED",altpll_component.port_clk1 = "PORT_USED",altpll_component.port_clk2 = "PORT_USED",altpll_component.port_clk3 = "PORT_UNUSED",altpll_component.port_clk4 = "PORT_UNUSED",altpll_component.port_clk5 = "PORT_UNUSED",altpll_component.port_clkena0 = "PORT_UNUSED",altpll_component.port_clkena1 = "PORT_UNUSED",altpll_component.port_clkena2 = "PORT_UNUSED",altpll_component.port_clkena3 = "PORT_UNUSED",altpll_component.port_clkena4 = "PORT_UNUSED",altpll_component.port_clkena5 = "PORT_UNUSED",altpll_component.port_extclk0 = "PORT_UNUSED",altpll_component.port_extclk1 = "PORT_UNUSED",altpll_component.port_extclk2 = "PORT_UNUSED",altpll_component.port_extclk3 = "PORT_UNUSED",altpll_component.valid_lock_multiplier = 1;endmodule// ============================================================ // CNX file retrieval info// ============================================================ // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "20.000"// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "5"// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "5.00000000"// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_ctrl.mif"// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"// Retrieval info: PRIVATE: SPREAD_USE STRING "0"// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"// Retrieval info: PRIVATE: USE_CLK0 STRING "1"// Retrieval info: PRIVATE: USE_CLK1 STRING "1"// Retrieval info: PRIVATE: USE_CLK2 STRING "1"// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"// Retrieval info: LIBRARY: altera_mfaltera_mf.altera_mf_components.all// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "5"// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "5000"// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "50000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0// Retrieval info: GEN_FILE: TYPE_NORMAL clk_ctrl.v TRUE// Retrieval info: GEN_FILE: TYPE_NORMAL clk_ctrl.ppf TRUE// Retrieval info: GEN_FILE: TYPE_NORMAL clk_ctrl.inc FALSE// Retrieval info: GEN_FILE: TYPE_NORMAL clk_ctrl.cmp FALSE// Retrieval info: GEN_FILE: TYPE_NORMAL clk_ctrl.bsf FALSE// Retrieval info: GEN_FILE: TYPE_NORMAL clk_ctrl_inst.v TRUE// Retrieval info: GEN_FILE: TYPE_NORMAL clk_ctrl_bb.v TRUE// Retrieval info: LIB_FILE: altera_mf// Retrieval info: CBX_MODULE_PREFIX: ON`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company :/*-----------------------------------------------------------------------------SDRAM接口说明：上电复位时，SDRAM会自动等待200us然后进行初始化，具体模式寄存器的设置参看sdram_ctrl模块。