西安交通大学组成专题实验报告

计算机组织与结构专题实验报告 MIPS 单周期处理器的设计学生姓名 赵荣建 专业班级计算机45班 学 号 ********** 指导教师 姜欣宁 完成日期 2017-05-09一.实验目的根据所学的CPU组成原理，自主设计一个MIPS32位的单周期处理器。

二.设计方案参照计算机组成原理教材上的MIPS32位处理器的工作原理。

1.构建数据通路取指令指令译码指令执行存储器访问结果写回取指周期：a.从指令寄存器PC输出端得到地址b.送地址到指令存储器IM地址端Ac.从指令存储器IM的数据端RD得到指令d.计算下地址：通过运算器，PC+4形成下地址，送回到PC。

2. .MIPS 寄存器集：定义了32个32位的寄存器3.MIPS三种指令格式：R-类型、I-类型和J-类型R-类型格式：* 所有指令操作吗OP都是0；特定操作由funct决定。

* 机器语言指令中，字段分配格式如上图；前两个寄存器rs、 rt 是源寄存器，rd是目的寄存器。

而在汇编语言格式中，第一个寄存器是目的寄存器。

如：add $t0，$s4，$s5 #[rd]=[rs]+[rt]，[t0]=[s4]+[s5];I-类型格式：* 指令含4个字段；op, rs, rt 和 imm* 有两个寄存器操作数和一个16位立即数操作数，一些指令中，rt也可作为源寄存器。

J-类型格式：* 有一个26位立即数操作数，扩展后形成目的地址。

4.算逻单元ALU 的设计ALU 工作原理图* 两级控制：通过系统控制器（Control ）B A和运算器控制器（ALU Control）产生ALU的控制信号：ALUoper* ALU控制信号对照表：5.单周期数据通路的构建1）构件：PC、指令存储器、寄存器文件RF和数据存储器； 2）取指令的过程：PC→IM: A/RD3）取源操作数的过程：IM:RD→RF:A1/RD1。

4）立即数的符号扩展的过程：IM:RD(Instr:15:0)→Sign Extend（15:0→Signimm31:0）；其中Signimm15:0=Instr15:0, Signimm31:16=Instr155）存储器地址计算：6）向寄存器文件写入数据RegWrite信号被置成1，写入过程在时钟周期最后的时钟上升沿完成。

7）形成PC的下地址指令占4个字节，字编址。

6.单周期控制器的构建控制单元基于指令中的opcode字段（31:26）、funct字段（5:0）产生控制信号；主译码的真值表。

见下图：7.完整的单周期MIPS处理器三.设计过程1.指令集设计R型指令指令序号指令译码结果（B）存储指令（H）$t0,$t1,$t2 100010<2> and$s3,$s4,$s5 000000 10100 10101 10011 0000010010002959824<3> or$s0,$s6,$s7 000000 10110 10111 10000 0000010010102d78025<4> xor$t3,$t4,$t5 000000 01100 01101 01011 00000100110018d5826<5> slt$t7,$t5,$t6 000000 01101 01110 01111 0000010101001ae782a<6> nor$t7,$t5,$t6 000000 01101 01110 01111 0000010011101ae7827<13> srl$t0,$s1,$t5 000000 10001 01101 01000 00000000010022d4002<14> sll$t0,$s1,$t2 000000 10001 01010 01000 00000000000022a4000<17> inc $t0,$t6 000000 01110 00000 01000 0000000001101c04003指令序号指令译码结果（B）存储指令（H）00000001<11> beq $t1,$t1,1 000100 01001 01001 000000000000000111290001 J型指令指令序号指令译码结果（B）存储指令（H）2.MIPS 32位单周期处理器结构设计CPU设计结构图如下：信号说明：a1:pc中的指令的地址送往IM去寻找指令a2：pc产生的下一条指令的地址a3：pc中指令的地址加4a4：取pc中指令的地址加4后的高六位b1：取J型指令的低26位b2：操作码字段高六位b3：第一个源操作数的寄存器地址，R型的21-25位，I型的21-25位b4：第二个源操作数的寄存器地址，R型的16-20位，I型指令的目的寄存器地址，16-20位b5：R型指令的目的寄存器地址，11-15位b6：I型指令的立即数，0-15位b7：R型指令的低六位，0-5位b8：b4和b5经二路选择器二选一b20：从IM中取出来的指令内容c1：I型指令将16位立即数扩展成32位c2：存入目的寄存器的内容c3：从源寄存器1中取出的内容c4：从源寄存器2中取出的内容c5：c1和c4二选一c6：ALU计算出的结果，也是读DM的地址c7：从DM中取出的内容c8、c9：针对不同类型的指令对进行pc值的修正的选择d1：功能选择信号e类信号：主操作控制信号，主要是各部件的读写控制信号核心模块说明：IM：按序号存放指令（共17条，其中lw指令执行了两次），在CPU启动时从<0>开始执行。

Rf：主寄存器，存放32个32位字，存储情况见下表（十进制表示，单数行是地址序号，双数行是对应的存储值）：<0> <1> <2> <3> <4> <5> <6> <7>7 6 5 4 3 2 1 0<16> <17> <18> <19> <20> <21> <22> <23>DM是对应的存储值）：<0> <1> <2> <3> <4> <5> <6> <7>8 7 6 5 4 3 2 1<16> <17> <18> <19> <20> <21> <22> <23>8 7 6 5 4 3 2 1<24> <25> <26> <27> <28> <29> <30> <31>tRf：测试模块，用于输出指令执行结果以检验是否正确；IRf：测试模块，用于输出当前执行的指令，与tRf搭配使用。

四.代码分析1.Add //完成分支指令的目标地址计算//library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity add isPort ( a: in STD_LOGIC_VECTOR (31 downto 0);b : in STD_LOGIC_VECTOR (31 downto 0);y : out STD_LOGIC_VECTOR (31 downto 0));end add;architecture Behavioral of add isbeginy<=a + b;-------将a和b相加赋给yend Behavioral;2.Add4 //完成PC+1(采用字寻址)的计算//library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity Add4 isport(pcin:in std_logic_vector(31 downto 0);pcout:out std_logic_vector(31 downto 0)); end Add4;architecture behave of Add4 isbeginprocess(pcin)beginpcout <= pcin + 1;---------pc值的修改end process;end behave;3.ALU //主运算器//library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity alu isPort (a1, b1 : in STD_LOGIC_vector(31 downto 0);alucontr: in STD_LOGIC_VECTOR (3 downto 0);result : buffer STD_LOGIC_VECTOR (31 downto 0);zero : out STD_LOGIC);end alu;architecture behave of alu is--signal d1: integer;--signal c1,f1: bit_vector(31 downto 0);beginprocess(a1,b1,alucontr)begincase alucontr iswhen "0000"=> result<= a1 and b1; ------and 与操作when "0001"=> result<= a1 or b1; -----or或操作when "0010"=> result<= a1 + b1; -----add 相加when "0011"=> result<= a1 xor b1; -----xor异或when "0100"=> result<= a1 nor b1; ------nor或非操作when "0101"=> result<=TO_STDLOGICVECTOR(to_bitvector(a1) sll conv_integer(b1)); ------Sll将a1向左移动b1数值位when "0110"=> result<= a1 - b1; -----sub减法when "1001"=> result<= a1 + 1; ------inc自增when "1010"=> result<= a1 - 1; -------dec自减when "0111"=> ----slt比较大小if(a1<b1)then result<=x"00000001";else result<=x"00000000";end if;when "1000"=> result<=TO_STDLOGICVECTOR(to_bitvector(a1) srl conv_integer(b1)); ------srl算术右移when others=> result<=x"00000000";end case;if(a1=b1)then --beq 判断分支指令是否转移当a1=b1时进行转移zero<='1';elsezero<='0';end if;end process;end behave;4.and_gate //与门，完成分支指令的判定//library ieee;use ieee.std_logic_1164.all;entity and_gate isport(a,b:in std_logic;c:out std_logic);end and_gate;architecture dataflow of and_gate isbeginc <= a and b;end dataflow;5.mux2_1 //5位二路选择器，由控制信号选择目的寄存器//library ieee;use ieee.std_logic_1164.all;entity mux2_1 isgeneric (width:integer:=5);Port ( d0,d1 : in STD_LOGIC_VECTOR (width-1 downto 0);s : in STD_LOGIC;y : out STD_LOGIC_VECTOR (width-1 downto 0));end mux2_1;architecture Behavioral of mux2_1 isbeginy<=d0 when s='0' else d1;---------s位0选择d0，若s为1选择d1 end Behavioral;6.Rf //32个32位寄存器组成的主寄存器，有预存//library ieee;use ieee.std_logic_1164.all;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity regfile isPort ( clk : in STD_LOGIC;we3 : in STD_LOGIC;------写使能信号ra1 : in STD_LOGIC_VECTOR (4 downto 0);------源寄存器1的地址ra2 : in STD_LOGIC_VECTOR (4 downto 0);------- 源寄存器2的地址wa3 : in STD_LOGIC_VECTOR (4 downto 0);--------目的寄存器地址wd3 : in STD_LOGIC_VECTOR (31 downto 0);-------写入目的寄存器的内容rd1 : out STD_LOGIC_VECTOR (31 downto 0);--------从源寄存器1中读出的内容rd2 : out STD_LOGIC_VECTOR (31 downto 0));-------从源寄存器2中读出的内容end regfile;architecture Behavioral of regfile is--subtype ramtype is std_logic_vector(31 downto 0);--type memory is array(0 to 31) of ramtype;type ramtype is array(31 downto 0) of STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL mem:ramtype:=--signal mem_initial:memory:=((x"00000000"),(x"00000001"),(x"00000002"),(x"00000003"),(x"00000004" ),(x"00000005"),(x"00000006"),(x"00000007"),(x"00000008"),(x"00000009"),(x"0000000a"),(x"0000000b"),(x"0000000c") ,(x"0000000d"),(x"0000000e"),(x"0000000f"),(x"00000000"),(x"00000001"),(x"00000002"),(x"00000003"),(x"00000004") ,(x"00000005"),(x"00000006"),(x"00000007"),(x"00000008"),(x"00000009"),(x"0000000a"),(x"0000000b"),(x"0000000c") ,(x"0000000d"),(x"0000000e"),(x"00000000"));---------预先存入32个寄存器的32位数beginprocess(clk) beginif (clk'event and clk='1') thenif (we3='1') then mem(CONV_INTEGER(wa3))<=wd3;------写使能信号为一，将目的寄存器的内容写入目的寄存器地址所对的单元内end if;end if;end process;process(ra1,ra2) beginif(conv_integer(ra1)=0)then rd1<=x"00000000";else rd1<=mem(conv_integer(ra1));------读出源寄存器1中的内容end if;if(conv_integer(ra2)=0) then rd2<=x"00000000";else rd2<=mem(conv_integer(ra2));--------- -读出源寄存器2中的内容end if;end process;end Behavioral;7.signext //符号拓展模块，将16位立即数拓展为32位，用于分支指令// library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity signext isPort ( a : in STD_LOGIC_VECTOR (15 downto 0);y : out STD_LOGIC_VECTOR (31 downto 0));end signext;architecture Behavioral of signext isbeginY<=X"0000"& a when a(15)='0' else x"ffff" &a;-----------16位数扩展为32位，若是正数，前面扩展0，负数则扩展1end Behavioral;8.PC //程序计数器，提供取指令地址//library ieee;use ieee.std_logic_1164.all;entity pc is --实体描述port(pc_in: in std_logic_vector(31 downto 0);clk,reset: in std_logic;pc_out: out std_logic_vector(31 downto 0));end pc;architecture behave of pc is --实体的行为描述--signal pc_temp: std_logic_vector(31 downto 0);beginF:process(clk)beginif (clk'event and clk = '1') thenif(reset='0')thenpc_out <= pc_in;end if;end if;end process;end behave;9.IM //指令存储器，已预存17条指令，由PC指出地址//library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;entity IM isport(--clk,read,write:in std_logic;address:in std_logic_vector(31 downto 0);--im_in:in std_logic_vector(31 downto 0);im_out:out std_logic_vector(31 downto 0));end IM;architecture behave of IM issubtype dword is std_logic_vector(31 downto 0);type memory is array(0 to 18) of dword;signal mem_initial:memory:=((x"02328020"),(x"012a4022"),(x"02959824"),(x"02d78025"),(x"018d5826" ),(x"01ae782a"),(x"01ae7827"),(x"8d300001"),(x"ad290001"),(x"8d300001"),(x"21280001"),(x"11290001" )--beq,(x"00000000"),(x"022d4002"),(x"022a4000"),(x"08000011")--J,(x"00000000"),(x"01c04003"),(x"01a04004"));-----------指令寄存器中预先存储了17条指令beginprocess(address)beginim_out<=mem_initial(conv_integer(address));end process;end behave;10.control //主控制器，用于译码指令输出控制信号// library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity controller isPort ( memtoreg,memwrite,memread : out STD_LOGIC;op : in STD_LOGIC_VECTOR (5 downto 0);branch,alusrc : out STD_LOGIC;regdst,regwrite : out STD_LOGIC;jump : out STD_LOGIC;aluop : out STD_LOGIC_VECTOR (1 downto 0));end controller;architecture Behavioral of controller issignal controls:STD_LOGIC_VECTOR (9 downto 0);beginprocess(op)begincase op iswhen "000000"=>controls<="0110000010";--R型when "100011"=>controls<="1101001000";-----lw(只有这种情况memread会是1)when "101011"=>controls<="0001010000";------swwhen "000100"=>controls<="0000110000";------beqwhen "001111"=>controls<="010*******";-------luiwhen "001000"=>controls<="010*******";------addiwhen "000010"=>controls<="0000000100";--J型转移when others =>controls<="----------";end case;end process;memread <=controls(9);regwrite<=controls(8);regdst <=controls(7);alusrc <=controls(6);branch <=controls(5);memwrite<=controls(4);memtoreg<=controls(3);jump <=controls(2);aluop <=controls(1 downto 0);----------对应e类型的信号，相应各位决定了是否进行寄存器读写，存储器读写等操作end Behavioral;11.ALU control //ALU译码器，用于完成运算器的功能选择//library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity alucontrol isPort ( funct : in STD_LOGIC_VECTOR (5 downto 0);aluop1 : in STD_LOGIC_VECTOR (1 downto 0);aluoper : out STD_LOGIC_VECTOR (3 downto 0)); end alucontrol;architecture Behave of alucontrol isbeginprocess (aluop1,funct) begincase aluop1 iswhen"00"=>aluoper<="0010";--add(for 1w/sw/addi/lui/j) when"01"=>aluoper<="0110";--sub(for beq)when others=>case funct iswhen "100000"=>aluoper<="0010";------addwhen "100010"=>aluoper<="0110";-----subwhen "100100"=>aluoper<="0000";-----andwhen "100101"=>aluoper<="0001";----orwhen "101010"=>aluoper<="0111";-----sltwhen "100110"=>aluoper<="0011";-----xorwhen "100111"=>aluoper<="0100";----norwhen "000000"=>aluoper<="0101";-----sllwhen "000010"=>aluoper<="1000";-----srlwhen "000011"=>aluoper<="1001";-----incwhen "000100"=>aluoper<="1010";-----decwhen others =>aluoper<="----";end case;end case;end process;end Behave;12.DM //数据存储器，有预存//library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dm isport(address: in std_logic_vector(31 downto 0);data_in: in std_logic_vector(31 downto 0);write,read: in std_logic;data_out: out std_logic_vector(31 downto 0);clock: in std_logic);end dm;architecture behave of dm istype ramtype is array(31 downto 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);SIGNAL sram:ramtype:=((x"00000001"),(x"00000002"),(x"00000003"),(x"00000004"),(x"00000005" ),(x"00000006"),(x"00000007"),(x"00000008"),(x"00000001"),(x"00000002"),(x"00000003"),(x"00000004"),(x"00000005") ,(x"00000006"),(x"00000007"),(x"00000008"),(x"00000001"),(x"00000002"),(x"00000003"),(x"00000004"),(x"00000005") ,(x"00000006"),(x"00000007"),(x"00000008"),(x"00000001"),(x"00000002"),(x"00000003"),(x"00000004"),(x"00000005") ,(x"00000006"),(x"00000007"),(x"00000008"));------------预先存储在DM中的数据，用于对实验的进行验证使用beginwrite_op:process(write,clock)beginif(clock'event and clock='1') thenif(read='0' and write='1') thensram(conv_integer(address))<=data_in;-------数据读入DMend if;end if;end process;read_op:process(read,write,sram,address)beginif (read='1' and write='0') thendata_out<=sram(conv_integer(address));------------数据从DM中读出elsedata_out<=(others=>'Z');end if;end process;end behave;13.mux2_11 //32位二路选择器，实例化4次完成不同的功能//library ieee;use ieee.std_logic_1164.all;entity mux2_11 isgeneric (width:integer:=32);Port ( d01,d11 : in STD_LOGIC_VECTOR (width-1 downto 0);s1 : in STD_LOGIC;y1 : out STD_LOGIC_VECTOR (width-1 downto 0));end mux2_11;architecture Behavioral of mux2_11 isbeginy1<=d01 when s1='0' else d11;end Behavioral;14.tRf //测试模块，用于输出指令执行结果以检验是否正确//library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity tregfile isPort ( tclk : in STD_LOGIC;twe3 : in STD_LOGIC;tra1 : in STD_LOGIC_VECTOR (4 downto 0);tra2 : in STD_LOGIC_VECTOR (4 downto 0);twa3 : in STD_LOGIC_VECTOR (4 downto 0);twd3 : in STD_LOGIC_VECTOR (31 downto 0);trd1 : out STD_LOGIC_VECTOR (31 downto 0);trd2 : out STD_LOGIC_VECTOR (31 downto 0));end tregfile;architecture Behavioral of tregfile istype ramtype is array(31 downto 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);SIGNAL mem:ramtype;beginprocess(tclk) beginif (tclk'event and tclk='1') thenif (twe3='1') then mem(CONV_INTEGER(twa3))<=twd3;--------向目的寄存器中写数据end if;end if;end process;process(tra1,tra2) beginif(conv_integer(tra1)=0)then trd1<=x"00000000";else trd1<=mem(conv_integer(tra1));-----读源寄存器1中的数据end if;if(conv_integer(tra2)=0) then trd2<=x"00000000";else trd2<=mem(conv_integer(tra2));------- 读源寄存器1中的数据end if;end process;end Behavioral;15.IRf //测试模块，用于输出当前执行的指令，与tRf搭配使用// library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Iregfile isPort ( iclk : in STD_LOGIC;iwe3 : in STD_LOGIC;ira1 : in STD_LOGIC_VECTOR (4 downto 0);ira2 : in STD_LOGIC_VECTOR (4 downto 0);iwa3 : in STD_LOGIC_VECTOR (4 downto 0);iwd3 : in STD_LOGIC_VECTOR (31 downto 0);ird1 : out STD_LOGIC_VECTOR (31 downto 0);ird2 : out STD_LOGIC_VECTOR (31 downto 0));end Iregfile;architecture Behavioral of Iregfile istype ramtype is array(31 downto 0) of STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL mem:ramtype;beginprocess(iclk) beginif (iclk'event and iclk='1') thenif (iwe3='1') then mem(CONV_INTEGER(iwa3))<=iwd3;end if;end if;end process;process(ira1,ira2) beginif(conv_integer(ira1)=0)then ird1<=x"00000000";else ird1<=mem(conv_integer(ira1));end if;if(conv_integer(ira2)=0) then ird2<=x"00000000";else ird2<=mem(conv_integer(ira2));end if;end process;end Behavioral;16.CPU //顶层模块//library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CPU isport(rout1,rout2: out std_logic_vector(31 downto 0);--测试clk1,ret: in std_logic);end CPU;architecture behave of CPU issignal a1,a2,a3,a4:std_logic_vector(31 downto 0);signal b1:std_logic_vector(25 downto 0);signal b2,b7:std_logic_vector(5 downto 0);signal b3,b4,b5,b8:std_logic_vector(4 downto 0);signal b6:std_logic_vector(15 downto 0);signal c1,c2,c3,c4,c5,c6,c7,c8,c9,b20:std_logic_vector(31 downto 0); signal d1:std_logic_vector(1 downto 0);signal e1,e2,e3,e4,e5,e6,e7,e8,e9,e10 :std_logic;signal f1:std_logic_vector(3 downto 0);--signal g1:std_logic_vector(27 downto 0);--------------具体信号见前面，都具体解释了component Add4port(pcin:in std_logic_vector(31 downto 0);pcout:out std_logic_vector(31 downto 0));end component;component pcport(pc_in: in std_logic_vector(31 downto 0);clk,reset: in std_logic;pc_out: out std_logic_vector(31 downto 0)); end component;-----------pc模块component IMport(--clk,read,write:in std_logic;address:in std_logic_vector(31 downto 0);--im_in:in std_logic_vector(31 downto 0);im_out:out std_logic_vector(31 downto 0));end component;-----------IM模块component addPort ( a: in STD_LOGIC_VECTOR (31 downto 0);b : in STD_LOGIC_VECTOR (31 downto 0);y : out STD_LOGIC_VECTOR (31 downto 0));end component;----------add模块component mux2_1generic (width:integer:=5);Port ( d0,d1 : in STD_LOGIC_VECTOR (width-1 downto 0); s : in STD_LOGIC;y : out STD_LOGIC_VECTOR (width-1 downto 0)); end component;-------------mux2_1模块component mux2_11generic (width:integer:=32);Port ( d01,d11 : in STD_LOGIC_VECTOR (width-1 downto 0); s1 : in STD_LOGIC;y1 : out STD_LOGIC_VECTOR (width-1 downto 0)); end component;component and_gateport(a,b:in std_logic;c:out std_logic);end component;------------- mux2_11模块component controllerPort ( memtoreg,memwrite,memread : out STD_LOGIC;op : in STD_LOGIC_VECTOR (5 downto 0);branch,alusrc : out STD_LOGIC;regdst,regwrite : out STD_LOGIC;jump : out STD_LOGIC;aluop : out STD_LOGIC_VECTOR (1 downto 0));end component;component regfilePort ( clk : in STD_LOGIC;we3 : in STD_LOGIC;ra1 : in STD_LOGIC_VECTOR (4 downto 0);ra2 : in STD_LOGIC_VECTOR (4 downto 0);wa3 : in STD_LOGIC_VECTOR (4 downto 0);wd3 : in STD_LOGIC_VECTOR (31 downto 0);rd1 : out STD_LOGIC_VECTOR (31 downto 0);rd2 : out STD_LOGIC_VECTOR (31 downto 0)); end component;-----------controller模块component signextPort ( a : in STD_LOGIC_VECTOR (15 downto 0);y : out STD_LOGIC_VECTOR (31 downto 0));end component;-------------- signext模块component aluPort (a1, b1 : in STD_LOGIC_vector(31 downto 0);alucontr: in STD_LOGIC_VECTOR (3 downto 0);result : buffer STD_LOGIC_VECTOR (31 downto 0);zero : out STD_LOGIC);end component;--------- alu模块component alucontrolPort ( funct : in STD_LOGIC_VECTOR (5 downto 0);aluop1 : in STD_LOGIC_VECTOR (1 downto 0);aluoper : out STD_LOGIC_VECTOR (3 downto 0));end component;-------------- alucontrol模块component dmport(address: in std_logic_vector(31 downto 0);data_in: in std_logic_vector(31 downto 0);write,read: in std_logic;data_out: out std_logic_vector(31 downto 0);clock: in std_logic);end component;--------------DM模块component tregfilePort ( tclk : in STD_LOGIC;twe3 : in STD_LOGIC;tra1 : in STD_LOGIC_VECTOR (4 downto 0):=("00001"); tra2 : in STD_LOGIC_VECTOR (4 downto 0):=("00000"); twa3 : in STD_LOGIC_VECTOR (4 downto 0):=("00001"); twd3 : in STD_LOGIC_VECTOR (31 downto 0);trd1 : out STD_LOGIC_VECTOR (31 downto 0);trd2 : out STD_LOGIC_VECTOR (31 downto 0));end component;component IregfilePort ( iclk : in STD_LOGIC;iwe3 : in STD_LOGIC;ira1 : in STD_LOGIC_VECTOR (4 downto 0):=("00001"); ira2 : in STD_LOGIC_VECTOR (4 downto 0):=("00000"); iwa3 : in STD_LOGIC_VECTOR (4 downto 0):=("00001"); iwd3 : in STD_LOGIC_VECTOR (31 downto 0);ird1 : out STD_LOGIC_VECTOR (31 downto 0);ird2 : out STD_LOGIC_VECTOR (31 downto 0));end component;begina4<=(a3(31 downto 26))&(b1);z1:Add4 port map(pcin=>a1,pcout=>a3);z2:and_gate port map(a=>e2,b=>e9,c=>e10);z3:mux2_1 port map(d0=>b4,d1=>b5,s=>e7,y=>b8);z4:mux2_11 port map(d01=>c4,d11=>c1,s1=>e6,y1=>c5);z5:mux2_11 port map --memtoreg (d01=>c6,d11=>c7,s1=>e3,y1=>c2);z6:mux2_11 port map(d01=>a3,d11=>c8,y1=>c9,s1=>e10);z7:mux2_11 port map(d01=>c9,d11=>a4,y1=>a2,s1=>e8);z8:regfile port map (clk=>clk1,we3=>e1,ra1=>b3,ra2=>b4,wa3=>b8,wd3=>c2,rd1=>c3,rd2=>c4);z9:signext port map (a=>b6,y=>c1);z12:pc port map (pc_in=>a2,pc_out=>a1,clk=>clk1,reset=>ret);z13:IM port mapim_out(25 downto 0)=>b1, im_out(31 downto 26)=>b2, im_out(25 downto 21)=>b3, im_out(20 downto 16)=>b4, im_out(15 downto 11)=>b5, im_out(15 downto 0)=>b6, im_out(5 downto 0)=>b7, address=>a1,im_out(31 downto 0)=>b20 );z14:add port map(a=>a3,b=>c1,y=>c8);z15:controller port map (memtoreg=>e3,memwrite=>e4,memread=>e5,op=>b2,branch=>e2,alusrc=>e6,regdst=>e7,regwrite=>e1,jump=>e8,aluop=>d1);z16:alu port map(a1=>c3,b1=>c5,alucontr=>f1,result=>c6,zero=>e9);z17:alucontrol port map (funct=>b7,aluop1=>d1,aluoper=>f1);z18:dm port map(address=>c6,data_in=>c4,write=>e4,read=>e5,data_out=>c7,clock=>clk1);z19:tregfile port map(tclk=>clk1,twe3=>e1,trd1=>rout1,twd3=>c2);z20:Iregfile port map(iclk=>clk1,iwe3=>e1,ird1=>rout2,iwd3=>b20);end behave;五.实验结果分析根据Rf、DM及IM存储情况，每一条指令执行结果为：结果11011 00001 1010 01001 00001 00000 1..100 00001 同<7> 序号<9> <10> <11> <13> <14> <15> <17> <18> 指令lw addi beq srl sll J inc dec 结果00110 00111 00111 00011 111000000 同<14> 00010 00001 仿真结果：加法add的实现：源寄存器1为10001，第17个，源寄存器2为10010，为第18个，17号寄存器里存放的是14,18号寄存器李存放的是13（可由上面查表获得数值），两数相加结果为27，应存放到10000,16号寄存器里。