A 10-Gbps CDR-DEMUX with LC delay line VCO in 0.18-spl mu-m CMOS

A10-Gb/s CDR/DEMUX With LC Delay Line VCOin0.18- m CMOSJonathan E.Rogers,Member,IEEE,and John R.Long,Member,IEEE Abstract—A monolithic10-Gb/s clock/data recovery and1:2demultiplexer are implemented in0.18-Fig.2.Early/late (bang–bang)phase detector-based CDR.variations as well as noise.In addition,an early/late PD pos-sesses intrinsic matching between the sampling and retiming phases,allowing operation at speeds where it is difficult to match the delay of a conventional analog phase detector to that of the retiming latch.It is this combination of robustness and speed that makes the bang–bang PD an excellent choice for an IC-based implementation.Fig.2shows a block diagram of the CDR-PLL implemented in this work.Data is compared to the voltage-controlled oscil-lator (VCO)clock at the loop input.If the falling clock edge occurs before the data transition (early),the early/late phase de-tector outputs avoltage,is thetuning gain of the VCO in Hz/V .A.System-Level DesignCharacterization of early/late (bang–bang)PLL behavior is described by Walker [2]and analysis of its application to SONET compatible CDR systems is found in the publication by Greshishchev [3].At the system level,design of the bang–bang CDR is reduced to the selection of two main system parameters.The first is the bang–bang frequencystep,defined by Walker [2]as(2)wherethe gain of the integral branchof theloop,is the unit interval or length of the bit period inseconds.This stability factor is the ratio of proportional and integral path gains with a correction for the amount of latency around the loop.A stability factor greater than unity ensures stability while the loop is not slew-rate limited in the phase domain.It should be noted that the bandwidth of the jitter transfer function (JTF)for a bang–bang loop is inversely proportional to the input jitter amplitude.A JTF for jitter amplitudes in excess of 1UI cannot be defined,as the loop will slip cycles when such large jitter in-puts are not tracked.To ensure that the loop JTF does not exhibit peaking,the stability factor is made large enough so that the pro-portional loop dominates during slew limiting (slope overload)at jitter inputs less than 1UI p-p.Therefore,this design imple-ments a large stability factor(.Thehalf-rate early/late phase detector compares the data falling edge with the phase of the quadrature clock.The phase detector pro-duces no output if a falling edge of the data is not present,oth-erwise an early or late pulse is produced.The phase informa-tion generated by the phase detector travels down two separate paths.The direct path to the oscillator provides high frequency proportional (bang–bang)control for the system.Through this tuning path,the early/late phase detector outputs translate into frequency stepsofROGERS AND LONG:10-Gb/s CDR/DEMUX WITH LC DELAY LINE VCO IN0.18-m CMOS transistors.In the quadrature sampling paths,where metastability and hysteresis are a con-cern,extra buffering is used.Also,the input latch of the first flip-flop is increased in size in order to improve performance. All samples enter the logic on the same clock edge simplifying the early/late logic.The phase detector pulses are retimed at the output of the phase detector in order to remove asymmetries in both amplitude and duration from the output pulses.Note that a drawback to these modifications is unequal loading of the in-phase and quadrature clock lines.Thus,care must be taken to avoid a static offset in the phase detector as this could cause a reduction in the residual jitter tolerance.Note that1:2demultiplexed data could be tapped off directly from early/late logic inputs A and B of Fig.4.However,a sep-arate1:2demux was used for the testchip to minimize loading of the phase detector latches,at the expense of possible phase alignment errors at the demux and a slight increase(10mW)in power consumption.III.C IRCUIT D ESCRIPTIONThe transistor and block level design of the10Gb/s CDR circuits are described in the following sections.The implemen-tation of the phase detector is examined first,followed by an in-depth description of the LC delay line VCO.A.Phase DetectorThe phase detector logic is implemented in resistively-loaded MOS current mode logic(MCML).This offers several advan-tages over conventional CMOS and other all-NMOS implemen-tations.First,it has a relatively low output impedance making it suitable for high-speed operation.MCML logic also benefits from reduced logic voltage swing as well as from the elimina-tion of lower mobility PMOS transistors compared to CMOS logic.The MOS equivalent of a bipolar ECL gate is not prac-tical,especially from a1.8-V supply due to attenuation of the signal by source followers and lack of headroom.Another benefit of using MCML is reduced switching-re-lated supply noise,due to the relatively constant current drawn from the power supply.For improved supply rejection,the gain stages and output buffers of the ring oscillator are implemented as MCML inverter/buffers.An additional benefit of this simple design is that the clocked phase detector elements can interface with the ring oscillator without level shifting or swing adjust-ment.The first goal of this design is to create a buffer which has the widest possible bandwidth,while still having enough gain.A minimum value of approximately2for the small-signal gain was chosen,otherwise the gate noise margin becomes unacceptable. Biasing of the circuit so that the large-signal switching speed approaches maximum performance is now considered. First,an appropriate voltage swing(1784IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.37,NO.12,DECEMBER2002Fig.4.Early/late(bang–bang)phase detector.the propagation delay time is not.When the differential pair isswitched so that transistor M1[see Fig.5(a)]is carrying all thebias current,M1will be in the active region(saturation)as longas voltage swingA/ROGERS AND LONG:10-Gb/s CDR/DEMUX WITH LC DELAY LINE VCO IN0.18-m CMOS technology.Maximizing the tracking bandwidth reduces the pattern-de-pendent jitter(hysteresis)caused by the phase detector latches.Increasing bandwidth by reducing the gain creates a tradeoff be-tween resistance to metastability and the tracking bandwidth.Tracking bandwidth is improved without increasing the likeli-hood of metastability by making device sizes in the input latches(e.g.,the master latch)significantly larger than the slave.Thisreduces the relative loading of the master by the slave latch.Thistechnique was used in the latches which sample the incomingfull-rate data in the1:2demux and on the quadratureclockFig.7.LC delay line oscillator.edges.The physical layout of the MCML latch is also shownin Fig.6.B.LC Delay Line OscillatorFig.7shows a block diagram of the two-stage LC delay lineVCO.The symmetry of this architecture ensures that precisein-phase(CKI)and quadrature(CKQ)clocks are generated.The5-GHz center frequency is tunable through external(EX),internal(IN),and high-frequency bang–bang(BB)inputs.The external tuning input is used to control the oscillator’scenter frequency in laboratory testing.This input could also beincorporated into a frequency-locked calibration loop to boostthe frequency acquisition range of the PLL.The internal tuningport is part of the integral tuning path,while the bang–bangtuning input completes the higher speed proportional tuningpath.Circuitry in the oscillator core is fully differential(withthe exception of the varactors)in order to reject supply noise.The LC delay line promotes frequency stability with supply,process,and temperature variations,without compromisingtuning speed.The oscillation frequency is determined by the total propa-gation time through the gain blocks and differential transmis-sion line stages.Load resistors of each MCML buffer match theoutput to the75-m,a conductor width of41786IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.37,NO.12,DECEMBER2002(a)(b)Fig.8.Balanced LC delay line.(a)Physical layout.(b)GEMCAP2model.TABLE IS IMULATED VCO SENSITIVITIESbecause the inductance seen in common mode is less than when differentially driven,and this places common-mode oscillations outside the bandwidth of the gain stages.The delay lines account for 43ps of delay time each at 5GHz or 86%of the total delay around the oscillator loop.Concentra-tion of the loop delay in these lines makes the VCO resistant to variations in power supply,temperature and process.Table I compares simulated sensitivities of the LC delay line VCO (in-cluding tuning circuitry)with an ring oscillator composed of identical MCML gain stages (without tuning capability)and comparable center frequency.Supply pulling is over an order of magnitude lower for the delay line oscillator,at 45MHz/V .In addition,sensitivity of the delay line oscillator to process (based on transistor variation only)and temperature variations is sub-stantially less than for a ring oscillator,mainly due to the domi-nance of inductance over capacitive parasitics in the loopdelay.(a)(b)Fig.9.NMOS varactor.(a)Varactor structure.(b)Varactor C –V curve.The simulated temperature sensitivity includes back-end metal and substrate resistivity effects,which dominate temperature de-pendence of the on-chip delay line.In addition,it is important to note that the tuning response time of the delay line oscillator is on the order of the clock period (comparable to a conventional ring oscillator),which is important in the bang–bang PLL ap-plication.GEMCAP2[8]is used to derive a SPICE-compatible lumped-element model for the delay line [see Fig.8(b)]and refine the oscillator design.Each pi-section of this model corresponds to an individual conductor segment of the delay line,with circuit elements representing the self-inductance,frequency-dependent resistances (e.g.,skin effect),capacitance to the substrate as well as the capacitance and loss of the substrate itself.Also modeled is the capacitance and mutual magnetic coupling between wind-ings.These elements are then combined to form the multi-seg-ment delay line model which is employed in transient simula-tions of the oscillator.The remaining capacitance required for oscillation at 5GHz is added by inversion-mode NMOS varactors at each gain stage input (a high impedance node).Integral loop tuning range is designed at 32.5MHz/V ,and the (simulated)voltage swing at the clock buffer inputs is 2.5V differential,which consumes extra power but improves switching speed of the MCML logic.The varactors were selected based on practical issues related to the fabrication technology [9].Fig.9shows a cross section and the tuning characteristics of the inversion mode NMOS var-actor used in the VCO.This varactor was chosen because the four-terminal NMOS transistor model in the IC design kit could be used for circuit simulations without modification.IV .E XPERIMENTAL R ESULTSTable II summarizes the measurements for the LC delay line oscillator.Phase noise spectral density of the VCO runningROGERS AND LONG:10-Gb/s CDR/DEMUX WITH LC DELAY LINE VCO IN0.18-103dBc/Hz, which falls to135dBc/Hz).The difference is primarily due to frequency multiplication between the reference source (2.5GHz)and locked VCO(5GHz),which adds a minimum of6dB to the phase noise.The fabricated oscillator has a measured center frequency of 4.45GHz(10%slower than predicted by simulations).Subse-quent measurements of individual component test structures re-vealed that the frequency shift is caused by unanticipated loss and delay between the oscillator gain stages.Excessive resistive losses in the top metal,inaccuracy in the modeling of parasitic capacitances,and stray inductance between the delay line and gain stages(which is not extracted from the physical layout for simulation)all contribute to this error.The measured capaci-tance per unit length and resistance per unit length of the delay line are45%and28%higher,respectively,than those derived from the same simulation.This result exposes a sensitivity of the circuit to the absolute loss and capacitance in the delay line and,more importantly,sensitivity to variations in these param-eters over process.Work is ongoing to analyze the architecture for variations in the properties of the backendmetal/dielectric Fig.12.CDR clock and data waveforms(10-Gb/soperation).Fig.13.Measured CDR jitter tolerance.TABLE IIICDR SUMMARYstack and the actual magnitude of these variations.This charac-terization work is aimed at improving the accuracy of the CAD models thereby allowing better correlation between the simula-tion and measurement.Nevertheless,it is important to note that oscillators from two separate fabrication runs showed only0.2% variation in VCO center frequency.The measured external tuning range and bang–bang fre-quency step(varied using the BB input)are125and2.5–5MHz, respectively.Characterization of this varactor using a separate test structure showed40%less capacitance variation than expected,thus explaining the smaller tuning ranges observed.A VCO center frequency close to4.98GHz is needed in order to conduct full-speed testing of the CDR including bit error rate testing(BERT)at the SONET OC-192rate(9.953Gb/s).A non-invasive technique for adjusting the oscillation frequency was1788IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.37,NO.12,DECEMBER2002Fig.14.A10-Gb/s CDR testchip micrograph.developed so that a design iteration is avoided,thereby allowing the prototype to be fully characterized.The method is shown schematically in Fig.11,where a metal plate is placed in close proximity to the delay line using a micro-manipulator.Current induced in the metal plate reduces the self-inductance of the delay lines.Since delay between oscillator stages is proportional to line inductance,the frequency increases when the inductance is lowered.However,the plate must be placed within approxi-mately10m from Fig.11)to beeffective.Conductivity of the metal plate is important(i.e.,gold or a similar metal is used),as resistive losses actually increase the signal delay and slow down the oscillator.An unwanted sec-ondary effect is additional interwinding capacitance that results from placing another conductor in close proximity to the delay line,which acts to reduce the oscillation frequency.The induc-tive effect dominates,however,with the net result that the center frequency is adjustable from4.45to5.5GHz with negligible ef-fect on phase noise.The oscilloscope eye pattern of Fig.12is measured in re-sponse to10-Gb/s PRBS input data(2output buffers used for testing.Note that a1:8or1:16demulti-plexer would be used in a typical application,which relaxes the bandwidth requirements for off-chip buffering of the recovered data.Measured jitter transfer,generation,and tolerance all meet the SONET OC-192requirements(measured jitter of8ps p-p),with the exception of the small residual jitter tolerance.The jitter tolerance exceeds specifications at low jitter frequencies but is very close to the SONET mask at higher frequencies(see Fig.13).Poor electrical contact from probes to the chip,phase error between the quadrature clocks,and mismatch between the demux and PD latches are likely sources of degradation in the jitter performance at higher frequencies.Poor electrical contact is partly due to wear caused by mechanical scrubbing of the pad by the probe tip.Repeated contacts were needed to trim the os-cillation frequency before measuring the jitter tolerance,which caused significant wear of the pad metal and inconsistent elec-trical contacts.CDR performance is summarized in Table III.A photomicrograph of the1.9microstrip.The pad configuration used was dictated by the RF on-wafer probes used for test.In order to increase the isolation between the oscillator and the data path circuits,power supplies are kept separate.The layout also includes an extensive bottom metal ground plane which provides the reference plane for the microstrips as well as increasing the capacitance from substrate to ground.The IC consumes285mW from a1.8-V supply(not including50-ROGERS AND LONG:10-Gb/s CDR/DEMUX WITH LC DELAY LINE VCO IN0.18-。