Burg算法在雷达测速中的应用
Burg算法(word文档良心出品)
功率谱估计的古典算法与现代算法的比较——选取周期图法与Burg算法为例现代信号分析中, 对于常见的具有各态历经的平稳随机信号, 不可能用清楚的数学关系式来描述, 但可以利用给定的N 个样本数据估计一个平稳随机信号的功率谱密度叫做功率谱估计(PSD)。
功率谱估计可以分为经典功率谱估计(非参数估计)和现代功率谱估计(参数估计)。
一、古典功率谱估计古典功率谱估计是将数据工作区外的未知数据假设为零, 相当于数据加窗经典功率谱估计方法分为: 相关函数法(BT 法)、周期图法以及两种改进的周期图估计法。
1、相关法相关法是以相关函数为媒介来计算功率谱的，所以又叫间接法，它的理论基础是维纳--辛钦定理。
先对数据工作区外的未知数据赋值为零，再由序列x(n)估计出自相关函数R(n)，最后对R(n)进行傅立叶变换, 便得到x(n)的功率谱估计。
2、周期图法周期图法是由获得的N点数据构成的有限长序列直接求fft得其频谱，取频谱幅度的平方再除以N，以此作为对x(n)真实功率谱的估计。
3、改进的周期图法改进的周期图法的主要途径是平滑和平均。
平滑是用一个适当的窗函数与算出的功率谱进行卷积，使谱线平滑，这种方法得出的谱估计是无偏的，方差也小，但分辨率下降；平均就是将截取的数据段再分成L个平均的小段，分别计算功率谱后取功率谱的平均，当L趋于无穷大的时候，L个平均的方差趋于零，可以达到一致谱估计的目的。
由于存在旁瓣，会产生两个后果：一是功率谱主瓣能量泄露到旁瓣使谱估计的方差增大，二是与旁瓣卷积后得到的功率谱完全属于干扰，严重情况下，强信号与旁瓣的卷积可能大于弱信号与主瓣的卷积，使弱信号淹没在强信号的干扰中无法检测出来。
这是古典法谱估计的主要缺点，即便是改进的周期图法也无法克服分辨率低的缺点。
我们从中选取周期图法作比较，其算法实现如下：Fs=600; %采样频率n=0:1/Fs:1;%产生含有噪声的序列xn=cos(2*pi*40*n)+cos(2*pi*90*n)+0.1*randn(size(n));n=1:length(xn);figure(1);subplot(2,1,1);plot(n,xn);window=boxcar(length(xn));%矩形窗nfft=1024;[Pxx,f]=periodogram(xn,window,nfft,Fs);subplot(2,1,2);plot(f,10*log10(Pxx));得到的图形为：二、现代谱估计参数模型法是现代谱估计中的主要内容，AR 模型参数的求解有三种方法：自相关法、Burg 递推算法和改进协方差法。
一种基于Burg谱估计和FFT的频偏估计方法
一种基于Burg谱估计和FFT的频偏估计方法陈伟;邢依依;刘梦婷【摘要】针对星间链路通信中常用的BPSK、QPSK、UQPSK和64QAM等调制信号的载波频偏估计问题,提出了一种基于Burg谱估计和FFT的通用频偏估计方法.采用Burg谱估计方法对信号进行粗频偏估计,补偿该频偏后得到含有较小残留频偏的信号;并进行改进的四次方非线性变换,去除调制信息;再利用FFT估计出较高精度的残留频偏值.仿真结果表明,该方法估计精度高、范围大.【期刊名称】《电子科技》【年(卷),期】2016(029)003【总页数】4页(P160-163)【关键词】星间链路通信;频偏估计;Burg谱估计;FFT【作者】陈伟;邢依依;刘梦婷【作者单位】西安电子科技大学电子信息攻防对抗与仿真重点实验室,陕西西安710071;西安电子科技大学电子信息攻防对抗与仿真重点实验室,陕西西安710071;西安电子科技大学电子信息攻防对抗与仿真重点实验室,陕西西安710071【正文语种】中文【中图分类】TN927+.3AbstractA general frequency offset estimation method of BPSK,QPSK,UQPSK and 6 4QAM signals based on Burg spectrum estimation and FFT is proposed tosolve the carrier frequency offset estimation of common signals in inter sat ellite link communication.First,the coarse frequency offset estimation is obt ained by using the Burg spectrum estimation method,and the signal of the residual frequency offset is obtained after the compensation of the freque ncy offset.Then the improved fourth non-linear transformation is used to remove modulated information.Finally,the residual frequency offset value is estimated by FFT.Simulation results show that this method is of high accuracy and wide acquisition range. Keywordsinter satellite link communication;frequency offset estimation;Burg spectru m estimation;FFTMPSK和MQAM这两类调制信号以其高的频带利用率和良好的抗噪性能,目前已在卫星无线通信系统中得到广泛应用。
基于BURG算法的谱估计研究和MATLAB实现毕业论文
毕业设计（论文）题目：基于BURG算法的谱估计研究及其MATLAB实现目录一、毕业设计（论文）开题报告二、毕业设计（论文）外文资料翻译及原文三、学生“毕业论文（论文）计划、进度、检查及落实表”四、实习鉴定表XX大学XX学院毕业设计（论文）开题报告题目：基于BURG算法的谱估计研究及其MATLAB实现机电系电子信息工程专业学号：学生：指导教师：（职称：讲师）（职称：）XXXX年XX月X日英文原文Parametric spectral estimation on a single FPGAABSTRACTParametric, model based, spectral estimation techniques can offer increased frequency resolution over conventional short-term fast Fourier transform methods, overcoming limitations caused by the windowing of sampled, time domain, input data. However, parametric techniques are significantly more computationally demanding than the Fourier based methods and require a wider range of arithmetic functionality; for example, operations such as division and square-root are often necessary. These arithmetic processes exhibit communication bottleneck and their hardware implementation can be inefficient when used in conjunction with multipliers. A programmable, bit-serial, multiplier/divider, which overcomes the bottleneck problems by using a data interleaving scheme, is introduced in this paper. This interleaved processor is used to show how the parametric Modified Covariance spectral estimator can be efficiently routed on a field programmable gate array for real-time applications.1. INTRODUCTIONDue to its ease of hardware and software implementation the shortterm fast Fourier transform(STFFT)is widely used for spectral estimation and is known as the conventional method. However, the technique has drawbacks in terms of spectral resolution and accuracy caused by the finite length of the input data sequence used. Windowing of input data causes spectral broadening and Gibb’s phenomenon of spectral leakage can mask the weaker frequency components of the true power spectral density(PSD)[1]. These unwanted effects can be reduced by using longer data sequence lengths, so that the transformed signal becomes a better representation of the infinite data sequence, but in real life this usually is not feasible as the characteristics of the input data may change with time. Over short periods of time the data signals can often be assumed to exhibit wide-sense stationarity, where the signal characteristics are assumed approximately constant but the spectral resolution is therefore limited. In attempts to improve the PSD estimation, windowing functions, Bartlett or Hanning for example, can be used to reduce side-lobe levels but these lower spectral resolution by broadening the main lobe of the PSD[2].Model based, parametric spectral estimation techniques can alternatively be used, where the unrealistic assumption that data is zero outside the window of interest is dropped[1]. Either knowledge of the underlying process or reasonableassumptions about the nature of the unobserved data are used to improve frequencyresolution over the conventional approaches. The computational burden of suchprocessors is however much higher than the STFFT and arithmetic functions such asdivision and square-root often become necessary. In the division and square-rootnon-restoring algorithms there is an inherent dependency that the result bits mustbe computed in a most significant bit(MSB)first manner, with the computation of abit directly dependent upon the result of the previous one[3]. This interdependencymakes it difficult to efficiently realize such arithmetic functions in hardware,and implementations are usually much slower than other basic functions such asmultiplication, addition and subtraction. Communication bottlenecks can thereforeeasily occur in systolic arrays where different types of processors are interconnected.The difficulties with hardware implementation of parametric spectral estimatorshave led to a preference of software implementation on homogeneous DSP networks[4].However, high levels of processing capacity have not been fully reflected in systemthroughput since the increased communication incurred as a result of parallelismis constrained by communication bus performance. This restricts the range ofproblems that can be computed in realtime and the software approach may sometimesbe inadequate for real-time spectral estimation.In this paper, hardware implementation of a parametric spectral estimator isaddressed. A bit-serial processor capable of division and inner product stepcomputation is developed by combining separate processors for these functions. Thedesign uses a high level of pipelining so that division can be computed at a highrate and multiplication is performed on a MSB first data stream, eliminating thebottleneck problem. The high level of pipelining allows many independentcomputations to be performed simultaneously or interleaved. The use of theinterleaving scheme is demonstrated by implementing the design of a ModifiedCovariance type of parametric spectral estimator, to produce a field programmablegate array(FPGA)based system for the spectral analysis of Doppler signals fromultrasonic blood flow detectors.2. MODIFIED COVARIANCE SPECTRAL ESTIMATIONThe model order p=4 Modified Covariance(MC)spectral estimator, proven to beoptimally cost efficient for the blood flow application where mean velocity and flowdisturbance are of interest[5], involves solving the following linear system ofcovariance matrix equations:(1) where each element j i C,is obtained from:∑∑-=--=+•++-•--=110,)()1(21N p n p N n ji j n i n j n i n N C(2) for a window of length N data samples. The k aˆ filter parameter estimates are obtained by solution of the linear system(1), using the Cholesky, forward elimination and back substitution algorithms. The signal white noise varianceestimate, 2ˆσis calculated as: k p k k c a c ,010,02ˆˆ•+=∑=σ (3)and the power spectral density(PSD), )(ˆnMC f P , is obtained from: 2122221ˆ)(ˆ)(ˆ∑=-=+==p k f j k k n n MC ne z z af A f P πσσ(4)Hence, the MC spectral estimator may be partitioned onto four different programming modules:•CMR-calculation of the elements of the covariance matrix and right-hand side vector, 5N multiply accumulates taking into account matrix symmetry.•Cholesky-solution of the linear system of equations, 6 divisions and 10 inner step products for non-square-root Cholesky, 4 divisions and 12 inner step products for solving triangular systems.•WNV-calculation of the white noise variance, 4 multiply accumulates.•PSD-computation of the power spectral density, 4N inner step products for a zero padded DFT, N multiplications to find absolute value of DFT and N/2 divisions for the PSD.The number of samples, over the fixed time duration window of 10ms, is required to be either 64, 128, 256 or 512 depending on Doppler signal conditions. Implementation of the algorithm in Matlab software proved to be in excess of a factor of 310times too slow for real-time operation and that a performance of up to 13.5 MFLOPS/s is required[4]. Execution times of MC algorithm implementation using various topologies of Texas Instruments TMS320C40 DSPs with T8 transputers as routers have also fallen short of the real-time requirements, where processing time is over 150ms too long in the worst case[4][6]. Use of a single DSP in a PC hosted system has been shown sufficient for the smaller N but the specification of N=512 could not be achieved[4], thus prompting consideration of the hardware approach.3. BIT-SERIAL INTERLEAVED PROCESSORStudy of word-parallel systolic implementations of the MC method has shown the method to provide more than adequate throughput for the specified real-time blood flow application but the cost of such a system is very high in terms of arithmetic units, communication burden and control complexity[7]. For example, a systolic array processor for non-square root Cholesky decomposition[8] requires 13 processing elements(PEs), each PE having 2 to 6 ports of either m(single precision)or 2m(double precision)lines, and control is necessary to reverse data streams before back substitution. An alternative way to approach the hardware design involves consideration of bit-serial processing techniques.The nature of multiplication algorithms normally involve the computation of least significant bits(LSBs)first and bit-serial multipliers reflect this in their output ordering. Conversely, division algorithms such as non-restoring are MSB first in nature[9]. Computation of each quotient bit can be performed from m controlled add subtract(CAS)operations, the decision on whether to add or subtract being taken given the result of the previous bit computed(except on the first operation where the signs of the input operands are used to decide). Allowing carries to ripple through therefore leads to a propagation delay greater than m CAS cells. In a bit-serial multiplier, the delay between successive bits being output is likely to be around a single full adder(FA)delay, leading to a maximum clock frequency approximately m times higher and a communication bottleneck with the divider. The clockrate of the divider can be increased to a similar maximum rate as the multiplier by pipelining the carries in each individual CAS stage. However, this means that each output bit is then available only once in every m clock cycles. There is also the problem that data streams must be reversed between multipliers and dividers. One possibility is to use registers and extra control logic to reorder the bit stream from the divider but the operation time is still limited.The efficiency of the divider with the pipelined carry can be greatly improved by using the redundant slots between the output of successive bits to perform other separate divisions. The bit-serial/word-parallel divider shown in[3]allows m+1 individual divisions to be performed simultaneously or interleaved. This decreases the mean division operation time to achieve similar performance to a bit-serial multiplier but there is still the problem of data stream matching when interfacing such devices. One way to tackle this problem is to redesign the multiplier so that it works on a MSB first data stream, rather than storing and reordering the divider outputs which increases latency and control requirement[10]. MSB first multiplication, first demonstrated by McCanny et al.[11], shows it is possible to perform multiplication on positive numbers by summing partial products(PPs)inreverse order to the norm. This also requires inclusion of an MSB first addition unit to ensure that output carries from the PPs are added into the final product. Larsson-Edefors and Marnane[12], extend the concept of MSB first multiplication to the two’s complement number system and show bit-serial architectures for this application. In order to match the divider bit-streams exactly to the multiplier bit-streams it is then just a matter of inserting extra delays along the FA sum pipeline so that the addition of PPs from a number of different multiplications can be performed simultaneously as shown by Bellis et al[13].Study of the bit-serial interleaved divider and multiplier reveals that both architectures show a large degree of similarity. Both work in load/operational phases; the loading networks for the divisor and multiplier both consist of m+1 delay feedback SISO registers and the FA sum/carry pipelines are alike. Both designs also require MSB first, half adder(HA)cell, addition stages; the divider requires m PEs, for 1’s complement error correction which occurs for negati ve dividends, and the multiplier requires m-1 HA PEs to add the output carries from the PPs. Therefore, it is possible to combine the two designs to make a programmable bitserial device which allows m+1 computations to be simultaneously interleaved, as shown in figure 1.The processor has two mode selection inputs DIVi and SUBi, which control four modes of operation i i Y Z X /0±= or i i i Y X Z Z •±=0 where i Z and 0Z are both double precision. Ldi is the load/operational mode select signal for the storage of i Y and i Z over the first m(m+1) clock cycles. Ldi switches into operational mode over the next m(m+1) clock cycles where the remaining data is input and the bulk of the computation is performed in the FA array. All control signals are fully pipelined similarly to the data, allowing the shortest possible block pipeline period of 2m(m+1) clock cycles and continuous input/output of data(i.e. while one block set of m+1 computations are being output, the next block set may be loaded in). The pipeline also allows independent functionality between each of the separate interleaves and on the same interleave a division may immediately follow an inner step product computation and vice-versa.4. INTERLEAVED PROCESSOR BASED MODIFIED COVARIANCE SYSTEMCost-bene fit analysis on systolic array implementation of the CMR and Cholesky sections of the MC spectral estimator shows that a 12 bit fixed point word-length is suf ficient for these computations[7]. Using the bit-serial processor with a 12 bit word-length results in the capacity for interleaving 13 computations.On interleaves 0 to 4 the CMR multiplications are performed over N consecutive block sets, such that the products i n n x x +• are produced on interleave)40(≤≤i i andblockset )10(-≤≤N n n . A bit-serial systolic array provides the correct input data sequencing from consecutive Doppler signal samples and a separate MSB first double precision accumulator, whose architecture is similar to that of HA section in figure1, computes the covariance matrix elements, which are then stored in RAM. The system for computing the CMR calculation is shown in figure 2.The entire Cholesky, forward elimination, back substitution and WNV computations are performed on interleave 5 on the system shown in figure 3. Here division and inner product step computation are necessary. Once the covariance matrix elements are stored in the dual port RAM after block set N the Cholesky decomposition can commence on interleave 5 while in parallel the CMR computation on the next set of data can be processed on interleaves 0 to 4. A ROM block controls the addressing of the dual port RAM for retrieval of stored data to go onto the processor inputs and storage of the processor results. To achieve good dynamic resolution for the low word-length used, a systolic array scaling module is included between the RAM and the processor, whose scaling factors are also produced by the ROM controller along with the mode control. Overall timing in the system is controlled by three counters, qi(range 0 to 12),qb(range 0 to 23) and qw(range 0 to N)corresponding to the interleaves, bit-position and input word.A zero padded point DFT is computed on interleaves 6, 7, 8 and 9. This is basically amatrix vector multiplication and is computed by using the processor in inner product step mode. The system for this section consists of a ROM to provide storage of the twiddle factor matrix n W , another ROM to control the addressing of the twiddle factors for a particular qw and 4 registers which continuously recirculate the filterparameter results(n aˆ)from the Cholesky decomposition stage. On interleave 6 thereal and imaginary parts of the first set of products 1ˆa W i N • are alternately formed.Using a single flip-flop delay the results of these computations are then fed backinto the i Z input of the interleaved processor to be added to the products 2ˆaW i N • and the DFT is built up in this way. The dynamicrange of the PSD computation is quite high compared to the rest of the system, therefore, at this stage a floating point representation of the DFT results is taken using a systolic based conversion circuit. PIPO registers are used to store the 6 bit exponents of the real and imaginary parts of the DFT, whose squares are computed on interleave 10. On interleave 11 the absolute value of the DFT is computed. The maximum of each pair of real and imaginary results from interleave 10 is fed to the i Z input while the other value is piped into the i Y to be appropriately scaled by the difference in the two squared exponents appearing on the i X input. The PSD is then computed on interleave 12, involving N/2 divisions of the WNV formed on interleave 5 with the absolute values from interleave 11. The exponents of the PSD are then easily derived from the exponents of the DFT results.5. CONCLUSIONThis paper has proposed a bit-serial interleaved processor which can be programmed for use in division or inner product step computations. The interleaving idea was introduced in order to perform bit-serial division at the same high clock rate as multiplication without resorting to carry look-ahead schemes to remove the communication bottleneck. The result is a high throughput processor which is cost ef ficient in terms of VLSI implementation, since communication between PEs in the linear array is localised and control is very simple. An application in parametric spectral estimation, namely implementation of theModi fied Covariance spectral estimator, which makes full use of the interleaving scheme, was described. This system has been programmed and simulated using VHDL. Synthesis was targeted to exploit the resources of a Xilinx XC4036EX-2 FPGA. This type of FPGA has dual port RAM capability, where a 16x1 bit dual port RAM can be implemented in a single con figurable logic block (CLB). A dual port RAM cell is an area ef ficient method to implement a 13 or 14 bit SISO register, as used in the interleaving process. Such registers would otherwise have to be implemented using the pairs of flip flops in each CLB, i.e.7 CLBs. CLBs can also be con figured as ROM blocks which are useful for generating the address signals in the Cholesky and PSD modules, and for storage of the DFT twiddle factors. The processor design exhibits mostly localised communication to make use of the fast routing resources between nearest neighbours in the FPGA’s CLB matrix and enable high speed operation. Timing analysis of the FPGA layout shows that the maximum processor clock frequency of 35MHz allows real-time spectral estimation to be performed for the speci fied constraints. There-programmable aspect of the FPGA is also useful; rather than designing control logic to switch between the different values of N, which uses resources and is likely to slow clock speed, a different bit-stream can be downloaded for each N. This idea can also be extended for changing to higher model order estimations where otherwise it would be difficult to paramete rise p in such a system.6. REFERENCES[1] S. M. Kay, Modern Spectral Estimation-Theory & Application. Prentice Hall, 1988.[2] M. Kassam, K. W. Johnston, and R. S. C. Cobbold, “Quantitative estimation of spectral broadening for the diagnosis of carotid arterial disease: Method and in vitro results, ”Ultrasound in Medicine and Biology, vol.11, pp. 425–433, 1985.[3] W .P. Marnane, S. J. Bellis, and P. Larsson-Edefors, “Bitserial interleaved high-speed division, ”Electronics Letters, vol. 33, pp. 1124–1125, June 1997.[4] M. M. Madeira, S. J. Bellis, M. G. Ruano, and W. P. Marnane, “Configurable processing for real-time spectral estimation, ”in Preprints of AARTC98,pp. 209–214, 1998.[5] M. G. Ruano and P. J. Fish, “Cost/benefit criterion for selection of pulsed Doppler ultrasound spectral mean frequency and bandwidth estimation, ”IEE E Transactions on Biomedical Engineering, vol. 40, no. 12, pp. 1338–1341, 1993.[6] M. G. Ruano, D. F. G. Nocetti, P. J. Fish, and P. J. Fleming, “Alternative parallel implementationsof an AR-modified covariance spectral estimator for diagnostic ultrasound blood flow studies, ” Parallel Computing,vol. 19, no. 4, pp. 463476, 1993.[7] S. J. Bellis, P. J. Fish, and W. P. Marnane, “Optimal systolic arrays for real-time implementation of the Modified Covariance spectral estimator, ”Parallel Algorithms and Applications, vol .11, no. 1-2, pp. 71–96, 1997.[8] S. J. Bellis, W. P. Marnane, and P. J. Fish, “Alternative systolic array for non-square-root Cholesky decomposition, ”IEE Proceedings: Computers and Digital Techniques, vol. 144, pp. 57–64, Mar. 1997.[9] K. Hwang, Computer Arithmetic: Principles Architecture and Design. John Wiley & Sons, 1979.中文译文单一FPGA上的参数谱估计摘要参数化谱估计模型技术可以提供针对传统的短期快速傅里叶变换提高频率分辨率的方法，克服了窗口采样，时域，输入数据造成的限制。
基于广义Burgers方程的超声速客机远场声爆高精度预测方法
基于广义Burgers方程的超声速客机远场声爆高精度预测方法乔建领; 韩忠华; 丁玉临; 池江波; 孟冠宇; 宋笔锋; 宋文萍【期刊名称】《《空气动力学学报》》【年(卷),期】2019(037)004【总页数】12页(P663-674)【关键词】超声速客机; 声爆预测; 广义Burgers方程; 声射线方法; 大气风【作者】乔建领; 韩忠华; 丁玉临; 池江波; 孟冠宇; 宋笔锋; 宋文萍【作者单位】西北工业大学航空学院超声速客机研究中心西安 710072; 西北工业大学航空学院气动与多学科优化设计研究所西安 710072【正文语种】中文【中图分类】V211.30 引言超声速客机是未来民机发展的重点方向之一。
早在20世纪中后期,英法和前苏联就研制了以“协和”和“图-144”为代表的第一代超声速客机。
然而其商业运营以失败告终,究其原因,严重的声爆问题是造成其最终停止商业运营的重要原因之一。
在吸取第一代超声速客机失败教训的基础上,近年来,美国、欧洲和日本等掀起了新一代环保型超声速客机的研究热潮,并制定了一系列研究计划[1-3](如图1为美国波音公司的“N＋2”代超声速客机方案),重点突破以声爆预测及其抑制为核心的一系列关键科学与技术问题。
图1 波音公司拟研发的下一代超声速客机[4]Fig.1 The next generation of supersonic transport proposed by Boeing[4]声爆问题是制约新一代超声速客机研制的核心关键问题。
远场声爆的高精度预测是新一代超声速客机设计中声爆评估和优化设计的基础和前提,是其中核心的关键技术之一。
目前,国内外发展的声爆预测理论和方法主要有修正线化理论[5-7]、简化声爆预测方法[8-9]、CFD全流场求解方法[10-12]、近场CFD计算耦合远场传播方法[13-16]。
由于受到计算量和计算精度的限制,近场CFD与远场传播相结合的方法,成为了最主要的声爆高精度预测方法。
基于小波降噪的雷达时频信号互相关测速算法
基于小波降噪的雷达时频信号互相关测速算法作者：李佳曹林王东峰付冲来源：《现代电子技术》2020年第09期摘; 要：为提高基于FMCW体制的双波束车流量雷达的测速精度，对其信号特征进行分析，结合Burg和广义互相关理论，提出基于小波降噪的时频信号互相关测速算法（CC⁃BWT）。
首先，利用最大熵功率谱估计的Burg方法得到雷达回波的频谱信息，通过CFAR检测出目标车辆后提取车辆的时频信号;然后，对时频信号进行小波分解，以改进的阈值函数作为降噪依据进行信号重构，之后两路信号做互相关，估计出时延，从而测得车辆速度。
结合仿真和实测数据，并与相位法和双谱法进行对比，验证了该算法的测速准确度达到96%以上且算法鲁棒性好。
关键词：互相关测速; 时频信号提取; 小波降噪; 最大熵谱估计; 信号重构; 车辆测速中图分类号： TN957.51⁃34; ; ; ; ; ; ; ; ; ; ; ;文献标识码： A; ; ; ; ; ; ; ; ; ; ; ; ;文章编号：1004⁃373X（2020）09⁃0014⁃07Wavelet denoising based cross⁃correlation velocity detection algorithmof radar time⁃frequency signalLI Jia1， CAO Lin1， WANG Dongfeng2， FU Chong3（1. Department of Communication Engineering， Beijing Information Science & Technology University， Beijing 100101， China;2. Beijing TransMicrowave Science and Technology Co.， Ltd.， Beijing 100018， China;3. School of Computer Science and Engineering， Northeastern University， Shenyang 110004， China）Abstract： The signal features of FMCW （frequency modulated continuous wave） are analyzed to improve the accuracy of FMCW system based speed detection of dual⁃beam vehicle flowrate radar. In combination with the Burg and generalized cross⁃correlation theory， atime⁃frequency signal cross⁃correlation algorithm based on Burg and wavelet transform（CC⁃BWT） is proposed. Firstly， the frequency spectrum information of radar echo is obtained with the Burg method based on the maximum entropy power spectrum estimation and thetime⁃frequency signal of the vehicle is extracted after the target vehicle is detected with CFAR. And then， the time⁃frequency signal is subjected to wavelet decomposition to reconstruct the signal by taking the improved threshold function as the denoising basis， then the two signals are correlated for the estimation of the delay and the vehicle speed is obtained finally. It is compared with the phase method and the bispectrum method in combination with the simulation and measured data. The comparison results verify that the speed detection accuracy of the algorithm is above 96% and its robustness is good.Keywords： cross?correlation velocity detection; time⁃frequency signal extraction; wavelet denoising; MESE; signal reconstruction; vehicle velocity detection0; 引; 言双波束雷达[1]测速原理如图1所示，利用车辆经过两个波束的时间差[τ]和两个波束的间距[d]计算车辆的速度[v]，公式可以简化理解为：[v=dτ]; （1）目前，应用到车流量雷达测速的方法有以下几种：利用雷达处理机内部定时器记录车辆驶离雷达照射区域时间，利用距离变化率测速，相位法、双谱法和广义互相关法[2]等。
基于信号BURG谱特征的盲源分离排序算法
∗收稿日期：2020年8月14日，修回日期：2020年9月27日作者简介：李兰瑞，男，硕士研究生，助理工程师，研究方向：水声信号处理。
1引言盲源分离在未知源信号传播信道参数、源信号间统计独立的情况下，依靠阵列数据分离出源信号的波形［1］。
在水声探测领域，海洋环境噪声和舰船辐射噪声间常认为是相互独立的且符合盲源分离条件。
利用盲源分离算法处理水声信号则可实现干扰分离、邻近方位目标信号净化、提高目标信号的信噪比的目的［2~3］。
因而，盲源分离算法在水声信号处理领域应用潜力巨大。
但是，盲源分离存在输出信号次序不确定问题，同一信号在不同时刻不能保持在固定通道输出，不利于声纳兵的听音识别，稳健的排序关联算法也有待进一步研究［4］。
现有的排序法在分析数据较短时性能不够稳健，排序成功率较低，稳健的排序算法对盲源分离输出信号进行关联有利于声纳兵的听音识别，具有重要的实际应用价值。
现有研究表明：1）同一目标在一定时间内的线谱特征相对稳定，不同目标间线谱特征存在非相干特性；2）在短数据情况下，BURG 谱变换相对其他谱变换方式对线谱特征检测能力更强，且受噪声影响较小，性能更加稳健［5］。
同理，在盲源分离算法成功分离信号的情况下，相邻时刻同一目标信号线谱特征相对稳定。
综上，本文利用信号BURG 谱特征对信号进行排序关联，使得同一信号在不同时刻保持在固定通道输出，消除排序模糊性问题。
2基于信号BURG 谱特征的排序算法原理为更好地进行听音处理，我们希望同一信号在不同时刻保持在固定通道输出。
但由于缺少先验知识，信号的原始排列顺序无法得出。
因而排序关基于信号BURG 谱特征的盲源分离排序算法∗李兰瑞刘晓平郭煜姜栋瀚（海军装备部驻上海地区第一军事代表室上海201913）摘要盲源分离算法处理水声信号可实现干扰分离、邻近方位目标信号净化、提高目标信号的信噪比的目的。
但盲源分离输出信号次序不确定问题不利于声纳兵的听音识别，论文利用信号的BURG 谱特征对盲源分离输出信号进行排序关联，算法有效消除了排序模糊性问题。
Boosting和Bagging算法的高分辨率遥感影像分类探讨
第35卷第5期 测绘科学V o L 35 No ．52010年9月S ci e n c e of Su rv ey in g a nd Ma pp in gSep ．Boosting 和Bagging 算法的高分辨率遥感影像分类探讨陈绍杰①，逄云峰②(①龙岩学院资源工程学院，福建龙岩364012；②龙1=I 矿业集团生产处，山东龙1=1265700)【摘要】多分类器集成能够有效地提高遥感分类精度、降低结果中的不确定性，基于样本操作的Boosting 和 Bagging 算法是多分类器系统常用的两种算法。
针对高分辨率卫星遥感分类的需求，以Quickbird 数据为例，分别 以BP 神经网络、RBF 神经网络和决策树为基分类器，对Boosting 和Bagging 算法的应用效果进行了实验和分析评 价。
结果表明Boosting 算法和Bagging 算法能够用于高分辨率遥感影像分类，具有较好的分类性能。
【关键词】多分类器集成；Boost ing ；Bagg ing ；高分辨率遥感【中图分类号】Tfr75l 【文献标识码】A 【文章编号】1009-2307(20io)05-0169-041引言类判决将根据分量分类器判决结果的投票来决定。
一般来说，这些分量分类器是同构的，可能都是神经网络分类器、当前遥感分类的两个主要的发展方向是：①提出和构 SVM 分类器或都是决策树分类器等。
对于Bagging 算法，组 建新的遥感分类方法，如人工神经网络、支持向量机、人 合多个分类器能通过减小误差方差从而减小期望误差值， 工免疫算法等；②多分类器的集成与组合 。
多分类器系 越多的分类器参与，误差方差就越小"J J 。
Bagging 算法通 统的基本思想是通过对分类器集合中分类器的选择与组合， 过随机的有放同的选取训练样本，改变训练样本集合，使 获得比任何单一分类器更高的精度。
由于不同分类器能够 多个分类器进行组合，得到一个性能改进的组合分类器。
正则burg算法
正则burg算法
正则burg算法是一种用于自动构建文法的算法，它是由法国计算机科学家
Jean-Claude R. Berge于1974年提出的。
该算法主要用于从已知的标注文本中提取
规则，并生成一个适用于文本生成的上下文无关文法。
正则burg算法的基本原理
是利用动态规划的方法来找到最优的文法规则集合，使得生成的文本能够最大程度地符合训练文本的特征。
在正则burg算法中，文法规则被表示为一个树状结构，其中每个非终结符都
有一个权重，用于衡量该规则的重要性。
算法的目标是找到最优的规则集合，使得这些规则能够最大程度地覆盖训练文本，并且生成的文本与训练文本的相似度最高。
正则burg算法的主要步骤包括：
1. 初始化：根据训练文本初始化文法规则的权重。
2. 自底向上的动态规划：从叶子节点开始，逐步向上计算每个非终结符的权重，直到根节点。
3. 选择最优规则：根据计算得到的权重，选择最优的规则集合，用于生成文本。
正则burg算法的优点在于能够自动从训练文本中学习文法规则，无需人工干预，且生成的文本质量较高。
然而，该算法也存在一些局限性，例如需要大量的训练文本来获取准确的文法规则，且对文本的结构要求较高。
总的来说，正则burg算法是一种用于自动生成文法规则的有效算法，能够帮
助提高文本生成的效率和质量，是自然语言处理领域的重要研究内容。
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第16卷 第4期 太赫兹科学与电子信息学报Vo1．16，No．4 2018年8月 Journal of Terahertz Science and Electronic Information Technology Aug．，2018文章编号：2095-4980(2018)04-0649-05Burg算法在雷达测速中的应用朱燕，刘逸通(安康学院 电子与信息工程学院，陕西 安康 725000)摘 要：为将Burg算法应用在汽车测速中，在多普勒效应原理的基础上，推导出移动物体发射波频率与接收波频率之间的关系，并分别用直接法和Burg算法估计测速模型中发射波频率82 Hz与接收波频率81 Hz。
经Matlab仿真表明：直接法估计的发射波与接收波主频率分别接近于82 Hz和81 Hz，但频率主峰旁边存在大量噪声频率的假峰；Burg算法估计出的发射波与接收波主频率更准确，同时主峰清晰且较其他噪声频率突出明显。
故Burg算法对间隔不大的发射波与接收波的频率分辨力远远优于直接法，可应用于测速环境中。
关键词：多普勒效应；测速模型；直接法；Burg算法中图分类号：TN953+.1文献标志码：A doi：10.11805/TKYDA201804.0649Application of Burg algorithm in radar speed measurementZHU Yan，LIU Yitong(Department of Electronics and Information Engineering，Ankang University，Ankang Shaanxi 725000，China)Abstract：In order to apply Burg algorithm in the vehicle speed measurement environment, based on the principle of Doppler effect, the relationship between the transmitted wave frequency and received wavefrequency of moving vehicles is derived, then the transmitted wave of 82 Hz and received wave of 81 Hzare estimated with the direct method and the Burg algorithm respectively in the vehicle speedmeasurement model. The Matlab simulation shows that the estimated values of transmitted wave andreceived wave are separately close to 82 Hz and 81 Hz by the direct method, but there are a lot of falsepeaks of noise frequency near the peak frequency. The estimated values of transmitted wave and receivedwave are accurate by the Burg algorithm, and the main peak is clear and prominent than other noisefrequency. Therefore, the Burg algorithm performs better than the direct method in resolving the frequencydifference which is small between the transmitted wave and received wave, and it can be applied to thespeed measurement environment.Keywords：Doppler effect；speed measurement model；the direct method；Burg algorithm近年来，我国道路建设发展愈发迅速，汽车时代提前到来，汽车的购买量与日俱增。
在当今这个汽车时代，存在很多交通隐患。
如何实时准确地反映驾驶者当前驾车速度，对于预防交通事故尤为重要。
目前，交通管理部门常采用雷达测速方法，雷达测速原理来自于多普勒效应的应用，借分析探测波的频率变化来计算汽车的行驶速度，以给予其正常行驶或者超速行驶的判定。
因此，如何准确估计探测波前后的频率显得尤为重要，本文从理论上推导出一种测速方法，使用直接法与Burg算法对理论参数进行估计，进而分析论证不同算法的实用性。
1 雷达测速简介交通中测速的方法有许多，如使用测速发电机、磁脉冲传感器、多普勒雷达等，其中雷达测速法因其精确度高、稳定性强[1]等特点而被广泛应用。
对于机械波、声波、光波和电磁波而言，当波源和观察者(或接收器)之间发生相对运动时，由多普勒效应可知：观察者接收到的波的频率与发出的波的频率不相同[2]。
如果用f表示频率，v表示速度，λ表示波长，理论上波长、频率和速度关系如式(1)所示：收稿日期：2017-05-08；修回日期：2017-08-21基金项目：陕西省教育厅科学研究计划资助项目(16JK1016)650太赫兹科学与电子信息学报 第16卷f =v /λ (1)下面讨论4种情况下物体接收波的频率f J 和发射波频率f 的关系，其中v 为发射波的波速[3]。
1) 当波源静止，物体相对于波源以v y 远离时，f J 和f 的关系如式(2)所示：J y v v f f v−= (2)2) 当物体静止，波源相对于物体以v y 远离时，f J 和f 的关系如式(3)所示：J yvf f v v =+ (3) 3) 当波源静止，物体相对于波源以v y 靠近时，f J 和f 的关系如式(4)所示：J y v v f f v+= (4)4) 当物体静止，波源相对于物体以v y 靠近时，f J 和f 的关系如式(5)所示：J yvf f v v =− (5) 雷达测速中通常是由发射器发射一束频率为f t 速度为c 0的电磁波，当它遇到以速度v 运动的汽车时，汽车处接收到的频率为f q ，此时产生多普勒频移，而频率的偏移只与发射源和运动物体之间的相对速度有关，可以用于速度测量[4]，由式(2)的结论可以推导出式(6)：0q 0c v f f c −= (6)然后，接收器接收由汽车反射回来的反射波，根据式(3)，接收波的频率f z 为：z 0c f f c v=+ (7) 将式(6)、(7)联立，可以得到接收波的频率f z 与发射波的频率f t 的关系，如式(8)所示：000z t t 000c c v c vf f f c v c c v−−==++ (8)2 直接法估计直接法是把随机信号x (n )的N 点观察数据x N (n )看作能量有限信号，直接对其进行傅里叶变换，可得到j (e )N X ω，再对其幅值取平方，然后除以N ，作为对x (n )真实功率谱j (e )P ω的估计。
这里用j PER ˆ(e )P ω表示直接法估计出的功率谱，根据文献[5]可知：2j PER1ˆ(e )()N P X k N=ω (9) 将ω在单位圆上等间隔取值，得式(10)：2PER1ˆ()()N P k X k N= (10) ()N X k 可以使用FFT 快速计算，因此，可以方便的求出PERˆ()P k 。
3 自回归模型一个自回归(Auto Regressive ，AR)模型可以看作是一个输入序列u (n )激励一个线性系统H (z )的输出x (n )[6]，其中输入序列u (n )是白噪声序列，方差为σ2。
该模型现在的输出是现在的输入和过去p 个输出的加权和。
由文献[7]可知，输出x (n )可以表示为式(11)，其中a k 为AR 模型的参数，p 为AR 模型的阶次。
1()()()pk k x n a x n k u n ==−−+∑ (11)功率谱j (e )x P ω与AR 模型参数之间的关系如式(12)所示，由该式可以看出，AR 模型功率谱的准确度与模型参数a k 和σ2密切相关。
第4期 朱 燕等：Burg 算法在雷达测速中的应用65122j 1j (e )1epkx k k P σa −==+∑ωω(12)4 Burg 算法AR 模型有3种求解方法，分别是自相关法、改进协方差法和Burg 算法。
自相关法对于2个小间隔频率的分辨能力不好，需要增大阶数来提高其精确度；改进协方差法的计算方式过于复杂；Burg 算法可有效估计出所需的2个小间隔频率，且模型阶数也不会过大，计算量较小。
相对于直接法估计的精确度取决于采样信号的长度以及采样点的多少，Burg 法则是利用递推的方法，先计算AR 模型阶次p 从1到m 时，前、后向预测误差f()m e n 、 b()m e n ，利用各阶次前、后向预测误差来求取反射系数k m ，然后使用Levinson 关系式求得AR 模型的参数，将该参数代入式(12)中求取功率谱。
由文献[8-9]可知，计算m 阶预测误差的递推公式如式(13)~式(15)所示，式中m =1,2,…,p 。
f f b 11()()(1)m m m m e n e n k e n −−=+− (13) b b b 11()()(1)m m m m e n e n k e n ∗−−=+− (14)f0f ()()()m e n e n x n == (15)求取反射系数的公式如下：1112f b 112f b112()(1)()(1)N n mN N n mn mm m m m m e n e n k e n e n −=−−==−−−−−−=+−∑∑∑(16)估计出k m 后，在阶次m 时的AR 模型的参数仍然由Levinson 算法递推求出[10]。
11()()()m m m a k a k ka m k −−=+− (17)()m m a m k = (18)211m m m p p k −⎢⎥=−⎣⎦ (19)得到模型的参数后，就可按照式(12)估计出功率谱。
经式(13)~(19)推导，Burg 算法不仅免去了大量的测量时间，而且使用递推方式巧妙避开了对已知数据段之外的数据做人为的假设。
5 汽车测速模拟现有一车速为v =40 m/s 的小汽车远离测速器驶去，测速器发射出的波速为c 0=6 120 m/s ，频率为f t =82 Hz ，根据式(8)可知，接收器接收波的频率为f z =81 Hz 。