Contents I Evolvable Fuzzy Hardware for Real-time Embedded Control in Packet Switching 1

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Linux LPC18XX BSP (Board Support Package) Guide fo

Linux LPC18XXBSP (Board Support Package) Guide for the Hitex LPC1850 Eval BoardRelease 1.10.1Table of Contents1.OVERVIEW (3)2.PRODUCT CONTENTS (3)2.1.S HIPPABLE H ARDWARE I TEMS (3)2.2.D OWNLOADABLE H ARDWARE M ATERIALS (3)2.3.D OWNLOADABLE S OFTWARE M ATERIALS (3)2.4.D OWNLOADABLE D OCUMENTATION M ATERIALS (3)3.SOFTWARE FUNCTIONALITY (4)3.1.S UPPORTED F EATURES (4)3.2.N EW AND C HANGED F EATURES (5)3.3.K NOWN P ROBLEMS &L IMITATIONS (5)4.HARDWARE SETUP (5)4.1.H ARDWARE I NTERFACES (5)4.2.J UMPERS (5)4.3.B OARD C ONNECTIONS (5)5.LPC1850 EVAL BOARD LINUX SOFTWARE SET-UP (6)5.1.U-B OOT I NSTALLATION (6)5.2.U-B OOT E NVIRONMENT (7)5.3.E THERNET MAC A DDRESS (8)5.4.N ETWORK C ONFIGURATION (8)5.5.L OADING L INUX I MAGES (8)5.6.U-B OOT B UILD (10)6.FURTHER MATERIALS (10)7.SUPPORT (10)1. OverviewThis document is a Linux LPC18XX BSP (Board Support Package) Guide for the HitexLPC1850 Eval board, Release 1.10.1.The BSP provides a software development environment for evaluation and development of Linux on the Cortex-M3 processor core of the NXP LPC18XX microcontroller using the Hitex LPC1850 Eval board as a hardware platform.2. Product ContentsThis product includes the following components.2.1. Shippable Hardware ItemsThe following hardware items are shipped to customers of this product:1.None - THIS IS A SOFTWARE-ONLY PACKAGE. Please purchase the LPC1850 Eval boardfrom Hitex or its distributors.2.2. Downloadable Hardware MaterialsThe following hardware materials are available for download from Emcraft's web site to customers of this product:1.None - Please obtain hardware materials pertinent to the LPC1850 Eval board directlyfrom Hitex.2.3. Downloadable Software MaterialsThe following software materials are available for download from Emcraft's web site to customers of this product:1.u-boot.bin - prebuilt U-Boot file in the format suitable for installation into embeddedFlash of Cortex-M3 on the LPC1850 Eval board;working.uImage - prebuilt Linux image ready to be loaded to the LPC1850 Evalboard;3.linux-LPC18XX-1.10.1.tar.bz2 - Linux LPC18XX software development environment,including:a)U-Boot firmware;b)Linux kernel;c)busybox and other target components;d)Linux-hosted cross-development environment;e)Framework for developing multiple projects (embedded applications) from a singleinstallation, including sample projects allowing to kick-start software development for Linux LPC18XX.2.4. Downloadable Documentation MaterialsThe following documentation materials are available for download from Emcraft's web site to customers of this product:1.linux-cortexm-um-1.10.1.pdf - Linux Cortex-M User's Manual;2.linux-LPC1850-EVAL-bspg-1.10.1.pdf - Linux LPC18XX BSP (Board Support Package)Guide for the Hitex LPC1850 Eval Board (this document).3. Software Functionality3.1. Supported FeaturesThe following list summarizes the features and capabilities of Linux LPC18XX, Release1.10.1:∙U-Boot firmware:o U-Boot v2010.03;o Target initialization from power-on / reset;o Runs from the internal eNVM and internal SRAM (no external memory required for standalone operation);o Serial console;o Ethernet driver for loading images to the target;o Serial driver for loading images to the target;o Device driver for built-in Flash (eNVM) and self-upgrade capability;o Device driver for storing environment and Linux images in external Flash;o Autoboot feature, allowing boot of OS images from Flash or other storage with no operator intervention;o Persistent environment in Flash for customization of target operation;o Sophisticated command interface for maintenance and development of the target. ∙Linux:o uClinux kernel v2.6.33;o Boot from compressed and uncompressed images;o Ability to run critical kernel code from integrated Flash of LPC18XX;o Serial device driver and Linux console;o Ethernet device driver and networking (ping, NFS, Telnet, FTP, ntpd, etc.);o busybox v1.17;o POSIX pthreads;o Hardened exception handling; an exception triggered by a process affects only the offending process;o Loadable kernel modules;o Secure shell (ssh) daemon;o Web server;o MTD-based Flash partitioning and persistent JFFS2 Flash file system for external Flash.∙Development tools:o ARMv7-optimized GNU toolchain from CodeSourcery (2010q1) is used for development of U-Boot, Linux and user-space applications (toolchain must bedownloaded separately from the CodeSourcery web site);o Cross GDB for debugging user-space applications;o mkimage tool used by the Linux kernel build process to create a Linux image bootable by U-Boot.∙Development environment:o Linux-hosted cross-development environment;o Development of multiple projects (embedded applications) from a single installation;o hello sample project ("Hello, world!" single-process configuration);o networking sample project (basic shell, networking and Flash management tools demonstration);o developer sample project (template project that can be used to jump-start development of custom user-space applications and loadable kernel modules).3.2. New and Changed FeaturesThis section lists new and changed features of this release:1.Improve boot-up time of network-enabled configurations in Linux Cortex-M3/M4.ID: RT 85493.3.3. Known Problems & LimitationsThis section lists known problems and limitations of this release:1.CONFIG_KERNEL_IN_ENVM requires disabling CONFIG_ARM_UNWINDand CONFIG_EARLY_PRINTK.ID: RT 74683.Workaround: When enabling CONFIG_KERNEL_IN_ENVM in the kernel, disableCONFIG_ARM_UNWIND and CONFIG_EARLY_PRINTK.4. Hardware SetupThis section explains how to set up the Hitex LPC1850 Eval board.4.1. Hardware InterfacesFor a description of the hardware interfaces provided by the LPC1850 Eval board, refer to detailed technical documentation and other associated materials available from Hitex.4.2. JumpersThe following jumpers must be configured on the LPC1850 Eval board:Jumper Configuration NotesJP5 2-3 closed Ethernet: MII modeJP14 2-3 closed Ethernet: MII modeJP15 open Ethernet: MII modeJP23 open Disable write protection of NOR flashSV1 only 5-6 and 7-8 closed Connect USART0 to the DB9 port "UART" SV3 all closed Connect Ethernet signalsSV6 all closed Connect Ethernet signalsSV12 all open Disconnect signals optionally shared withEthernetSV13 all open Disconnect signals optionally shared withEthernet4.3. Board ConnectionsTo power the LPC1850 Eval board up, simply connect it to a PC / notebook by plugging a USB-B cable into the X2 USB-B connector on the LPC1850 Eval board. As soon as theconnection to the PC has been made, the various on-boards LEDs should lit up, indicating that the board is up and running.To provide a serial interface to a PC / notebook plug a RS-232 cable to the X1 "UART" connector on the board. On the PC side, the serial link provides a serial console device to the LPC1850 Eval. The software installed on the board is configured for a 115.2 K terminal. On the Linux host, the serial console is available using a /dev/ttyS n device.To provide network connectivity to the board, connect it into your LAN by plugging a standard Ethernet cable into the 10/100 Ethernet connector. The board is pre-configured with an IP address of 192.168.0.2.5. LPC1850 Eval Board Linux Software Set-up5.1. U-Boot InstallationTo install U-boot onto the Hitex LPC1850 Eval, follow the step-wise procedure documented below:1.Configure the boot select jumpers according to the table below for booting from USB0:Jumper ConfigurationBOOT1 1-2 closedBOOT2 2-3 closedBOOT3 1-2 closedBOOT4 2-3 closed2.Connect the UART port of the LPC1850 Eval board to a host.3.Run a terminal program (e.g. HyperTerminal on Windows, or kermit on Linux) and createa serial connection to the LPC1850 Eval board with the following COM-port settings:115200 8N1.4.Connect the LPC1850 Eval board to a Linux host by plugging a USB-B cable into the X2USB-B connector on the LPC1850 Eval board.5.Install the free tool dfu-util on the Linux host either from your Linux distributionpackages or by building it from sources. The sources of dfu-util are available fordownload at /.6.Boot U-Boot on the LPC1850 Eval board by running dfu-util on the Linux host.dfu-util -R -D u-boot.bin7.Start a TFTP server in the local network of the LPC1850 Eval board and make the u-boot.bin image available on this TFTP server.8.Set the U-Boot environment variables serverip and ipaddr to the IP address of theTFTP server and the desired IP address of the LPC1850 Eval board, respectively.LPC1850-EVAL> setenv serverip 192.168.0.10LPC1850-EVAL> setenv ipaddr 192.168.0.18LPC1850-EVAL>9.Download the u-boot.bin image into the on-board RAM.LPC1850-EVAL> tftp lpc18xx/u-boot.binpleted.LPC18XX_MAC: link UP (100/Full)Using LPC18XX_MAC deviceTFTP from server 192.168.0.10; our IP address is 192.168.0.18Filename 'lpc18xx/u-boot.bin'.Load address: 0x28000000Loading: #######doneBytes transferred = 93200 (16c10 hex)LPC1850-EVAL>10.Write the u-boot.bin image into the beginning of the on-board NOR flash.LPC1850-EVAL> era 1c000000 +${filesize}....................... doneErased 23 sectorsLPC1850-EVAL> cp.b ${fileaddr} 1c000000 ${filesize}Copy to Flash... doneLPC1850-EVAL>11.Reconfigure the boot select jumpers according to the table below for booting from NORflash:Jumper ConfigurationBOOT1 1-2 closedBOOT2 1-2 closedBOOT3 2-3 closedBOOT4 2-3 closed12.Reset the LPC1850 Eval board and see the U-Boot start-up banner in the terminalprogram.5.2. U-Boot EnvironmentWhen the LPC1850 Eval board is reset, the Linux bootstrap will proceed to boot the U-Boot firmware from the external NOR Flash printing the following output to the serial console:U-Boot 2010.03-linux-cortexm-1.10.1 (June 11 2013 - 19:43:46)CPU : LPC18xx series (Cortex-M3)Freqs: SYSTICK=180MHz,CCLK=180MHzBoard: Hitex LPC1850 Eval rev 1DRAM: 8 MBFlash: 4 MB*** Warning - bad CRC, using default environmentIn: serialOut: serialErr: serialNet: LPC18XX_MACHit any key to stop autoboot: 0LPC1850-EVAL>U-boot makes use of the so-called environment variables to define various aspects of the system functionality. Parameters defined by the U-boot environment variables include: target IP address, target MAC address, address in RAM where a Linux bootable images will be loaded, and many more. To examine the current settings of the environment variables, run printenv from the U-Boot command interface.The reason for the warning about the "bad CRC" is that U-Boot is configured to store its environment variables in the external Flash. However, this being the first time when you boot Linux LPC18XX on the development board, obviously there is no U-Boot environment programmed to the external Flash. U-Boot goes to the external Flash, fails to find its environment there, prints the warning message and resorts to using the default environment integrated into the U-Boot image at build time.U-Boot provides a command called saveenv that stores the up-to-date run-time environment to the persistent storage, which will be the external Flash for the U-Boot configuration used on the LPC1850 Eval board. You need to call saveenv any time when you want to copy current settings of the environment variables to the persistent storage in Flash.This is how you can write the current U-Boot environment to the external Flash:LPC1850-EVAL> saveenvSaving Environment to Flash......LPC1850-EVAL>Reset the LPC1850 Eval board and check that there is no warning about the bad CRC in the boot-up messages. This is expected since now U-Boot successfully finds its environment in the external Flash:LPC1850-EVAL> resetresetting ...U-Boot 2010.03-linux-cortexm-1.10.1 (June 11 2013 - 19:43:45)...Hit any key to stop autoboot: 0LPC1850-EVAL>5.3. Ethernet MAC AddressIn Linux LPC18XX, the MAC address of the Ethernet interface is defined by the ethaddr U-Boot environment variable. The value of the MAC address can be examined from the U-Boot command line monitor as follows:LPC1850-EVAL> printenv ethaddrethaddr=C0:B1:3C:88:88:88LPC1850-EVAL>The default U-Boot environment for the LPC1850 Eval board sets ethaddr to a fixed MAC address. This address should work for you in a general case, however if you have more than two LPC1850 Eval boards in your LAN, use of the same address on multiple boards may result in packet collisions in your LAN and overall may render your LAN mal-functioning.If you have more than one LPC1850 Eval boards in your LAN, you have to assign a unique MAC address to each board.The MAC address can be changed by modifying the ethaddr variable as follows:LPC1850-EVAL> setenv ethaddr C0:B1:3C:88:88:89Don't forget to store your update in the persistent storage using saveenv so it is remembered across resets and power cycles.5.4. Network ConfigurationYou will have to update the network configuration of your board to match settings of your local environment.Typically, all you have to allow loading images over network from a TFTP server is update the U-Boot environment variables ipaddr (the board IP address) and serverip (the IP address of the TFTP server). Here is how it is done.Update ipaddr and serverip:LPC1850-EVAL> setenv ipaddr 192.168.0.2LPC1850-EVAL> setenv serverip 192.168.0.1and then save the updated environment to the external Flash so that your changes are persistent across resets/power cycles.5.5. Loading Linux ImagesAt this point, you are able to load Linux bootable images to the board over TFTP and either boot them directly or install them to the external Flash to allow booting Linux from Flash on power-up/reset.On the host, activate the Linux LPC18XX development environment and build the networking project:-bash-3.2$ . ACTIVATE.sh-bash-3.2$ cd projects/networking/-bash-3.2$ make...-bash-3.2$Copy the Linux bootable image to the TFTP download directory:-bash-3.2$ cp networking.uImage /tftpboot/vlad/-bash-3.2$To load the image directly, use the netboot U-Boot macro:LPC1850-EVAL> setenv image vlad/networking.uImageLPC1850-EVAL> run netboot...TFTP from server 172.17.0.1; our IP address is 172.17.5.100Filename 'vlad/networking.uImage'....Loading: ###############################################################################################################################################doneBytes transferred = 2084704 (1fcf60 hex)...Image Name: Linux-2.6.33-arm1Image Type: ARM Linux Kernel Image (uncompressed)...Verifying Checksum ... OKLoading Kernel Image ... OKOKStarting kernel ...Linuxversion2.6.33-arm1(******************.com)(gccversion4.4.1(SourceryG++Lite 2010q1-189) ) #1 Tue June 11 15:43:44 MSK 2013...To load the image into the Flash, use the U-Boot update macro:LPC1850-EVAL> setenv image vlad/networking.uImageLPC1850-EVAL> run update...TFTP from server 172.17.0.1; our IP address is 172.17.5.100Filename 'vlad/networking.uImage'....Loading: ###############################################################################################################################################doneBytes transferred = 2084704 (1fcf60 hex) ................................ doneUn-Protected 32 sectors................................ doneErased 32 sectorsCopy to Flash... doneLPC1850-EVAL>Reset the board and verify that the newly programmed image boots on the target in the autoboot mode:LPC1850-EVAL> resetresetting ...U-Boot 2010.03-linux-cortexm-1.10.1 (June 11 2013 - 17:19:37)...Starting kernel ......init started: BusyBox v1.17.0 (June 11 2013 - 17:19:37)~ #5.6. U-Boot BuildThe BSP distribution comes with U-Boot pre-built for the LPC1850 Eval board. If however you need to re-build U-Boot for your board, please follow the instructions below:1.Install the Linux LPC18XX distribution to the development host, as described in the LinuxCortex-M User's Manual.2.From the top of the Linux LPC18XX installation, activate the Linux LPC18XX cross-compile environment by running . ACTIVATE.sh.3.Go to the U-Boot source directory (cd u-boot/).4.Run the following commands:[psl@pvr u-boot]$ make lpc1850-eval_configConfiguring for lpc1850-eval board...[psl@pvr u-boot]$ make -s6. Further MaterialsRefer to Linux Cortex-M User's Manua l for detailed information on the software architecture of the Linux LPC18XX distribution.Visit Emcraft Systems' web site at to obtain additional materials related to Linux LPC18XX.7. SupportWe appreciate your review of our product and welcome any and all feedback. Comments can be sent directly by email to:*****************************The following level of support is included with your purchase of this product:∙Email support for installation, configuration and basic use scenarios of the product during3 months since the product purchase;∙Free upgrade to new releases of the downloadable materials included in the product during 3 months since the product purchase.If you require support beyond of what is described above, we will be happy to provide it using resources of our contract development team. Please contact us for details.。

A reconfigurable chip for evolvable hardware

A Reconﬁgurable Chip for Evolvable HardwareYann Thoma and Eduardo SanchezSwiss Federal Institute of Technology at Lausanne(EPFL),Lausanne,Switzerland Corresponding author.E-mail:yann.thoma@epfl.chAbstract.In the recent years,Xilinx devices,like the XC6200,were thepreferred solutions for evolving digital systems.In this paper,we presenta new System-On-Chip,the POEtic chip,an alternative for evolvablehardware.This chip has been speciﬁcally designed to ease the imple-mentation of bio-inspired systems.It is composed of a microprocessor,and a programmable part,containing basic elements,like every standardField Programmable Gate Array,on top of which sits a special layer im-plementing a dynamic routing algorithm.Online on-chip evolution canthen be processed,as every conﬁguration bit of the programmable arraycan be accessed by the microprocessor.This new platform can thereforereplace the Xilinx XC6200,with the advantage of having a processorinside.1IntroductionEngineers and scientists have much to learn from nature,in term of design capa-bilities.Living beings are capable of evolution,learning,growth,and self-repair, among others.Each of theseﬁelds can serve as inspiration to build systems that are more robust and adaptable.Three life axis deﬁne what makes nature a good candidate from which we can draw inspiration:Phylogenesis(P),Ontogenesis (O),and Epigenesis(E).Phylogenesis is the way species are evolving,by transmitting genes from parents to children,after a selection process.Based on the principles of the neo-darwinian theory,scientists have designed evolutionary algorithms,and more particularly genetic algorithms[1],that are used to solve complex problems for which a deterministic algorithm can notﬁnd a solution in an acceptable period of time.Ontogenesis corresponds to the growth of an organism.In living beings,af-ter fertilization,a single cell,the zygote,contains the genome that describes the entire organism and starts dividing,until the organism is totally created. Ontogenesis takes also care of self-healing,a very important feature of living beings,that prevents them from dying after a light injury.In electronics,self-repair based on ontogenetic principles has been applied to building more robust systems[2–5].Finally,epigenesis deals with learning capabilities.A brain,or more generally a neural network,is the way life solved the learning problem.Taking inspiration of real neurons,scientists have designed a huge variety of neural networks,to solve diﬀerent tasks,like pattern recognition[6]and robot learning[7].These three life axis have often been considered separately for designing sys-tems,or as a conjunction of learning and evolution.Until now,no real POE system has been constructed.The POEtic project is therefore the logical conti-nuity of bio-inspired systems.A new chip has been specially designed to ease the development of such systems.It contains a microprocessor,and a reconﬁgurable array oﬀering capabilities of dynamically creating paths at runtime.This paper focuses on the way POEtic,a promising alternative to the XC6200, can be used as a platform for evolvable hardware[8,9].Next section presents brieﬂy the principles of evolvable hardware and whyﬁeld programmable gate ar-rays are good candidates for such systems.Section3describes the POEtic chip, with an emphasis on its usefulness for evolvable hardware.Section4presents the way POEtic will be used for this purpose,andﬁnally section5concludes. 2Evolvable HardwareEvolvable hardware(EHW),on the phylogenetic axis,deals with the design of analog or digital circuits using genetic algorithms.This technic replaces an engineer in the design task,and can act in many diﬀerent areas.For instance, basic systems like adders or multipliers can be built,while robot control can also be generated.EHW processes can be evolved in simulation in many cases,but software implementations are very slow,and cannot alwaysﬁt real conditions. Therefore,hardware platforms are needed,to generate operating circuits,in case of analog design,and to speed up the entire process,in case of digital design.2.1FPGAs and the Xilinx XC6200familyField Programmable Gate Arrays(FPGAs)[10]are digital circuits that can be reconﬁgured,and thus make them excellent candidates for implementing EHW. Every commercial FPGA is based on a2-dimensional array of cells,in which it is possible to deﬁne the cells’functionalities and the routing.The most widely used for EHW,the Xilinx Virtex XC6200family,has been utilized in many experiments[11–15],due to its routing implementation based on multiplexers rather than on anti-fuse or memory bits(short circuits can be generated in almost every other types of FPGAs).The architecture of the XC6200is very simple,with cells based on some multiplexers and aﬂip-ﬂop.Moreover,the conﬁguration bits arrangement is public,giving a programmer total control over the conﬁguration.Unfortunately,these devices are not available any more,and no equivalent FPGA is available as of today.The inherent parallelism of FPGAs allows to rapidly test individuals to eval-uate theirﬁtness,but a problem remains:the conﬁguration is very slow.One of the last family of Xilinx devices,the Virtex II Pro,embeds a microprocessor that can access a reconﬁgurable array,but without the capability of reconﬁgur-ing it.The POEtic chip,as explained in the next section,will be a new hardware platform that solves this last drawback.3The POEtic ChipThe POEtic chip has been speciﬁcally designed to ease the development of bio-inspired applications.It is composed of two main parts:a microprocessor,in the environmental subsystem,and a2-dimensional reconﬁgurable array,called the organic subsystem(ﬁgure1).This array is made of small elements,called molecules,that are mainly a4-input look-up table,and aﬂip-ﬂop.In the or-ganic subsystem,a second layer implements a dynamic routing algorithm that will allow multi-chip designs,letting the user work with a bigger reconﬁgurable virtual array.The next section presents some features of the on-chip microprocessor.The subsequent section describes the reconﬁgurable array,with a special emphasis on how the diﬀerent parts of the basic elements can be used to build an EHW system similar to the XC6200.Fig.1.The POEtic chip,showing the microprocessor and the reconﬁgurable array. Many elements connected to the AMBA bus,like a second timer,serial and paral-lel ports,are omitted in order to simplify the schematics.On the right,the organic subsystem shows molecules on the bottom,and routing units on the top.3.1The MicroprocessorThe microprocessor is a32-bit RISC processor,specially designed for the POEtic chip.It exposes57instructions,two of which give access to a hardware pseudo-random number generator,that can be very useful for evolutionary processes. This small number of instructions limits the size of the processor,leaving more room for the reconﬁgurable array.An AMBA bus[16]allows communication with all internal elements,as shown inﬁgure1,as well as with the external world.It also permits to connect many POEtic chips together,in order to have a bigger reconﬁgurable virtual array.The microprocessor can conﬁgure the array,and also retrieve its state.The access is made in a parallel manner,the array being mapped on the microproces-sor address space.As a result,so that it is very fast to conﬁgure,or to partially reconﬁgure the array,since the conﬁguration of one molecule requires only three write instructions.For instance,when dealing with evolutionary processes,the retrieved state can be used to calculate theﬁtness of an individual and evolution can be performed by the microprocessor,avoiding fastidious data transmission with a computer.A C compiler,as well as an assembler,has been developed,letting a user eas-ily write programs for this microprocessor.Furthermore,an API will be supplied, in order to rapidly build a genetic algorithm by choosing the type of crossing-over,the selection process,and so on.Special functions will also simplify the reconﬁgurable array conﬁguration.3.2The Reconﬁgurable ArrayThe reconﬁgurable array is composed of two planes.Theﬁrst one is a grid of ba-sic elements,called molecules,based on a4-input look-up table,and aﬂip-ﬂop. The second one is a grid of routing units,that can dynamically create paths at runtime between diﬀerent points of the circuit.They implement a distributed dynamic routing algorithm,based on addresses.It can be used to create connec-tions between cells in a cellular system(e.g.a neural network),to connect chips together,or simply to create long-distance connections at runtime(interested readers can see a description of this algorithm in[17]).Fig.2.A“molecule”can act in eight diﬀerent operational modes,the mode being deﬁned by three conﬁguration bits.The left drawing shows a molecule in4-LUT mode, while the right depicts a molecule in3-LUT mode.The so-called molecules(seeﬁgure2)execute a function,according to an operational mode,deﬁned for each molecule by three conﬁguration bits(for more details,see[17]).The eight operational modes are:–4-LUT:The molecule is a4-input LUT.–3-LUT:The molecule is divided into two3-input LUTs.–Shift memory:The molecule is considered like a16-bit shift register.–Comm:The molecule is divided into a3-input LUT and a8-bit shift register.–Conﬁgure:The molecule has the possibility of partially reconﬁgure its neighborhood.–Input:The molecule is an input from the routing plane.–Output:The molecule is an output to the routing plane.–Trigger:This mode is used to synchronize the dynamic routing algorithm.3.3Molecular communicationIn addition to its functional part,a molecule contains a switch box for inter-molecular communication.Like in the Xilinx XC6200family,inter-molecular communication is implemented with multiplexers.This feature,although being more expensive in term of space and delays,avoids short circuits that could happen when partially reconﬁguring a molecule,or during an unconstrained evolution process.Every molecule is directly connected to its four neighbors,sending them its output,while long-distance connections are implemented by the way of switch boxes(ﬁgure3).There are two input lines from each cardinal direction,and two corresponding outputs.Each output can be selected from the six input lines from the other cardinal directions,or from the output of the molecule(or the inverse).As there are eight possible conﬁgurations for an output multiplexer,three conﬁguration bits are necessary for each output.The total lets the switch box being deﬁned by(2outputs by4directions by3bits=)24bits.These24bits could be part of the evolutionary process,orﬁxed,depending on the kind of system we want to evolve.For instance,in order to use the POEtic chip like a Xilinx XC6200,every switch box should be conﬁgured as inﬁgure3.Byﬁxing some conﬁguration bits to’0’,we can choose to only deal with one line to each direction,as shown in the right of theﬁgure.In every of its operational modes,a molecule needs up to four inputs.Multi-plexers are taking care of the selection of these inputs,like the twoﬁrst inputs shown inﬁgure4.An input can basically come from any long-distance line,but each multiplexer has special features.Some can retrieve theﬂip-ﬂop value,some the direct neighbors output,and so on.Byﬁxing some conﬁguration bits,we can for instance force the selection of a signal coming from N0in,S0 in.Therefore,only two bits are necessary to completely deﬁne every input. This way,every input has the same potential as the others,which would not be the case if every conﬁguration bit could be modiﬁed.fu n c _/f u n c _E 0_i n E 1_i n S 0_i n S 1_i n W 0_i n W 1_i n N0_o u t u n c _o u t /f u n c _o u t E 0_i n E 1_i n S 0_i n S 1_i n W 0_i n W 1_i n N1_o u t N0_i n N 1_i n E 0_i n E 1_i n f u n c _/f u n c W 0_i W 1_i S0_o u t N0_i n N 1_i n E 0_i n E 1_i n f u n c _/f u n c _o u t W 0_i n 1_i n S1_o u t Switch Boxfu n c _o u t E 0_i n S 0_i n W 0_i n _o u t N0_i n E 0_i n f u n c _o u t W 0_i n S0_o u t Fig.3.On the left,the switch box contained in every molecule,as shown in ﬁgure 2,and on the right a subset of the possible conﬁgurations to reduce the genome size.Black boxes represent conﬁguration bits that can be used for evolution,while white boxes are “don’t care bits”for such applications.3.4Conﬁguration BitsOne of the advantages of the POEtic chip is the possibility to deﬁne any of the 76conﬁguration bits.These bits are split into ﬁve blocks,as shown in table 1.The ﬁrst bit of each block indicates whether the block has to be reconﬁgured or not,in case of a partial reconﬁguration coming from a neighbor molecule.As mentioned before,the microprocessor can access (read/write)the conﬁguration bits with a 32-bit bus.For EHW,this feature is very important in terms of execution time.Since only two clock cycles are needed for a write and three words of 32bits deﬁne a molecule,the conﬁguration of the entire array or of only a part of it is very fast.In comparison with standard FPGAs,like a Xilinx with JBits [18,19],in which the entire conﬁguration bitstream must be sent each time in serial,the reconﬁguration,like the ﬁrst conﬁguration,is made in parallel,allowing a huge gain in term of time.Moreover,compared to a total reconﬁguration,if we only evolve the switch box or the LUT,loading time can be divided by three,as only part of the molecule conﬁguration needs to be reloaded.4Evolvable Hardware on POEticIn last section,we showed diﬀerent parts of the reconﬁgurable array that can be used in an evolvable process.The ﬁnal chip being not yet available,we will not present experimental results,but concepts that will be used later to demonstrateconfig_direct_in config_special_inputconfig_mode=Fig.4.The two ﬁrst inputs of the molecule.The signals configselTable1.Theﬁve blocks of conﬁguration bits(theﬁrst three bits cannot be partially conﬁgured by a neighbor molecule).Numberglobal partial conﬁguration enable21lut(15downto0)(cf.ﬁgure2)lut inputs conﬁguration enable1413bits for each of the8multiplexers(cf.ﬁgure3)mode partial conﬁguration enable31sequential or combinational output1dﬀenable used or not1local reset origin1asynchronous/synchronous reset1value of theﬂip-ﬂop–The evolution is made Online,because every individual will be tested using the reconﬁgurable array.–The evolution is On-chip,as the microprocessor is incorporated into the reconﬁgurable chip.–The scope of evolution can be Static,or Dynamic,depending on the type of application.POEtic,with its dynamic routing capability,could show function level evo-lution that involves sine generators,adders,multipliers,artiﬁcial neurons,or others.However,in this paper we only present gate level evolution,that involves OR/AND gates,or in our example,look-up tables.Basically,an unconstrained evolution could be executed with the entire con-ﬁguration bitstream,since it is impossible to create a short-circuit.However,76 bits for each molecule signify a huge genome,if,for instance,we deal with a10 by10array.Therefore,in many cases,only part of the bitstream will be evolved, in order to reduce the search space.The experiments made by Thompson using the Xilinx XC6200are based on the same principle of avoiding to evolve the entire bitstream.They only deal with18bits per element,in order to evolve oscillators,for instance.The same types of applications could be resolved with22bits using the POEtic chip.4.2Genome RepresentationIn the approach chosen in this paper,we evolve a system at the gate level,by evolving the routing or the function of molecules.Therefore,it is natural to directly evolve the conﬁguration stream of the chip.Since there are 76conﬁgura-tion bits,and the bus has a width of 32bits,only three words deﬁne a molecule.In order to evolve routing and functionality,we do not want to evolve the entire bitstream,but only part of it.By using very simple logical operations we can modify the entire genome,without modifying ﬁxed parts,as shown in ﬁgure 6.In our example,the routing uses half of its capabilities,with the subset shown in ﬁgure 3.The molecule inputs are the same as shown in ﬁgure 4,and the operational mode is ﬁxed to the 3-LUT mode.Therefore,the functionality can be any 3inputs function.This case corresponds to an evolution of the basic cells of ﬁgure 5.N0_in E0_in S0_in func_outN0_func_outFig.5.The basic element,subset of the molecule,that can be evolved,deﬁned by only 22bits.Black boxes are conﬁguration bits that are evolved.The full genome is composed,for each molecule,of 96bits (3x32),76deﬁning conﬁguration bits.However,in our example,only 22bits really represent infor-mation used to deﬁne the phenotype,the 74other bits being ﬁpared to the 18bits used by Thompson with a XC6200,we deal with 4more bits,because we totally evolve the look-up table content,rather than just some multiplexers.This way the genome is bigger,but each element has more ﬂexibility.In the evolution process,crossing-over and mutation will be applied to the entire conﬁguration stream,and the very simple logical operations will erase parts of it with the ﬁxed bits.This way,there is no need to use complex trans-formation,from a smaller virtual bitstream to a real one,saving execution time.Moreover,the ﬁxed parts can be viewed like junk DNA in living beings,in which a large part of the genome is simply unused.Fig.6.Thisﬁgure depicts the way a phenotype can be generated,from a variable genome and aﬁxed part.A line represents the3x32=96bits where20are unused bits and76are conﬁguration bits of a molecule.These76bits are divided into theﬁve blocks described in table1.Theﬁrst line is the genome evolved using crossing-over and mutation.The genome mask is used in a logical“and”operation with the genome. It contains’1’at every place the genome is deﬁned by the evolutionary algorithm. Only22bits are relevant to deﬁne the phenotype:8bits for the switch box,6bits for the molecular inputs,and8bits for the3-input LUT.Theﬁxed part,combined with its mask(the inverse of the genome mask)corresponds to every conﬁguration bits not deﬁned by the evolution.By simply using an“or”operation on the two results of“and”operations,we obtain the phenotype that is the real conﬁguration of the molecule.5ConclusionIn this paper we presented how the POEtic chip can be useful as an EHW platform.The conjunction of a custom microprocessor and a reconﬁgurable array is perfect to implement an on-chip evolution process.Moreover,compared to a Xilinx Virtex II Pro where there is also a microprocessor,the advantage of POEtic is the fact it is aware of the entire memory map of the conﬁguration bits,and that the microprocessor can conﬁgure the chip.Finally,compared to a Xilinx XC6200,POEtic has the advantage of having a microprocessor inside, allowing fast conﬁguration of the reconﬁgurable array.Table2summarizes the features of the XC6200,the Virtex II Pro,and POEtic.At present,a test chip is being fabricated.After functional tests on this small chip(it only contains the microprocessor and12molecules),theﬁnal POEtic chip,containing about200molecules,will be designed and sent to fabric.As soon as it is available,the concepts described in this paper will be tested with the real hardware,to show the promising usefulness of the POEtic chip as a powerful replacement of the Xilinx XC6200for EHW.parison of features useful for EHW between a XC6200,a Virtex II Pro and the POEtic chip.Feature XilinxXC6200Yes Yes Processor inside YesNo Yes Bitstream detail available NoNo Yes5.1AcknowledgementsThis project is funded by the Future and Emerging Technologies programme (IST-FET)of the European Community,under grant IST-2000-28027(POETIC). The information provided is the sole responsibility of the authors and does not reﬂect the Community’s opinion.The Community is not responsible for any use that might be made of data appearing in this publication.The Swiss participants to this project are supported under grant00.0529-1by the Swiss government. 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英文单片机模糊逻辑控制器对永磁直流电动机的设计和应用

Engineering Applications of Artiﬁcial Intelligence 18 (2005) 881–890Single-chip fuzzy logic controller design and an application on a permanent magnet dc motorSinan PravadaliogluI.M.Y.O., Control Sys. Department, Dokuz Eylu ¨l University, Menderes cad, Istasyon sok 5, Buca, 35170 Izmir, Turkey Received 27 March 2004; accepted 11 March 2005 Available online 23 May2005AbstractThis paper describes a low-cost single-chip PI-type fuzzy logic controller design and an application on a permanent magnet dc motor drive. The presented controller application calculates the duty cycle of the PWM chopper drive and can be used to dc–dcconverters as well. The self-tuning capability makes the controller robust and all the tasks are carried out by a single chip reducing the cost of the system and so program code optimization is achieved. A simple, but effective algorithm is developed to calculate numerical values instead of linguistic rules. In this way, external memory usage is eliminated. The contribution of this paper is to present the feasibilityof a high-performance non-linear fuzzy logic controller which can be implemented byusing a general purpose microcontroller without modiﬁed fuzzy methods. The developed fuzzy logic controller was simulated in MATLAB/SIMULINK. The theoretical and experimental results indicate that the implemented fuzzy logic controller has a high performance for real-time control over a wide range of operating conditions.2005 Elsevier Ltd. All rights reserved.Keywords: Dc motor drive; Fuzzy logic controller; Microcontroller; Application; Simulation1.IntroductionIn switch-mode power supplies, the transformation of dc voltage from one level to another level is dc–dc conversion and accomplished by using dc–dc converter circuits, which offers higher efficiency than linear regulators. They have great importance in many practical electronic systems, including home appliances, computers and communication equipment. They are also widely used in industry, especially in switch-mode dc power supplies and in dc motor drive applications. The dc- dc converter accepts an unregulated dc input voltage and produces a controlled dc output at desired voltage level. They can step-up, step-down and invert the input dc voltage and transfer energy from input to output in discrete packets. The one disadvantage of dc–dc converters is noise. At every period to charge in discrete packets, it creates noise or ripple. The noise can be minimized using specific control techniques and with convenient component selection. There are well-knowncontrol techniques including pulse-width modulation (PWM) where the switch frequencyis constant and the duty cycle varies with the load.PWM technique affords high efficiency over a wide load range. In addition, because the switching frequency is fixed, the noise spectrum is relatively narrow, allowing simple low-pass filter techniques to reduce the peak-to- peak voltage ripple. For this same reason, PWM is popularwith telecom power supply applications where noise interference is of concern .The most important requirement of a control system for the dc–dc converter is to maintain the output voltage constant irrespective of variations in the dc input voltage and the load current. However, load changes affect the output transiently and cause significant deviations from the steady-state level of dc output voltage, which must be controlled to equal adesired level by the control systems. The inherent switching of a dc–dc converter results in the circuit components being connected periodically changing configurations, each configuration being described by a set of separate equations. Transient analysis and control system design for a converter is therefore difficult since a number of equations must be solved in sequence. Although the state-space averaging is the most commonly used model to obtain linear transfer functions to solve this problem, it neglects significant parts of non-linear behavior of dc–dc converters. Development of non-linear controllers for dc–dc converters have gained considerable attention in recent years.A fuzzy logic model based controller is chosen as the non-linear controller for this study. Fuzzy logic control (FLC) has been an important research topic. Despite the lack of concrete theoretical basis many successful applications on FLC were reported and various applications for dc–dc converters and electrical drives have been published and can be found in the literature (So et al., 1996, 1995;Mattavelli et al., 1997; Brandsetter and Sedlak, 1996; Hyo et al., 2001; Gupta et al., 1997;Zakharov, 1996; V as, 1998, 1999). FLC has a wide-spread application on the non-linear and complex systems as well as linear systems due to its capability to control the systems that might not have a transfer function between input and output variables. Experi-ences show that fuzzy control can yield superior results to those obtained by conventional control algorithms.In the meantime, new fuzzy microcontroller chips are available on the market and are able to execute fuzzy rules very fast with their mask programmed algorithms that have some drawbacks such as restriction in implementing any desired algorithm. Digital signal processing (DSP) integrated circuits (IC) are capable of computing and processing the system variables very quickly with high precision. But most of the DSP circuits are expensive and do not contain peripherals such as analog to digital (A/D) and digital to analog (D/A) circuits for conversion and PWM generator on chip,and need to be added externally. A fuzzy controller application among the others on dc–dc converters used a TMS320-DSP and fuzzy controller with an evaluation module plus some external chips. They were an A/D converter for feedback signal evaluation, a D/A converter for converting the calculated quantity into a control output and a PWM chip to generate the appropriate duty cycle for the semiconductor switching elements (So et al., 1995; Brandsetter and Sedlak, 1996). An implementation of an FLC with 8-bit conventional microcontroller is presented in Gupta et al. (1997) for dc–dc converters and a modified centroid method for defuzzication process is used to reduce the processing time of 8-bit microcontroller. However, this moded defuzzification technique increases the settling time of the system. A detailed simulation and experimental study on the closed-loop control of dc motor drive with FLC is carried out in Zakharov (1996) and a PC computer with an evaluation board is employed for FLC. The transient response of proportional integral (PI)-type current and speed controllers are compared to that of the FLC.The aim of the study presented in this paper is to design and to implement a high-performance fuzzy tuned PI controller for controlling the rotor speed of permanent magnet dc motor (PMDCM). We also provide a wayof designing such a controller in a cost effective way by using a general purpose single-chip microcontroller. This design is implemented with-outmaking the assumptions for the modification of defuzzification process which was presented in Guptaet al. (1997). This leads to an improved performance of the transient and steadystate of the closed-loop System.The experimental results are also compared to the simulation result obtained from MATLAB/SIMU-LINK.2.Permanent magnet dc motor and class C chopperA PMDCM fed via class C chopper can be described by the state-space form in the continuous time as follows:where R a is armature resistance (Ohm), L a is armature inductance (Henry), K aψis back electromotive force and torque constant (V/rad/s or Nm/A), J is total moment of inertia (kgm2) and B v is viscous friction constant (Nm/rad/s). V a（t）represents the voltage applied to armature by a class C type of chopper given in Fig. 1.The average value of armature voltage is a function of t on, period of chopping and the level of dc input voltage as shown in Fig. 2.In analog control systems, the repetitive sawtooth waveform is compared with the control voltage to generate the PWM gate signals to the MOSFETs employed in the chopper. The duty cycle is equal to the ratio between control voltage (E c) and the peak of sawtooth. The control voltage signal is generally obtained amplifying the difference between the actual output voltage and its desired value. Simple controls can be carried out using analog IC, such as operational amplifier circuits but sophisticated control tasks usually involves the using of digital ICs, microcontrollers or DSPs to support high-performance, repetitive, numeri-cally intensive tasks. Building a closed-loop control system, the actual output voltage can be sensed by a tacho generator which produces an output voltage proportional to armature rotation. Development and application of FLC in electrical drives have drawn greater attention in recent years (Vas, 1998, 1999).Fig. 1. Dc motor and Class C chopper.Fig. 2. V oltage waveforms of Class C type of chopper.3. Fuzzy controllerConventional controllers are derived from control theory techniques based on mathematical models of the process. They are characterized with design procedures and usually have simple structures. They yield satisfying results and are widely used in industry. However, in a number of cases, such as those, when parameter variations take place, or when disturbances are present, or when there is no simple mathematical model, fuzzy logic based control systems have shown superior performance to those obtained by conventional control algorithms.Fuzzy control is a method based on fuzzylogic. L.A.Zadeh's pioneering work in 1965, and his seminal paper in 1973 on fuzzy algorithms introduced the idea of formulating the control algorithm by logical rules. On the basis of the ideas proposed in this paper, Mamdani developed the first fuzzy control model in 1981. This then led to the industrial applications of fuzzy control.Fuzzy control can be described simplyas "control with sentences rather than equations" (Jan Jantsen1998). It provides an algorithm to convert a linguistic control strategy—based on expertknowledge—into an automatic control strategy. The essential part of a fuzzy controller is a set of linguistic rules which is called rule base.1. If error is Negative and change in error is Negative then output is Negative Big.2. If error is Negative and change in error is Zero then output is Negative Medium.The fuzzy rules are in the familiar if–then format and the "if side" is called the antecedent and the "then side"is called the consequent. The antecedents and the consequents of these if–then rules are associated with fuzzy concepts (linguistic terms), and they are often called fuzzy conditional statements. A fuzzy control rule is a fuzzy conditional statement in which the antecedent is a condition and the consequent is a control action.The fuzzy controller should execute the rules and compute a control signal depending on the measured inputs or conditions. There is no design procedure in fuzzy control such as root-locus design, pole placement design, frequencyresponse design, or stability design because the rules are often non-linear and close to the real world. Non-linearityis handled byrules, member-ship functions and the inference process.Described fuzzy logic model based on non-linear controller is developed and tested on real-time feedback control for the rotor speed of PMDCM. The speed feedback and fuzzy control algorithm block diagram are given in Fig. 3. The tacho-generator measures the actual rotor speed supplying input to the on-chip A/D converter. At the beginning of every kth switching cycle, the reference rotor speed w ref is compared with the actual rotor speed w act. The error (e(k)) and change of error (ce(k)) values of rotor speed are the inputs of the fuzzy control algorithm, which are defined asThe microcontroller calculates these inputs right after conversion from on-chip A/D converter. The fuzzy control algorithm is divided into three modules:(1) fuzzification, (2) decision-making or inference, (3)defuzzification.Fig. 3. Block diagram of drive circuit.In the fuzzification module, the error and change of error signals are evaluated by fuzzy singletons and their numerical values are converted into seven linguistic variables or subsets: PB (Positive Big), PM (Positive Medium), PS (Positive Small), ZE (Zero), NB (Negative Big), NM (Negative Medium) and NS (Negative Small). The fuzzification module calculates the degree of membership of every linguistic variable for given real values of error and change of error. The triangular shapes as given in Fig. 4a are used for smooth operation on membership functions.The calculated values of fuzzy variables are used in he decision-making process. Decision-making is infer-ing from control rules and linguistic variable defidefini-tions. There are seven sets for the error and seven sets for the change of error, and thus total 49 rules taking place for the whole control surface which are given in compact form in Table 1. This rule table can reflect experiences of the human experts.For each error and change of error, there are two overlapping memberships; therefore, all linguistic vari-ables except two has zero membership. Each two overlapping memberships of error and change of error will create four combinations as inference results.The maximum of these four inference results will have two parts, namely, the weighting factor w i and the degree of change of duty cycle y i. The min fuzzy implication rule of Mamdani is used to obtain the weighting factorwhich gives the membership degree of every relation (Lee, 1990). The inferred output ui of each rule isFig. 4. (a) Membership functions for error and change of error.(b) Enlargement for error membership function at a point x.Here, y i represents the centroid of membership function defining the ith rule output variable and can be stored in a look-up table for quick acquisition.Membership functions for change of output of FLC,which is the dutycycle for this application, is shown in Fig. 5According to the membership functions of the input,the output variables and the rule table, respectively, in Figs. 4a, 5 and Table 1, the control surface representa-tion is shown in Fig. 6.In defuzzification module, a crisp value for output is performed. Although the defuzzification process has many methods, the weighted average method is employed for this application because the operation of this method is computationally quite simple and takes less time in the computation process of microcontroller (Bart Kosko,1991; Ross, 1995). The output of defuzzification module can be represented byThe inferred output results and the weighing factors from each of the four rules are used in the equation given above to obtain a crisp value for the change of duty cycle. It is obvious that this calculation is the most time-consuming part of FLC and has computational complexity. The microcontroller output is the PWM duty cycle and defined asThis crisp value is the fuzzy controller actual output at the kth sampling period and is obtained from the previous value of control d(k-1) that is updated by Δd(k).In case of wide range changes of the drive operation, the response of FLC will be non-linear. This means that they should compensate either big positive errors like start-up or small negative errors during step changes.The main difference between the classical PI controller and fuzzy PI controller can be defined with their gains where fuzzy type has variable gain.4.Simulation resultsComputer simulation has an important role in the evaluation of power electronics and closed-loop con-troller designs (Pires and Silva, 2002). Fig. 7 shows the block diagram used in the MATLAB/SIMULINK program to simulate the closed-loop system which was performed on a PMDCM fed via class C chopper, presented in Fig. 3, having the following parameters:R a=0.271Ω,L a=0.41mH, J=0.00074 kgm2, B v=0.0013Nm/rad/s, K aψ= 0.0527V/rad/s.The simulation is performed in the time domain and the sampling period of A/D converter is T =1ms, dc input voltage V =24 and reference speed w ref=188.5 rad/s. The load torque T L was defined as a linear function of rotor speed w r having the operating point (T L =0.26Nm, w r =188.5 rad/s). KE1 in the block diagram given in Fig. 7 is the gain of tacho-generator, W ref1 and W ref , which are the step functions to change the sign of change of error in first sampling. The block of signal generator supplies 2 kHz sawtooth waveform having the magnitude of one; hence, the control signal generated bythe FLC will be equal to the duty cycle of the gate signals applied to the power switches. During simulation process when the change of error is calculated, noise on output of the A/D converter has appeared because change of error in time of 1ms is a very small value, so we have a problem of least significant bit in the number. To eliminate this effect additional gain blocks are introduced before the A/D converter block. So it is necessary to divide after A/D converter output and that is why KE and KCE are placed in the configuration.Fig. 8 shows the variation of actual rotor speed and armature current in time, when the load torque is increased by the amount of 0.17Nm at 0.4 s. The actual rotor speed deviates from the reference speed and comes back to the reference after transients are damped out. The increase of armature current is the response to increase of load torque.5.Hardware and software designsThe hardware setup for the proposed fuzzy logic algorithm was implemented in assembly programming, using 8-bit RISC (Reduced Instruction Set Computing) core microcontroller AT90S8535. A schematic diagram of the FLC with one of the Insulated Gate Bipolar Transistor (IGBT) drive circuits of Class C chopper is shown in Fig. 9. The microcontroller has 8K bytes of programmable flash memory, 512 bytes of internal random access memory, 8 channel 10 bit ADC, 10 bit PWM output, 16 different interrupt sources, an analog comparator, 32 programmable I/O lines, a bi-directional serial interface and has the ability to execute assembler instructions in a single clock cycle. The processing speed is one million instructions per megahertz crystal (Atmel Corporation).The universe of discourse for error and change of error are extended from -1024 to +1024 and the grades of each membership function (0–1) are also extended from 0 to 1024. In order to classify the fuzzy controller inputs, e(k) and ce(k), into seven fuzzy sets and to determine their memberships, 10 bit mathematical routines are used. Therefore, processing the on-chip 10 bit A/D converter sampling values and setting up the on-chip 10 bit PWM output for semiconductor switches are directlyachieved. As a result, the total system resolution is extended to 1/1024 insteadof 1/256 and better performance is obtained.The symmetrical and 50% overlapped triangular membership functions of e(k) and ce(k) simplify the calculations and its negative side is a reflection of the positive. The fuzzy subset linguistic rule table given in Table 1 is changed to integer numbers in order to suit assembly programming. A simple but effective algo-rithm is designed for the appropriate numerical values ofconverted linguistic rules. This is realized with the following equation according to calculated error values.The most important difference between the present paper and the papers cited in the references, is the developed algorithm for fast calculation.For error membership function,where e is the error value, X min=-1024 is the minimum value of the control variable as shown in Fig. 4a, s is the section number, starting from 0 to 6 for representing seven fuzzy subsets of errormembership and T g the width of every triangular membership function, here it is 256.For instance, let w ref =1000 rpm and w act =650 rpm. The calculation of error according to Eq. (2) is e(k)=350 rpm at a point x shown in Fig. 4b and from Eq. (8),is calculated. This value should be classified into fifth fuzzy set. It is well known that every e(k) belongs to at most two fuzzy sets. Therefore, the above error value has two overlapping fuzzy sets, fifth and sixth which are prevailed to linguistic PS and PM as shown in Fig. 4b. The fraction part of s always belongs to the membership function which has a positive slope. Therefore, for this example, the membership grade at point b shown in Fig.4b isμpm(e)=0.36719.The sum of membership grades of two symmetrical and 50% overlapped triangular fuzzy sets is always equal to 1.0μpm(e)+μps(e)=1.0.Hence the membership grade at point a isμps(e)=1.0-0.36719=0.63281.At the kth sampling time, change of error membership function is also evaluated using the same Eq. (8). The calculated values of fuzzy variables are used in the decision-making process. The flow chart of implemented assembler program is shown in Fig. 10.Membership functions of the output duty cycle for application on a PMDCM drive is presented in Fig. 5.A table is created for defuzzification process and stored as a look-up table containing the mean values of these membership functions of output and are used according to the weighted average method for defuzzification. The weighted average method for the defuzzification has an advantage over the other techniques in the case of limited memory structure of RISC core microcontrol-lers. A crisp value for the change of duty cycle is calculated from Eq. (6). According to Eq. (7) and the change of output of FLC shown in Fig. 5, the calculated change of the duty cycle is used to determine the new duty cycle for the application,The calculated value is used to update the PWM output by an interrupt routine shown in Fig. 10 at every 1ms (milli-second). Tests have shown that realization of the mentioned fuzzy interrupt routine lasts 450 ms (micro-second) processing time with 4MHz clock frequency. In this implementation, a D/A converter,which might be needed for output variable is eliminated by directly controlling the on–off periods of semicon-ductor switches via the on-chip PWM generator. When the motor is started from standstill, the error and change of error are estimated as positive at first sampling of rotor speed since their initial value at standstill are taken to be zero. The trend of change of error from standstill to steady state of rotor speed is negative; therefore, by changing the sign of change of error from positive estimated at first sampling to negative reduces the settling time of the rotor speed.6.ResultsAnother identical machine was coupled to the motor via their shafts and operated as a generator for loading. Two different loading conditions were applied on the motor. In the first loading condition, the generator terminals were closed to the resistive load of 2Ωand, the rotor speed and armature current variations in time during this loading case were recorded. These results are given in Fig. 11a (Upper trace: 1V/div., Lower trace: 0.2V/div. and 100mV/A. Time base: 200ms/div.). In the second loading condition, the resistance of 2Ωwas connected to the generator terminals while the rotor is running at reference speed. After the transients were damped out, the resistor was disconnected. The varia-tions of actual rotor speed and generator output current during this case were recorded and are given in Fig. 11b (Upper trace: 1V/div., Lower trace: 0.2V/div. And 100mV/A, Time base: 500ms/div.). It can be observed from the waveforms that the fuzzy logic controller responds to the step change on the load properly and brings the actual rotor speed back to the reference speed.7.ConclusionFuzzy logic controller is implemented without mod-ified methods byusing a general purpose low-cost microcontroller for the speed control of a PMDCM. All the tasks are carried out bya single chip reducing the cost of the system and program code optimization is achieved with developed effective algorithm. In our approach, the software-based decision table is used and only simple computations required in the on-line control of an FLC; therefore, higher sampling rate can be realized more easily when comparing with other type of control schemes. The developed fuzzy logic controller was simulated in MA TLAB/SIMULINK. Simulation and experimental results are compared in order to show the response of the FLC under loading conditions. It can be found that the experimental results are very close to the simulation results. The rise and settling times are reasonably smaller and there is no significant overshoot on the experimental results. The effect of saturation is not included into the motor and generator models; therefore, the simulation results deviate from the experimental results within a small percentage during loading transients. The experiments indicate that the implemented fuzzy controller has a high performance for real time control over a wide range of operating conditions.ReferencesAtmel Corporation. . A VR RISC datasheets, application notes, tools.Bart Kosko, 1991. Neural Networks and FuzzySystems. Prentice-Hall, New York. Brandsetter, P., Sedlak, P., 1996. Fuzzycontrol of electric drive using DSP, PEMC’96, Budapest, Hungary, pp. 3/462–3/466.Gupta, T., Boudreaux, R.R., Nelms, R.M., Hung, J.Y., 1997. Implementation of a fuzzycontroller for DC–DC converter using an inexpensive 8-b Microcontroller. IEEE Transactions on Industrial Electronics 44 (5).Hyo, S.Park, Hee, J.Kim., 2001. Simultaneous control of buck and boost DC–DC converter byfuzzycontroller. ISIE 2001 Proceed-ings, Pusan, Korea, pp. 1021–1025.Jan Jantsen, 1998. Design of FuzzyControllers, Technical Uni-versityof Denmark, Department of Automation, Pub. No: 98-E-864.Lee, C.C., 1990. Fuzzylogic in control systems: fuzzylogic controller.Part I, II. IEEE Transactions on Systems Man and Cybernetics 20(2), 404–435.Mattavelli, P., Rossetto, L., Spiazzi, G., Tenti, P., 1997. General purpose fuzzycontroller for DC–DC converters. IEEE Transac-tions on Power Electronics 12 (1).Pires, V.F., Silva, J.F.A., 2002. Teaching nonlinear modeling, simulation, and control of electronic power converters using.MA TLAB/SIMULINK. IEEE Transactions on Education 45 (3).Ross, T.J., 1995. FuzzyLogic with Engineering Applications.McGraw-Hill, New York.So, W.C., Tse, C.K., Lee, Y.S., 1995. An experimental fuzzy controller for DC–DC converters. IEEE Power Electronics Specialist Con-ference Record. pp. 1339–1345.So, W.C., Tse, C.K., Lee, Y.S., 1996. Development of a fuzzy logiccontroller for DC/DC converters: design, computer simulation and experimental evaluation. IEEE Transactions on Power Electronics11, 1.Vas, P., 1998. Sensorless Vector and Direct Torque Control. Oxford University Press, Oxford. Vas, P., 1999. Artiﬁcial Intelligence Based Electrical Machines and Drives. Oxford UniversityPress, New York.Zakharov, A., 1996. Investigation of dc servo drive with fuzzy logic control. M.Sc. Thesis, Technical Universityof Budapest, Depart-ment of Electrical Machines and Drives.。

硬件设施也需要柔软作文

硬件设施也需要柔软作文英文回答：Hardware facilities also require softness. While hardware is crucial for the functioning of any system or device, it is the soft aspects that enhance the overall user experience and make the hardware more user-friendly.One example of the need for softness in hardware facilities is the design of smartphones. The hardware components of a smartphone, such as the processor, memory, and screen, are important for its performance. However, it is the soft aspects such as the user interface, operating system, and apps that make the smartphone easy to use and navigate. For instance, a well-designed user interface with intuitive icons and menus allows users to easily access the features and functions of the smartphone. This soft aspect enhances the overall user experience and makes the hardware more user-friendly.Another example is the design of smart homes. The hardware components of a smart home, such as sensors, cameras, and smart devices, are essential for automationand control. However, it is the soft aspects such as the user interface, voice recognition, and automationalgorithms that make the smart home easy to operate and manage. For example, a smart home with a user-friendly interface and voice recognition technology allows users to control various devices and systems with simple commands. This soft aspect enhances the convenience and comfort of living in a smart home.中文回答：硬件设施也需要柔软。

1.1. INTRODUCTION Basic Fuzzy Mathematics for Fuzzy Control

on the circumstance. For the above age example, X = [0, 130]. Letting A denote fuzzy set "young," we can represent its membership function by jU^(x), where x eX. People have different views on the same (vague) concept. Fuzzy sets can be used to easily accommodate this reality. Continue the age example. Some people might think age 50 is "young" with membership value as high as 0.9, whereas others might consider that 20 is "young" with membership value merely 0.2. Different membership functions can be used to represent these different versions of "young." Figure 1.3 shows two more possible definitions of the fuzzy set "young." Not only do different people have different membership functions for the same concept, but even for the same person, the membership function for "young" can be different when the context in which age is addressed varies. For instance, a 40-year-old president of a country would likely be regarded as young, whereas a 40-year-old athlete would not. Two different fuzzy sets "young" are needed to effectively deal with the two situations. These examples show that (1) fuzzy sets can practically and quantitatively represent vague concepts; and (2) people can use different membership functions to describe the same vague concept. We now introduce some definitions needed to describe fuzzy control crisp set "young" is given in Fig. 1.1. This set is unreasonable because of the abrupt change of the membership value from 1 to 0 at 35. Although a different cutoff age at which membership value changes from 1 to 0 may be used, a fundamental problem exists. Why is it that a 34.9-year-old person is completely "young," while a 35.1-year-old person is not "young" at all? No crisp set can realistically capture, quantitatively or even qualitatively, the essence of the vague concept "young" to reasonably match what "young" means to human beings. This simple example is not meant to discredit the traditional set theory. Rather, the intention is to demonstrate that crisp sets and fuzzy sets are two different and complementary tools, with each having its own strengths, limitations, and most effective application domains.

hardware

Evaluating cost and effectiveness of software redundancy techniques forhardware errors detectionM. Rebaudengo, M. Sonza Reorda 1Politecnico di TorinoTorino, Italy1 Contact Author:M. Sonza Reorda, Politecnico di Torino, Dip. Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 Torino - Italy Phone: +39 11 564.7055, Fax.: +39 11 564.7099, E-mail: sonza@polito.it1. IntroductionRedundancy is a common answer to the increasing demand of high dependability in safety-critical applications. In this paper we consider low-cost computer-based systems; in such systems hardware redundancy is unacceptable and software redundancy is the only design modification which can possibly be introduced to improve the system fault tolerance.Different software fault tolerant approaches have been proposed to address different kinds of error sources [TJPr96][RMSi96]. To achieve a high degree of fail-silent behavior in ordinary computers the intrinsic Error Detection Mechanisms (EDMs) of the system (exceptions, memory protection, etc.) can be complemented with a set of carefully chosen software error detection techniques [RMSi96]. These techniques include Algorithm Based Fault Tolerance (ABFT)[HuAb84], Assertions , and Code Flow checking. The technique adopted here is based on variable duplication:as a main advantage, it can be automatically implemented on the high-level code of the program.The paper performs some analysis about the cost and effectiveness of this approach.2. The FATO approachThis paper adopts the Software Error Detection approach called FA TO [BCPR97], based on source code modification and data redundancy , that aims at increasing the robustness of the system with respect to hardware errors in the memory and registers.The main idea of the approach is to perform two different modifications to the source code; the first one corresponds to duplicating some or all of the program variables in order to introduce data redundancy and modifying all the operators to manage the introduced replica of the variables. The second one aims at introducing consistency checks inside the control flow to periodically verify the consistency between the two copies of each variable. This approach has been developed mainly to detect transient bit-flip faults in memory locations storing the data and in the microprocessor's user registers.As a simple example, Fig. 1 shows a code modification for a sum operation among three variables a , b and c .Originala =b + c:Modifieda 0 =b 0 +c 0;a 1 = b 1 + c 1;if (b 0 != b 1 || c 0 != c 1) error();Fig.1: Code modification.3. Trading-off fault coverage and CPUTime overheadIn some cases, safety-critical applications have strict constraints in terms of memory occupation and system performance. The duplication of the whole set of variables and the introduction of a consistency check before every read operation represent the optimum choice from the fault coverage point of view. We consider only faults appearing in the data memory during the life period of each variable. With this assumption, the duplication of the whole set of variables guarantees that 100% of faults is covered by this software redundancy technique. On the other side, by duplicating a lower percent of variables one can trade-off the obtained fault coverage with the CPU time overhead.In this paper we propose an analysis of the code useful to choose a good trade-off between system overhead and fault coverage achieved with variable duplication and consistency checks for a low-cost safety critical computer-based system. An experimental analysis is currently being performed, considering a set of benchmark programs; the preliminary experimental results reported here refer to a representative program which emulates a railway control system in a small railway station with 2 railroads.To avoid the duplication of the whole set of variables, we propose an analysis of the data trace of a fault-free execution of the target application. This allows to determine the life time of each variable (corresponding to the cumulative length of the longest time intervals between a write operation and the following read operations, not containing other write operations). V ariables are ordered according to their life time, and those with the largest life time are duplicated.In fact, the larger the life time is, the higher the probability that an error affecting this variable occurs.We assume that all the faults in a duplicated variable are detected by the FA TO approach.Fig. 2 shows the CPU time overhead introduced in the benchmark program by duplicating a decreasing number of variables, selected according to the above strategy. The fault coverage achieved by duplicating a subset of variables ranging from 10% to 100% has been experimentally evaluated and reported in Fig. 3. The experimental results with our benchmark show that duplicating 50% of the variables is enough to guarantee a Fault Coverage of 85% with a reduced CPU time overhead (28%).262,29199,30147,9428,3417,2384,72950100150200250300100%90%70%50%30%10%0%Duplicated VariablesC P U T i m e [%]Fig. 2: CPU time overhead vs. the percentage ofduplicated variablesAnother parameter that has to be carefully set to decrease the code size and the execution time overhead is the consistency check granularity . In particular,different solutions can be chosen in terms of where to introduce the consistency checks:• after each read operation ;• at the end of each life period .The number (provided that is greater than 1) and position of the consistency checks do not modify theachieved fault coverage: if the variable is duplicated,any fault appearing in its life period is detected.Introducing a check after each read operation is the safest choice, giving the minimum latency of a fault. On the other side, this solution gives a high overhead in terms of CPU time. Introducing a check at the end of each life period increases the latency with a reduced cost in terms of CPU time. A more precise analysis of the link between the number of introduced consistency checks and the latency is currently under analysis.4. ConclusionsIn this paper we report some data about the costs (in terms of CPU time) and advantages (in terms of Fault Coverage) of a previously proposed technique [BCPR97] for software redundancy to improve fault tolerance in low-cost computer-based safety critical systems. The proposed approach is based on variable duplication and consistency check introduction. An exhaustive application of this approach could dramatically increase the resources (CPU time and memory) overhead; therefore, a balanced trade-off has to be defined between fault coverage and overhead. We propose to study the system fault-free behavior to decide the variables to be duplicated and checked,ordering the variables taking into account their life period.Work is currently being done in optimizing the automatic modification of the source code in order to tune the number of variables to be duplicated and the granularity of the consistency checks to be inserted in the code, introducing more sophisticated techniques for code analysis.5. References[BCPR97] A. Benso, F. Corno, P. Prinetto, M. Rebaudengo,M. Sonza Reorda, FATO: a software FAult TOlerant approach, IEEE International On-Line Testing Workshop, July 1997[HuAb84]K. H. Huang, J. A. Abraham, Algorithm-BasedFault Tolerance for Matrix Operations, IEEE Trans. Computers, vol. 33, 1984, pp. 518-528[PVBW88]D. Powell, P. Verissimo, G. Bonn, F.Waeselynck, D. Seaton, The Delta-4 Approach to Dependability in Open Distributed Computing Systems, Proc. FTCS-18, 1988, pp. 246-251[RMSi96]M. Zenha Rela, H. Madeira, J. G. Silva,Experimental Evaluation of the Fail-Silent Behavior in Programs with Consistency Checks ,Proc. FTCS-26, Sendaj (J), 1996, pp. 394-403[TJPr96] D. Todd Smith, T. A DeLong, B. W. Johnson, J.A. Profeta III, An Algorithm Based Fault Tolerant Technique for Safety Critical Applications ,Reliability and Maintainability Symposium,Philadelphia, 199710046,671,6395,299,585,8220406080100120100%90%70%50%30%10%D uplicated Variables [%]F a u l t C o v e r a g e [%]Fig. 3: Fault Coverage vs. the percentage of duplicated variables。

S2-LP Sigfox firmware framework user 说明书

UM2173User manualGetting started with the S2-LP Sigfox firmwareIntroductionThe S2-LP Sigfox firmware framework provided by ST allows you to develop embedded applications on the STEVAL-FKI868V2, STEVAL-FKI915V1, the X-NUCLEO-S2868A2 and the X-NUCLEO-S2915A1 platforms.The package also includes the support for the STEVAL-IDB007V2 and STEVAL-IDB008V2 kits to be used with the shields included in the above mentioned kits. This enables the support for BlueNRG-1 and BlueNRG-2 System-on Chip. STEVAL-FKI001V1 and the STDES-MONARCH are also supported with dedicated firmware binaries and configurations.You should first read user manual UM2169 Getting started with the Sigfox S2-LP kit, which explains how to prepare the board with a Sigfox ID/PAC/KEY and to register the node on your backend account.Hardware requirements 1Hardware requirementsA Windows® PC with:• 2 USB ports•135 MB free hard disk spaceAt least one of the following ST evaluation kits:•STEVAL-FKI868V2 or X-NUCLEO-S2868A2 (for RC1, RC3, RC5 and RC6) kit with STM32 Nucleo-64 development board or STEVAL-IDB007V2/IDB008V2 board•STEVAL-FKI915V1 or X-NUCLEO-S2915A1 (for RC2 and RC4) with STM32 Nucleo-64 development board or STEVAL-IDB007V2/IDB008V2 board•STEVAL-FKI001V1 development kit2Firmware architectureThe firmware consists of stacked modules in a framework where each module demands the implementation of lower level functions from the module beneath it.Figure 1.Sigfox firmware application2.1RF_APIThe rf_ap library is responsible of the S2-LP configuration and implementation of the modulation scheme.This library drives the S2-LP according to the Sigfox modulation protocol:•DBPSK for uplink (14dBm at 100bps for RC1/3/5, 22dBm at 600bps for RC2/4)•2GFSK, BT=1 for downlink The channel frequency, datarate and other relevant parameters depend on the applicable radio control zone (RC).Exported callbacks are:Firmware architectureNVM API2.2NVM APIThis is the layer use to read/write in FLASH or EEPROM all the information handled by the Sigfox library (forexample messages counter).Main functions are:2.3MCU_APIIf the platform changes, but the processor type remains the same, you only need to re-implement the MCU_APImodule. This means that the framework can easily be ported to another board equipped with a microprocessor ofthe same type but with a different pinout by simply re-implementing this module.Main functions are:2.4ST retriever libThis module is in charge of perform all the encryption routines and to retrieve the credentials from the device.Main funcions are:2.5ST Monarch libThis module performs all the operation to scan the air and detect Sigfox Monarch beacons.Main functions are:3Application developmentEmbedded applications using the Sigfox framework call SIGFOX_APIs to manage communication.Table 1. Application level Sigfox APIsThe application should call a set of functions in order to instruct the RF_LIB to configure the radio in the proper way.These are the main functions exported by the ST_RF_API header (st_rf_api.h) and are implemented into the Section 2.1 RF_API module.Table 2. ST_RF_API3.1Opening the librarySIGFOX_API_open must be called to initialize the library before performing any other operation.This API requires pointer to the Radio Configuration zone struct to be used.Uplink frequencies are avilable at https:///sigfox-radio-configurations-rcNote:As frequency hopping is implemented, the transmission frequency won’t be fixed.For radio control zones 2 and 4 (FCC), refer toSection 3.3 node_set_std_config command description for how to map the macro channels.Downlink frequencies are available at: https:///sigfox-radio-configurations-rc3.2Sending framesSIGFOX_API_send_frame is the core Sigfox library function; this blocking function handles message exchange between the node and the base-stations.An important parameter of this function is initiate_downlink_flag:•When the initiate_downlink_flag is 0, the library only reads the first two parameters. The send frame istransmitted three times with a 500 ms pause.Figure 2. TX Frame timing•When the initiate_downlink_flag is 1, the send frame is transmitted tx_repetition times + 1 (max. 3) with a 500 ms pause. A 25 s RX window then opens 20 s after the end of the first repetition.Figure 3. TX/RX timingsOpening the librarynode_set_std_config command description If the reception is successful, the received 8-byte downlink frame is stored in the buffer location indicated by thecust_response input parameter.The content of the frame can be set in the backend or by registering a callback to a website.3.3node_set_std_config command descriptionThis function has different purposes according to the RC mode at which the serial port is open. FCC allows thetransmitters to choose certain macro channels to implement a frequency hopping pattern allowed by the standard.The channel map is specified in the first argument of SIGFOX_API_set_std_config, which consists of anarray of three 32-bit configuration words.Note:This API and its arguments are not applicable to RC1.Each bit of the config_words[0,1,2] array represents a macro channel according to the following mapping:Table 3. Macro channel mapping - config_words[0]Table 4. Macro channel mapping - config_words[1]Table 5. Macro channel mapping - config_words[2]A macro channel is only enabled when the corresponding config_words[] bit is set to 1. At least 9 macrochannels must be enabled to meet the FCC specifications.The second argument is a boolean indicating whether to use a timer feature in RC2 or 4 to be sure fulfilling theFCC duty cycle requirements.In RC3 the function is used to configure the LBT mode.config_word[0]: number of attempts to send the first frame (has to be greater or equal to 1)config_word[1]: maximum carrier sense sliding window (in ms) (greater than 6 ms)config_word[2]: bit 8: set the value to 1 to indicate that the device will use the full operational radio band (192kHz). bit 7-3: number of carrier sense attempts. bit 2-0: number of frames sent.timer_enable: unusedThe delay between several attempts of carrier sense for the first frame is set by SFX_DLY_CS_SLEEPThis setting only affects the uplink and should be called whenever SIGFOX_API_open is called to open thelibrary.Duty cycle 3.4Duty cycle3.4.1RC1The European regulation governing the 868 MHz band enforces a transmission duty cycle of 1%. Since eachmessage can last up to 6 seconds, it is possible to send up to 6 messages per hour.Your application must take this duty cycle into account in order to comply with the ETSI regulation.3.4.2RC2/4According to FCC 15.247, each device should ensure that continuous transmission never exceeds 400 ms andthat a given frequency channel is not reused inside 20 seconds. These limits are ensured by defining at least 9macro-channels via SIGFOX_API_set_std_config.Each macro-channel is a group of 6 25 kHz bandwidth channels with which the library performs randomfrequency hopping. There must be at least 9 macro-channels to satisfy the minimum 50 channel limit set in FCC15.247.When the SIGFOX_API_send_frame is called:1.the device transmits 3 repetitions on 3 different channels of the default macro-channel hopping list2.the second transmission takes place over the other 3 channels available on the same macro-channel3.the third transmission hops to another listed macro-channel and uses 3 channels from that group4.hopping and transmission continues according to the same logicSince the transmission lasts between 200 and 350 ms and a minimum delay of 500 ms occurs between frames,the device never returns to a given channel inside 20 seconds.The Sigfox base stations installed in RC2 are currently enabled to receive in the macro channel 1. The ones in theRC4 are enabled to receive on the 63rd channel.Any transmission performed over a different macro channel from the default is lost.Listen before talk 3.5Listen before talk3.5.1RC3/5In RC3/5, the transmitter should sense the channel before starting to transmit.For this reason, each TX phase into the figures 3 and 4 is preceded by a RX phase of variable duration.The duration of the listen before talk is called carrier sense time.This time can be in the range [cs_min, cs_max].The timings cs_min is 5ms, cs_max is defined by the user into the config_word[1] argument of theSIGFOX_API_set_std_config.The behavior of the LBT is the following:•Enter in RX•If no power >-80dBm is detected within the cs_min window, the LBT exits with success allowing a new transmission•If a power > -80dBm is detected and no cs_min time has elapsed with the power <-80dBm, the LBT exits with error, preventing a new transmission.Case no power detected:Figure 4. Behavior of the LBT above -80dBm is detected within the cs_min windowFigure 5. Behavior of the LBT -80dBm is detected and no cs_min time has elapsed with the power below-80dBmIf the channel is found busy for the cs_max time, the transmission will fail with error code 0x7D.The LBT is implemented by the ST RF_API in the following way.When a LBT cycle must be done, the lib will call the function MCU_API_timer_stop_carrier_sense.This timer will start to count the cs_max time.Then, the library will call the RF_API_wait_for_clear_channel function. In its implementation, the MCU willprogram the S2-LP as follows:•Set the RSSI_THRESHOLD=-80dBm (this is an argument of the function)•Register the 2 interrupts RX_TIMEOUT and RSSI_ABOVE THRESHOLD.•Program the RX TIMEOUT to the cs_min (passed to the function as an argument)•Set the device in RX and go into low power mode.Application example •If the RX timeout arises, it means that one cs_min window has elapsed without anyRSSI_ABOVE_THRESHOLD (no RSSI detected) for the current cs_min window. Return without error afterhaving disabled all the IRQs on the S2-LP.If the RSSI_THRESHOLD is raised, stop the RX and restart it again. If the channel becomes free at some pointwithin the cs_max and it is kept free for a time equal to cs_min, the RX_TIMEOUT interrupt will be raised and thefunction will return with no error. Otherwise the radio will be continuously stopped until the cs_max timeout(started by the MCU_API_timer_stop_carrier_sense) occurs, in this case the function returns with error.3.6Application exampleTo develop an application on the supported platforms, the application should:1.Initialize the hardware:–System clock–S2-LP SPI initialization–S2-LP SDN pin initialization2.Retrieve the crystal frequency and the carrier offset from the manufacturer data E2PROM, via the functionS2LPManagementIdentificationRFBoard().3.Retrieve the Sigfox ID, PAC and RC via the function enc_utils_retrieve_data orenc_utils_retrieve_data_from_flash. Assume that this function will return the ID of the board in thevariable uint32_t id.The procedure for opening and setting the library differs slightly for each radio control zone and is described bythe ST_Sigfox_Open_RCZ function in the St_Sigfox_Init.c file of the SDK.Assuming you have the 4-byte customer_data buffer to send and no downlink request:•SIGFOX_API_send_frame(customer_data,4,customer_resp,0,0);With donwnlink request:•SIGFOX_API_send_frame(customer_data,4,customer_resp,0,1);The function will return after about 50 seconds and, in the absence of errors (error code = 0), the customer_respbuffer will be filled with an 8-byte response.For further details, refer to the SigFox_PushButton_Project or the SigFox_CLI_Demo_Project example code andcorresponding doxygen documentation in the ST-Sigfox package.3.7Test modeThe test modes are available in the separate library ADDON_RF_PROTOCOL API.In order to access the test modes, it is necessary to close the Sigfox library.The test mode API is the following:sfx_error_t ADDON_SIGFOX_RF_PROTOCOL_API_test_mode (sfx_rc_enum_t rc_enum, sfx_test_mode_ttest_mode)where:- rc_enum is a number representing the number of RC.- test_mode is a number representing the test_mode.Please see the doxygen documentation included in the package STSW-S2LP-SFX-DK.The test mode should be used to perform the Sigfox verified certification using the SDR Dongle and the RSAEnvironment. For more information visit https:///sdr-dongle.4Current consumption on ST reference design4.1Current consumption for the STEVAL-FKI868V2 (for RC1/3)The current consumption of the S2-LP and of the STM32L152 is given below for both TX and RX phases.In the non-active phases, the S2-LP is maintained in shutdown mode with negligible current consumption.4.1.1TransmissionDuring transmission, the averaged current on the S2-LP on the STEVAL-FKI868V2 is about 17 mA.Figure 6.S2-LP TX current profile for STEVAL-FKI868V2051015202500.20.40.60.811.21.41.6c u r r e n t [m A ]time [s]The current on the STM32 side is much lower because the microcontroller is set in low power mode for most of the transmission phase: it is only woken during transmission when the TX FIFO must be filled with new data.The resulting current profile shows some 7 mA spikes every 10 ms, with troughs in between representing the sleep current below 10 µA.Figure 7.microcontroller TX current profile for STEVAL-FKI868V2012345678900.050.10.150.20.25c u r r e n t [m A ]time [s]Current consumption on ST reference designFigure 8.microcontroller TX current profile - zoom024681000.0020.0040.0060.0080.010.012c u r r e n t [m A ]time [s]4.1.2ReceptionAccording to the Sigfox protocol, reception lasts a maximum of 25 seconds. During this time, the S2-LP current consumption remains around 7.5 mA and the STM32 is maintained in stop mode with a current below 10 µA.Figure 9.S2-LP and microcontroller RX current profile for STEVAL-FKI868V2012345678900.020.040.060.08c u r r e n t [m A ]time [s]µC current (RX)S2-LP current (RX)4.2Current consumption for the STEVAL-FKI915V1 (for RCZ2/4)For the STEVAL-FKI915V1, we need only consider the current on the S2-LP and on the FEM (Skyworks-SE2435L) as the current consumption of the STM32 is the same as for the STEVAL-FKI868V2.In the non-active phases both the S2-LP and FEM are kept under shutdown and their current consumption is negligible.4.2.1TransmissionThe average current consumption of the S2-LP during frame transmission is about 5 mA.Figure 10.S2-LP TX current profile for FKI915V10123456700.050.10.150.20.250.3c u r r e n t [m A ]time [s]The 22 dBm power is provided by the FEM, with the following current shown below.Figure 11. FEM TX current profile for FKI915V10.00E+005.00E+011.00E+021.50E+022.00E+022.50E+020.050.10.150.20.250.3c u r r e n t [m A ]time [s]4.2.2ReceptionAccording to the Sigfox protocol, the reception lasts a maximum of 25 seconds. During this time, the current consumption of the S2-LP is constant, at about 8.7 mA, while the FEM has a consumption of 7 mA.Figure 12.S2-LP and FEM RX current profile for STEVAL-FKI915V101234567891000.010.020.030.040.050.060.070.08c u r r e n t [m A ]time [s]FEM current S2-LP currentRevision historyTable 6. Document revision historyContentsContents1Hardware description (2)2Firmware architecture (3)2.1RF_API (3)2.2NVM API (4)2.3MCU_API (4)2.4ST retriever lib (5)2.5ST Monarch lib (5)3Application development (7)3.1Opening the library (10)3.2Sending frames (10)3.3Set standard configuration (11)3.4Duty cycle (12)3.4.1RC1 (12)3.4.2RC2/4 (12)3.5Listen before talk (13)3.5.1RC3/5 (13)3.6Application example (14)3.7Test mode (14)4Current consumption on ST reference design (15)4.1Current consumption for the STEVAL-FKI868V2 (for RC1/3) (15)4.1.1Transmission (15)4.1.2Reception (16)4.2Current consumption for the STEVAL-FKI915V1 (for RCZ2/4) (16)4.2.1Transmission (16)4.2.2Reception (17)Revision history (19)List of tablesTable 1. Application level Sigfox APIs (7)Table 2. ST_RF_API (8)Table 3. Macro channel mapping - config_words[0] (11)Table 4. Macro channel mapping - config_words[1] (11)Table 5. Macro channel mapping - config_words[2] (11)Table 6. Document revision history (19)List of figuresFigure 1. Sigfox firmware application (3)Figure 2. TX Frame timing (10)Figure 3. TX/RX timings (10)Figure 4. Behavior of the LBT above -80dBm is detected within the cs_min window (13)Figure 5. Behavior of the LBT -80dBm is detected and no cs_min time has elapsed with the power below -80dBm (13)Figure 6. S2-LP TX current profile for STEVAL-FKI868V2 (15)Figure 7. microcontroller TX current profile for STEVAL-FKI868V2 (15)Figure 8. microcontroller TX current profile - zoom (16)Figure 9. S2-LP and microcontroller RX current profile for STEVAL-FKI868V2 (16)Figure 10. S2-LP TX current profile for FKI915V1 (17)Figure 11. FEM TX current profile for FKI915V1 (17)Figure 12. S2-LP and FEM RX current profile for STEVAL-FKI915V1 (18)IMPORTANT NOTICE – PLEASE READ CAREFULLYSTMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.No license, express or implied, to any intellectual property right is granted by ST herein.Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to /trademarks. All other product or service names are the property of their respective owners.Information in this document supersedes and replaces information previously supplied in any prior versions of this document.© 2020 STMicroelectronics – All rights reserved。

笔记本安装无线网卡驱动Intel

目录前言 (2)系统篇 (2)让非root用户可以读写mount的vfat分区 (2)查看你的机子是64位还是32位 (2)安装 liva 源 (2)更新FC6.2798Kernel版本的一个字体错误 (3)如何设置XINE自动播放DVD (3)笔记本安装无线网卡驱动Intel 3945ABG (3)用ntfs-3g挂载ntfs，及移动硬盘NTFS分区自动挂载 (5)多媒体 (6)使XMMS可以正确显示中文 (6)XMMS的WMA插件安装 (7)MP3插件安装 (7)安装Flash/Shockwave 插件 (7)安装DVD 播放器XINE (7)让系统支持RMVB AVI RM VCD DVD FC6 (7)应用篇 (9)让系统支持在GUI中解压RAR文件 (9)连接到win2000 server or windowsXP的远程桌面连接 (10)游戏篇 (10)让Linux玩Windows游戏的Cedega 5.0安装指南 (10)开发篇 (12)Running Visual Sourcesafe under Linux (13)前言作者Alfie声明，对于本文档无版权，目的只是为了方便自己更好的使用FC6。

内容都来自于各大讨论网站，例如：等如果有作者觉得本文档侵犯了版权，请联系作者（sifeiyong@），作者将给予删除。

当然，作者自用的版本，将保留作者认为有用的东西，：）感谢互联网，因为有了互联网，才让我可以更好的使用FC6。

系统篇让非root用户可以读写mount的vfat分区修改原始的mount命令（位于/etc/fstab目录中）。

原始的mount命令如下：/dev/hda5/media/hda5vfat defaults00修改为：/dev/hda5/media/hda5vfat uid=500, rw00注意：uid在系统的用户设置中可以看到，请修改为你要使用的用户的id查看你的机子是64位还是32位$ uname -mx86_64...or...i686安装 liva 源如果你不清楚是32还是64，你可以不用管了，直接在终端执行下边这个命令：#rpm-ihv/fedora/linux/6/i386/RPMS.freshrpms/freshrpms-release-1.1-1.fc.noarch.rpm如果是32位的，你可以用下边这个命令：＃ rpm -ihv /fedora/6/i386/livna-release-6-1.noarch.rpm如果是64位的，你可以用下边这个命令:# rpm -ihv /fedora/6/x86_64/livna-release-6-1.noarch.rpm然后，将Liva源导入：# rpm --import /RPM-LIVNA-GPG-KEY更新FC6.2798Kernel版本的一个字体错误# mkdir -p /usr/X11R6/lib/X11/fs/# ln -s /etc/X11/fs/config /usr/X11R6/lib/X11/fs/config如何设置XINE自动播放DVD如果你运行上边命令后，碟放进去，不能自动播放，你可以点System -> Preferences -> Removable Drives and Media.也就是系统－＞首选项－＞可移动驱动器和介质，来使其运行，你也可以执行下边命令：xine --auto-play --auto-scan dvd笔记本安装无线网卡驱动Intel 3945ABG1. 添加atrpms 源# gedit /etc/yum.repos.d/atrpms.repo添加以下内容：安装 key：# rpm --import http://A T /RPM-GPG-KEY.atrpms2. 安装驱动＃ yum --enablerepo=atrpms install ipw3945-kmdl-`uname-r` ieee80211-kmdl-`uname -r`3. 打开无线网卡脚本：把上面的代码保存为 ipw3945d。

IFB122 Hardware User’s Manual

IFB122Hardware User’s ManualDisclaimersThis manual has been carefully checked and believed to contain accurate information. Axiomtek Co., Ltd. assumes no responsibility for any infringements of patents or any third party’s rights, and any liability arising from such use.Axiomtek does not warrant or assume any legal liability or responsibility for the accuracy, completeness or usefulness of any information in this document. Axiomtek does not make any commitment to update the information in this manual.Axiomtek reserves the right to change or revise this document and/or product at any time without notice.No part of this document may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Axiomtek Co., Ltd.Copyright 2019 Axiomtek Co., Ltd.All Rights ReservedOctober 2019, Version A5Printed in TaiwanSafety PrecautionsBefore getting started, please read the following important safety precautions.1. Be sure to ground yourself to prevent static charge when installing the internalcomponents. Use a grounding wrist strap and place all electronic c omponents in any static-shielded devices. Most electronic components are sensitive to static electrical charge.2. Disconnect the power cord from the IFB122 before making any installation. Besure both the system and the external devices are turned OFF. Sudde n surge of power could ruin sensitive components. Make sure the IFB122 is properly grounded.3. Make sure the voltage of the power source is correct before connecting theequipment to the power outlet.4. Turn OFF the system power before cleaning. Clean the system using a clothonly. Do not spray any liquid cleaner directly onto the screen.5. Do not leave this equipment in an uncontrolled environment where the storagetemperature is below -45℃ or above 85℃. It may damage the equipment.6. Do not open the system’s back cover. If opening the cover for maintenance is amust, only a trained technician is allowed to do so. Integrated circuits on computer boards are sensitive to static electricity. To avoid damaging chips from electrostatic discharge, observe the following precautions:▪Before handling a board or integrated circuit, touch an unpainted portion of the system unit chassis for a few seconds. This will help to discharge anystatic electricity on your body.▪When handling boards and components, wear a wrist-grounding strap, available from most electronic component stores.Classification1. Degree of production against electric shock: not classified2. Equipment not suitable for use in the presence of a flammable anestheticmixture with air or with oxygen or nitros oxide.3. Mode of operation: Continuous4. Type of protection against electric shock: Class I equipmentGeneral Cleaning TipsYou may need the following precautions before you begin to clean the computer. When you clean any single part or component for the com puter, please read and understand the details below fully.When you need to clean the device, please rub it with a piece of dry cloth.1. Be cautious of the tiny removable components when you use a vacuum cleanerto absorb the dirt on the floor.2. Turn the system off before you start to clean up the component or computer.3. Never drop the components inside the computer or get circuit board damp orwet.4. Be cautious of all kinds of cleaning solvents or chemicals when you use it forthe sake of cleaning. Some individuals may be allergic to the ingredients.5. Try not to put any food, drink or cigarette around the computer.Cleaning ToolsAlthough many companies have created products to help improve the process of cleaning your computer and peripherals users can also use household items to clean their computers and peripherals. Below is a listing of items you may need or want to use while cleaning your computer or computer peripherals.Keep in mind that some components in your computer may only be able to be cleaned using a product designed for cleaning that component, if this is the case it will be mentioned in the cleaning.●Cloth: A piece of cloth is the best tool to use when rubbing up a component. Althoughpaper towels or tissues can be used on most hardware as well, we still recommend you to rub it with a piece of cloth.●Water or rubbing alcohol: You may moisten a piece of cloth a bit with somewater or rubbing alcohol and rub it on the computer. Unknown solvents may be harmful to the plastics parts.●Vacuum cleaner: Absorb the dust, dirt, hair, cigarette particles, and otherparticles out of a computer can be one of the best methods of cleaning a computer. Over time these items can restrict the airflow in a computer and cause circuitry to corrode.●Cotton swabs: Cotton swaps moistened with rubbing alcohol or water areexcellent tools for wiping hard to reach areas in your keyboard, mouse, and other locations.●Foam swabs: Whenever possible it is better to use lint free swabs such as foamswabs.Note We strongly recommended that you should shut down the system before you start to clean any single components.Please follow the steps below:1. Close all application programs2. Close operating software3. Turn off power4. Remove all device5. Pull out power cableScrap Computer RecyclingIf the computer equipments need the maintenance or are beyond repair, we strongly recommended that you should inform your Axiomtek distributor as soon as possible for the suitable solution. For the computers that are no longer useful or no longer working well, please contact your Axiomtek distributor for recycling and we will make the proper arrangement.Trademarks AcknowledgmentsAxiomtek is a trademark of Axiomtek Co., Ltd. IBM, PC/AT, PS/2, VGA are trademarks of International Business Machines Corporation.Intel ® and Pentium ® are registered trademarks of Intel Corporation.MS-DOS, Microsoft C and QuickBASIC are trademarks of Microsoft Corporation. VIA is a trademark of VIA Technologies, Inc.SST is a trademark of Silicon Storage Technology, Inc.UMC is a trademark of United Microelectronics Corporation.Other brand names and trademarks are the properties and registered brands of their respective owners.Table of ContentsSafety Precautions ....................................................................................... i ii Classification ............................................................................................... i v General Cleaning Tips ................................................................................. i v Cleaning Tools . (v)Scrap Computer Recycling ......................................................................... v i CHAPTER 1 INTRODUCTION .. (1)1.1General Description (1)1.2System Specifications (2)1.2.1CPU (2)1.2.2System Memory (2)1.2.3Console Port (2)1.2.4LAN (2)1.2.5Storage (2)1.2.6USB (2)1.2.7WatchDog Timer (WDT) (2)1.2.8COM (3)1.2.9Power (3)1.2.10Digital I/O,Relay,Console Connector and Pin Definition (4)1.2.11System LED (7)1.2.12Wireless (3G/GPRS or Wifi) (8)1.2.13Reset Button (8)1.2.14Operation Temperature (8)1.2.15Storage Temperature (8)1.2.16Humidity (8)1.2.17Weight (8)1.2.18Dimensions (8)1.2.19System I/O Outlet (8)1.3Jumper setting (9)1.3.1JP1 (9)1.3.2JP3 (9)1.4Dimensions (10)1.5I/O Outlets (11)1.6Packing List (12)CHAPTER 2 HARDWARE INSTALLATION (13)2.1Installing Din-rail Mounting (13)2.2 Installing Wall Mounting (Opitonal) (13)This page is intentionally left blank.IFB122 U ser’s ManualCHAPTER 1INTRODUCTIONThis chapter contains general information and detailed specifications of the IFB122. The Chapter 1 includes the following sections:⏹General Description⏹System Specification⏹Dimensions⏹I/O Outlets⏹Packing List1.1 General DescriptionIFB122 cost-effective din-rail fanless embedded system utilizes the low power RISC-based module (iMX6UL) processor and is designed to withstand temperatures ranging from -40℃to +70℃for using in extreme operating environment and industrial automation applications.IFB122 features 2 RS-232/422/485 serial ports, dual LANs, 1 DIO Port (2-In/1-Out), 1 eMMC onboard 4GB for storage. Its vertical din-rail form factor makes it easy to install the system in a small cabinet. Due to the RISC-based architecture, IFB122 will not generate a lot of heat while being operated.●Features⏹Fanless⏹Wide temperature operation of -40℃ - +70℃⏹Low power RISC-based module (i.MX6UL), 528MHz Processor⏹ 2 x 10/100Mbps Ethernets with magnetic isolation protection⏹ 2 x COM Ports⏹ 1 x USB 2.0 with power distribution control and over current protection⏹ 1 x DIO Port (2-In/1-Out) with Wet contacts⏹ 1 x Console Port for user setting with debug⏹ 1 x Watchdog Timer⏹LED Indicators (for user config)⏹Storage:Support one eMMC 4GB onboard (for boot disk)⏹ 1 power paths with terminal block and 9–48VDC⏹Din-rail mountingIFB122 U ser’s Manual1.2 System Specifications1.2.1 CPU●Low power RISC-based module (iMX6UL), ARM Cortex-A7 RISC-based 528MHzProcessor1.2.2 System Memory● 1 x DDR3 256MB SDRAM onboard1.2.3 Console Port●For user setting with debug●Connected to DIO terminal Block1.2.4 LAN●LAN 1 / LAN 2⏹10/100Mbps LAN w/ magnetic isolation protection 1.5KV⏹10/100Mbps LAN w/ magnetic isolation protection 1.5KV1.2.5 Storage● 1 x eMMC 4GB onboard (for boot disk)1.2.6 USB● 1 x USB2.0 port1.2.7 WatchDog Timer (WDT)● 1 WatchDog Timer1.2.8COM● DB9 Pin define● RS232/RS422/RS485 (COM1 ~ 2) ● COM 1~2 with TX/RX/RTS/CTS signals ●RS-232/422/485 Interface select by software1.2.9Power● DC input range 9~48V●Power consumption 9~48VDC, 0.55A~0.1A⏹ 0.55A@9V ⏹ 0.1A@48V ⏹0.4A@12V●DC Terminal Block1.2.10 Digital I/O,Relay,Console Connector and Pin Definition● 2 DI/ 1DO●DI: Wet●DO: Wet●DIO Design Specification●DIO 2-IN/1-OUT of TB10 Female with relay and comsole port.●Digital Input Wiring●Digital Output WiringRelay output with 0.5A @30VDCRelay outputThere is a very simple application for remote notice that uses relay and lampas below.1. Normal2. Warning●Console cable pin definition●DIO Terminal Block1.2.11 System LED1.2.12 Wireless (3G/GPRS or Wifi)● 1 x Mini card socket 1 (supports USB interface) with 1 x SIM Card Socket 1 by inside ●Support WiFi or 3G/GPRS21.2.13 Reset Button ● 1 x Reset button1.2.14 Operation Temperature●-40℃ ~ +70℃ (-40 ºF ~ +158ºF)1.2.15 Storage Temperature●-45℃ ~ +85℃ (-49 ºF ~ +185ºF)1.2.16 Humidity●10% ~ 95% (non-condensation)1.2.17 Weight●1kg1.2.18 Dimensions●31mm(W)x100mm(D)x125mm(H)1.2.19 System I/O Outlet● 2 x 9-pin D-Sub male connectors, COM1~COM2 ● 1 x Console Port● 2 x 10/100Mbps Ethernets with magnetic isolation protection● 1 x USB 2.0 with power distribution control and over current protection ● 1 x DIO Port (2-In/1-Out) with Wet contacts ● DC Powers Input with terminal block ●Relay outNoteAll specifications and images are subject to change without notice.1.3 Jumper setting 1.3.1 JP11.3.2 JP31.4 DimensionsThe following diagrams show you dimensions and outlines of the IFB1221.5 I/O OutletsThe following figures show you I/O outlets on front view and bottom view of the IFB122.●Front View●Top View●Bottom View1.6 Packing ListThe package bundled with your IFB122 should contain the following items: ●IFB122 System Unit x 1●Din-rail Kit x 1●Power terminal block x 1●DIO terminal block x 1●Console cable x 1IFB122 U ser’s ManualCHAPTER 2HARDWARE INSTALLATION 2.1 Installing Din-rail MountingThe IFB122 provides Din-rail Mount that customers can install as below:Prepare DIN Mount assembling components (screws and bracket) ready.2.2 Installing Wall Mounting (Opitonal)The IFB122 provides Wall Mounting that customers can install as below:Prepare Wall Mount assembling components (screws and bracket) ready.Assembly the bracket to the system, and fasten screws tight.IFB122 U ser’s ManualThis page is intentionally left blank.。

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ContentsI Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket Switching1I.1Introduction to EHW and EFH (1)I.2Packet switching (3)I.3Solutions for open issues (4)I.4Evolution scheme (7)I.4.1Genetic coding (7)I.4.2Inference scheme (9)I.4.3Fitness function (9)I.5Simulation (10)I.5.1Simulation results (11)I.5.2Tunability of EFH (12)I.6Hardware implementation (14)I.7Conclusions (18)Bibliography (21)Appendix:Copyright (25)Index25 Author Index25iList of FiguresI.1Multiplexer scheme (5)I.2Adaptation framework for EFH (6)I.3Membership functions for c1and c2 (8)I.4Membership functions for T and F (8)I.5Two classes of cellﬂows (11)I.6Cell delay for class1and class2in scenario1 (12)I.7Cell loss for class1and class2in scenario1 (13)I.8Cell delay for class1and class2in scenario2 (13)I.9Cell loss for class1and class2in scenario2 (14)I.10Cell delay for scenario1 (15)I.11Cell loss for scenario1 (15)I.12Cell delay for scenario2 (16)I.13Cell loss for scenario2 (16)I.14Block architecture of RFIC (19)I.15The hardware architecture of OAM (19)iiiList of TablesI.1A25-rule fuzzy system for ATM cell scheduling (9)I.2FIM content in PB<1,1> (18)vList of AlgorithmsviiChapter IEvolvable Fuzzy Hardwarefor Real-time Embedded Control in Packet SwitchingJu Hui Li I.1,Meng Hiot Lim I.2and Qi Cao I.3In this chapter,we describe a scheme to realize an evolvable fuzzy hardware(EFH)for real-time packet switching problem.The common challenges of evolvable hardware (EHW)implementation are issues pertaining to online adaptation,scalability and termination of evolution[1].The proposed EFH addresses these issues eﬀectively.A very interesting advantage of the proposed EFH is that the system performance can be tuned intuitively through parametric adjustment of theﬁtness function.This advantage gives the EFH system a very special property that conventional schedul-ing methods cannot fulﬁll easily.For the hardware implementation of the EFH, real-time fuzzy inference with high-speed context switching capability is necessary. We address this aspect through implementation based on a context independent reconﬁgurable fuzzy inference chip(RFIC).I.1Introduction to EHW and EFHEvolvable hardware(EHW)is a new type of hardware whose architecture can be evolved to suit the operating environment.In recent years,it has been attractingI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket SwitchingI.2.PACKET SWITCHINGI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket SwitchingI.3.SOLUTIONS FOR OPEN ISSUESI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket SwitchingI.4.EVOLUTION SCHEMEI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket SwitchingI.4.EVOLUTION SCHEMES Lc2F F T S F TF T T L T TT T TI.4.2Inference schemeEach entry in Table I.1can be interpreted as a statement of the form”if antecedent1 and antecedent2then conclusion”.The antecedent#represents the fuzzy conditions for c1or c2,characterized over the term set{V S,S,M,L,V L}.The conclusion can be T or F.The degree ofﬁring for each fuzzy rule is taken as the minimum of the degrees of matching between the inputs c1and c2and the antecedents.The aggregation is carried out by averaging the fuzzy conclusions derived from all the rules.Although we have shown a25-rule system,for this evolvable system,the number of the fuzzy rules can vary between0and25.In order to manage the evolution time and reduce the search space,we canﬁx the size of the rule set to be less than25 as in[29],so that the evolution time can be managed.This is because the search space for a reduced rule set is more manageable and hence the evolution eﬃciency can be signiﬁcantly improved.I.4.3Fitness functionAccording to the speciﬁcations of the problem,the capacity of the output channel is ﬁxed.This implies that no further adjustment on the output capacity can be made to cater forﬂuctuations in demand.If the bandwidth is not big enough to meet the demand of the two cellﬂows,servicing class1cell would meanﬁlling up the class2buﬀer and eventually resulting in cell loss for class2.Hence for a speciﬁed requirement on the level of cell delay for class1,a certain expected level of class2cell loss is inevitable.In other words,the class2cell loss is constrained by the desired level of class1cell delay that the system is trying to achieve.I.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket Switchingτ×τi=1m(i)(I.2)DelayF actor=ρ×υ(I.3) In Eq.I.2,m(i)is the waiting time of the i th cell in TB1before being sent out.τis a variable denoting the number of class1cell units in TB1sent during evaluation.τi=1m(i)is the sum of the cell delay of the cell units in TB1.In Eq.I.3,ρisa constant corresponding to the time required to send a cell through the output channel.The value ofρdepends on the bandwidth capacity of the output channel. The symbolυdenotes the size of TB#.With Eq.I.3,a reference value for the possible delay of class1cell units can be determined.I.5SimulationIn order to demonstrate the viability of the EFH scheme,we carried out simulations of EFH in cell scheduling on two diﬀerent scenarios.In the simulation,we assume the capacity of the output channel(OUT)and the input channels to be155.52MHz. The two cellﬂows are as shown in Figure I.5.For scenario1,class1is the CBR cellﬂow with cell bit rate of155.52MHz.class2 is VBR cellﬂow,also with a cell bit rate of155.52MHz.The diﬀerence is that the VBR speciﬁed has a2ms ON time period and a2ms OFF time period.This scenario is a very extreme case used to test the system’s controllability.In order to simulate the system performance on a more realistic cellﬂow,we can adopt scenario2.For scenario2,class1refers to CBR cellﬂow with a cell bit rate of100MHz.class2is VBR cellﬂow with unknown random cell bit rate.The minimum cell bit rate for VBR is55.52MHz while the maximum is155.52MHz.In these two scenarios,since the sum of the CBR and VBR cell rate is larger than the OUT channel’s capacity,I.5.SIMULATION(I.4)[T i(t)]γI.5.1Simulation resultsFor the simulation,the size of BUF1and BUF2is100cells,and the size of TB1and TB2is300cells.In theﬁtness function,λis0.35.All the simulations are carried out by using a C++program.The setting for the parameters of the evolutionary algorithm is as follows:•population size=10;•elite pool size=2;•crossover probability=0.6;•mutation probability=0.05;•number of generation=9;•number of evolutionary cycle=2.We simulated each scheduling scheme for cellﬂows lasting2seconds.Figure I.6 and I.7are the simulation results of FIFO,DWPS and EFH schemes on scenario1. Figure I.8and I.9are simulation results for FIFO,DWPS and EFH schemes on scenario2.The simulation results demonstrate the viability of the evolution schemeI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket SwitchingI.5.SIMULATIONI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket SwitchingI.6.HARDW ARE IMPLEMENTATIONI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket SwitchingI.6.HARDW ARE IMPLEMENTATIONI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket Switching2blocks and AveData0,111111,111110,110111,110110,101111,10111...0,110111,11011...0,001111,00111I.7ConclusionsThere are several challenges to the application of evolvable hardware for solving time critical problems.We highlighted three issues,namely online adaptation,scalabil-ity as well as termination of evolution.To realize EHW capable of intrinsic online evolution,these issues have to be considered.In this chapter,we proposed the EFH scheme,a form of EHW whereby the fuzzy inference scheme is carried out in hardware to achieve real-time operation.The scheme allows for updating of online context and domain rules and further incorporating mechanisms to evolve a context appropriate for the application scenario.In order to demonstrate the viability of our proposed EFH,we simulated the control performance of the EFH in cell schedul-ing and compared the results with some traditional scheduling methods.From the simulation results,it can be seen that the EFH is capable of dealing with changing cellﬂows much better than the traditional methods.Another signiﬁcant advantage of the EFH is tunability.This was also analyzed based on the simulation results.18I.7.CONCLUSIONSI.Evolvable Fuzzy Hardware for Real-time Embedded Control inPacket SwitchingBibliography[1]X.Yao and T.Higuchi,“Promises and Challenges of Evolvable Hardware”,IEEETrans on Syst.,Man and Cybern.,Part C,Applications and Reviews,vol.29, no.1,pp:87–97,Feb.1999.[2]W.X.Liu,M.Murakawa and T.Higuchi,“ATM Cell Scheduling by FunctionLevel Evolvable Hardware”,LNCS1259(ICES1996):pp.180-192[3]W.X.Liu,M.Murakawa and T.Higuchi,“Evolvable Hardware for On-line Adap-tive Traﬀc Control in ATM Networks”,Genetic Programming1997,Proc.of the Second Annual Conference,pp.504–509,Morgan Kaufmann Publishers,1997.[4]T.G.W.Gordon and P.J.Bentley,“On Evolvable Hardware”,In Ovaska,S.andSztandera,L.(Ed.)Soft Computing in Industrial Electronics.Physica-Verlag, Heidelberg,Germany,2002,pp.279-323[5]H.D.Garis,“Evolvable Hardware:Principles and Practice”,/∼degaris/papers/CACM-E-Hard.html[6]M.Iwata,I.Kajitani,H.Yamada,H.Iba and T.Higuchi,“A pattern recognitionsystem using evolvable hardware”,in Proc.Int.Conf.Parallel Probl.Solving Nature(PPSN’96).[7]E.Sanchez,Towards evolvable hardware:the evolutionary engineering approach,Berlin;New York:Springer,c1996.[8]K.C.Tan,C.M.Chew,K.K.Tan,L.F Wang and Y.J.Chen,“Autonomous RobotNavigation via Intrinsic Evolution”,Proc.of the2002Congress on Evolutionary Computation,2002(CEC’02).vol.2,2002pp.1272–1277[9]ngeheine,K.Meier and J.Schemmel,“Intrinsic Evolution of Quasi DCSolutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip”.Proc.NASA/DoD Conference on Evolvable Hardware,2002,pp.75–84 [10]F.H.Bennett,J.R.Koza,M.A.Keane,J.Yu,W.Mydlowee and O.Stiﬀelman,“Evolution by Means of Genetic Programming of Analog Circuits that Perform Digital Functions”,Proc.of the Genetic and Evolutionary Computation Confer-ence,July13-17,1999,Orlando,Florida.21BIBLIOGRAPHYBIBLIOGRAPHYAppendix:Copyright25。