VHDL的乘法器设计——数字电路课程设计

数字电路课程设计题目乘法器设计班级实验二班学号姓名时间第十三、十四周地点科A-304指导陈学英唐青【摘要】：用FPGA设计完成基于半加器、全加器和保留进位思想设计的4BIT四级流水乘法器，用modelsim仿真其结果。

【目录】：第一章、实验任务及原理第二章、设计思路方法及方案第三章、FPGA模块程序设计与仿真第四章、结束语【正文】【第一章】：实验任务及原理本实验只要求编写乘法器的硬件代码，并用Modelsim进行仿真测试。

设计乘法器，两个输入都是4BIT，对所有输入相乘都得到正确结果，乘法器采用四级流水设计，以增加处理速度。

用modelsim仿真时，要求用时钟上升沿方式遍历所有输入，检查输出结果是否正确。

原理用到流水，进位保留思想。

【第二章】：设计思路及方案算法结构（无符号）由上图可见，乘法的运算最终是加法的运算，两个4BIT输入，输出为7BIT。

模块一、半加器：单比特输入相加，模块二、全加器：由两个半加器组成，有一个进位输入，模块三、进位保留加法器：最终程序结构图流水设计的原理：在前向割集上加入四级流水图一图二如上图所示方框代表触发器，五边形代表组合逻辑块，假设图一中逻辑块输入输出延时为Ta，图二将逻辑块切割成两块，延时分别为T1，T2，且Ta=T1+T2，并在两逻辑块之间加触发器，两个逻辑块工作频率都可以达到clk频率，故工作速度增加一倍，虽然时延增加了，但资源优化了许多。

【第三章】：FPGA程序模块及仿真半加器的程序模块：entity half_adder isport(a,b:in std_logic;s,cout:out std_logic);end half_adder;architecture Behavioral of half_adder isbegins<=a xor b;cout<=a and b;end Behavioral;全加器的程序模块：调用半加器，采用顶层设计entity full_adder isport(a,b,cin:in std_logic;s,cout:out std_logic);end full_adder;architecture Behavioral of full_adder iscomponent half_adderport(a,b:in std_logic;cout,s:out std_logic);end component;signal h1s,h1cout,h2cout:std_logic;beginu1:half_adder port map(a,b,h1cout,h1s);u2:half_adder port map(cin,h1s,h2cout,s);cout<=h1cout or h2cout;end Behavioral;乘法器的程序模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;----Uncomment the following library declaration if instantiating----any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity mm isport(a:in std_logic_vector(3downto0);b:in std_logic_vector(3downto0);clk:in std_logic;reset:in std_logic;psum:out std_logic_vector(7downto0));end mm;architecture Behavioral of mm iscomponent half_adderport(a,b:in std_logic;s,cout:out std_logic);end component;component full_adderport(a,b,cin:in std_logic;s,cout:out std_logic);end component;signal x:std_logic_vector(1to16);-----原理图中从左到右------------原理图中，触发器从左到右，共四层，依次定义信号signal d1:std_logic_vector(1to16);signal d2:std_logic_vector(1to13);signal d3:std_logic_vector(1to10);signal d4:std_logic_vector(1to9);-----------原理图中，加法器从左到右，依次定义加法器输出的进位信号signal c1:std_logic_vector(1to3);signal c2:std_logic_vector(1to3);signal c3:std_logic_vector(1to3);signal c4:std_logic;signal c5:std_logic;----------原理图中，加法器从左到右，依次定义加法器输出的和信号signal s1:std_logic_vector(1to3);signal s2:std_logic_vector(1to3);signal s3:std_logic_vector(1to3);signal s4:std_logic_vector(1to2);signal s5:std_logic;--------第四层加法器间的信号signal e:std_logic;beginx(1)<=a(3)and b(3);x(2)<=a(3)and b(2);x(3)<=a(2)and b(3);x(4)<=a(3)and b(1);x(5)<=a(2)and b(2);x(6)<=a(1)and b(3);x(7)<=a(3)and b(0);x(8)<=a(2)and b(1);x(9)<=a(1)and b(2);x(10)<=a(0)and b(3);x(11)<=a(2)and b(0);x(12)<=a(1)and b(1);x(13)<=a(0)and b(2);x(14)<=a(1)and b(0);x(15)<=a(0)and b(1);x(16)<=a(0)and b(0);-------------------------------------all dff process(clk,reset)beginif reset='0'thend1<="0000000000000000";d2<="0000000000000";d3<="0000000000";d4<="000000000";elsif clk'event and clk='1'then --------------------------------------first d1(1)<=x(1);d1(2)<=x(2);d1(3)<=x(3);d1(4)<=x(4);d1(5)<=x(5);d1(6)<=x(6);d1(7)<=c1(1);d1(8)<=s1(1);d1(9)<=x(9);d1(10)<=x(10);d1(11)<=c1(2);d1(12)<=s1(2);d1(13)<=x(13);d1(14)<=c1(3);d1(15)<=s1(3);d1(16)<=x(16);--------------------------------------second d2(1)<=d1(1);d2(2)<=d1(2);d2(3)<=d1(3);d2(4)<=c2(1);d2(5)<=s2(1);d2(6)<=d1(6);d2(7)<=c2(2);d2(8)<=s2(2);d2(9)<=d1(10);d2(10)<=c2(3);d2(11)<=s2(3);d2(12)<=d1(15);d2(13)<=d1(16);--------------------------------------third d3(1)<=d2(1);d3(2)<=c3(1);d3(3)<=s3(1);d3(4)<=c3(2);d3(5)<=s3(2);d3(6)<=c3(3);d3(7)<=s3(3);d3(8)<=d2(11);d3(9)<=d2(12);d3(10)<=d2(13);-------------------------------------fourthd4(1)<=d3(1);d4(2)<=d3(2);d4(3)<=c4;d4(4)<=s4(1);d4(5)<=s4(2);d4(6)<=d3(7);d4(7)<=d3(8);d4(8)<=d3(9);d4(9)<=d3(10);end if;end process;----------共五层，每一层都是从左到右，依次调用映射。

------------------------------firstu1:half_adder port map(a=>x(7),b=>x(8),cout=>c1(1),s=>s1(1)); u2:half_adder port map(a=>x(11),b=>x(12),cout=>c1(2),s=>s1(2)); u3:half_adder port map(a=>x(14),b=>x(15),cout=>c1(3),s=>s1(3)); ------------------------------secondu4:full_adder port map(a=>d1(4),b=>d1(5),cin=>d1(7),cout=>c2(1),s=>s2(1));u5:full_adder port map(a=>d1(8),b=>d1(9),cin=>d1(11),cout=>c2(2),s=>s2(2));u6:full_adder port map(a=>d1(12),b=>d1(13),cin=>d1(14),cout=>c2(3),s=>s2(3));------------------------------thirdu7:full_adder port map(a=>d2(2),b=>d2(3),cin=>d2(4),cout=>c3(1),s=>s3(1));u8:full_adder port map(a=>d2(5),b=>d2(6),cin=>d2(7),cout=>c3(2),s=>s3(2));u9:full_adder port map(a=>d2(8),b=>d2(9),cin=>d2(10),cout=>c3(3),s=>s3(3));------------------------------fourthu10:half_adder port map(a=>d3(5),b=>d3(6),cout=>e,s=>s4(2));u11:full_adder port map(a=>d3(3),b=>d3(4),cin=>e,cout=>c4,s=>s4(1));------------------------------lastu12:full_adder port map(a=>d4(1),b=>d4(2),cin=>d4(3),cout=>c5,s=>s5);------------------------------overpsum(7)<=c5;psum(6)<=s5;psum(5)<=d4(4);psum(4)<=d4(5);psum(3)<=d4(6);psum(2)<=d4(7);psum(1)<=d4(8);psum(0)<=d4(9);end Behavioral;仿真模块：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY testnew ISEND testnew;ARCHITECTURE behavior OF testnew IS--Component Declaration for the Unit Under Test(UUT) COMPONENT mmPORT(a:IN std_logic_vector(3downto0);b:IN std_logic_vector(3downto0);clk:IN std_logic;reset:IN std_logic;psum:OUT std_logic_vector(7downto0));END COMPONENT;--Inputssignal a:std_logic_vector(3downto0):=(others=>'0');signal b:std_logic_vector(3downto0):=(others=>'0');signal clk:std_logic:='0';signal reset:std_logic:='0';--Outputssignal psum:std_logic_vector(7downto0);--Clock period definitionssignal s0,s1,s2,s3:std_logic_vector(7downto0);signal test:std_logic;BEGIN--Instantiate the Unit Under Test(UUT)uut:mm PORT MAP(a=>a,b=>b,clk=>clk,reset=>reset,psum=>psum);--Clock process definitionsclk_process:processbeginclk<='0';wait for1us;clk<='1';wait for1us;end process;reset_process:processbeginreset<='0';wait for10ns;reset<='1';wait;end process;--时钟上升沿计数遍历所有可能输入值stim_proc:process(clk,reset)beginif reset='0'thena<="0000";b<="0000";elsif clk'event and clk='1'thenif a<"1111"then a<=a+'1';elsif a>"1110"thena<=(others=>'0');if b<"1111"then b<=b+'1';elsif b>"1110"thenb<=(others=>'0');end if;end if;-----------------------延迟四拍，使之与输出结果同步s0<=a*b;s1<=s0;s2<=s1;s3<=s2;---------信号test检验结果的正确与否，若正确，输出1，否则为0 if s3=psum then test<='1';else test<='0';end if;end if;end process;END;仿真结果：上图检测信号（test）一直是高电平；下图由开始部分看出，输出结果与输入延时了四拍；由此可见仿真结果是正确的。