硅基光电子技术在大数据时代的机遇与挑战(周治平)

Silicon Photonics: Challenge and Opportunity in Big Data Era周治平.北京大学Zhiping ZhouPeking University, Chinazjzhou@CIOEC, Sept. 2, 2015Shenzhen, ChinaSilicon Photonics Edited by Zhiping ZhouOutline •Interconnect and the emerging silicon photonics•Current silicon photonics interconnect •Difficulties and challenges •ConclusionsApplications push the growth of data centersSource: Intel IDF14Scalability: both quantity and continuous improvement of device performanceToday’s interconnects in data centersRack to rack: optical (VCSEL-based)In-rack: imminent transformation to optical solutionSource: M Paniccia, Presentation at Purdue University (2007).Today’s racks in data centersCopper interconnect can no longer provide the desired speed, must turn to optical interconnects.•High speed •Low energy consumption •Easy to useIn-rack: copper interconnectdifficult for >20 Gbps/wireTrend: 25G/50G/100G or higherAdvantages of optical solutionSpeed25 Gbps/channel commercialized, 50~70 Gbps/channelpossible in the futureScalability: multiplexing•Space division multiplexing: multiple cores or fibers Up to 64 fibers (MXC) in an AOC, aggregatedcapacity of 1 Tbps•Wavelength division multiplexing:Four wavelengths CWDM or more in the future Speed per channel, SDM and WDM are all scalable. Capacity can be readily upgraded.Optical interconnect: active optical cable (AOC)Easy-to-use optical solutionWire containing optical transceivers(WDM optional)Channel 10G, 25G or higherMultimode fibers / single mode fibers Change to AOCWhat is Silicon Photonics?•Chip size optical solutions with emphasize oninteraction between photons and electrons •Applications in interconnections, communications, and other areas such as internet of things, nonlinear optics, Advantages:•Compatible with CMOS fabrication processing: low cost, massive production•Single-mode & SMF: long transmission range, high speed The higher the capacity and production demand, the more competent is silicon photonics than VCSEL.Anticipation: pooling structureNew architecture enabled by higher interconnection capacitySource: Intel IDF14Outline •Interconnect and the emerging silicon photonics•Current silicon photonics interconnect •Difficulties and challenges •ConclusionsModulator1. An ultralow power athermal silicon modulator, Nature Communications, 20142. 50-Gb/s Silicon Mach-Zehnder Interferometer-based Optical Modulator with only 1.3 Vpp Driving Voltages, 2014 IEEE EPTCResonator-based 25 GbpsER=6 dBIL=1 dBVpp=0.5 V0.79 fJ/bit MIT MZ modulator50 Gbps ER=4.44 dB IL=4.2 dB L=4 mm Vpp=1.3 V 676 fJ/bitIMECoupler1.Bridging the gap between optical fibers and silicon photonic integrated circuits, Optics Express, 20142.High Coupling Efficiency Etched Facet Tapers in Silicon,CLEO, 2012Grating coupler IL: 0.62 dB (TE)1dB BW:40nm University of StuttgartInverse taper couplerIL: 0.7 dBDeepTrenchCornell UniversityIntel Creates World's First End-to-End Silicon Photonics link 50G in 2010 and 100G in 2013Single-die 25Gbps multi-channel WDM optical transceiverSummary for current developmentAcademia: mainly focuses on device level research, less on system level researchIndustry: some systems already commercialized.There is also potential to do better.Relatively mature device designFew accessible packaging platforms, packaging techniques to be further developed and refinedDevice performance and fabrication technologiesfall behind leading countriesDifficulties in ChinaWorldwideOutline •Interconnect and the emerging silicon photonics•Current silicon photonics interconnect •Difficulties and challenges •ConclusionsDifficulties and challengesEnergy consumptionOn-chip light sourceChallenge 1: Energy consumption Lowering the energy consumption in silicon photonic devices and systems, 2015.Proposes methods for device-leveloptical link energy reduction andinsights into on-chip lasersReviews current optical linkperformance in terms of energy andinsertion lossFeatured paperChallenge 1: Energy consumptionVery challenging goalRequires concerted research effortsInterconnect capacity demand will continue to grow in the future, and energy (per bit) needs to be reduced to keep the total consumption acceptable.Device Requirements for Optical Interconnects to Silicon Chips, Proceedings of IEEE, 2009•Short-term energy cost goal:——no more than copper interconnects•Link energy:1 pJ/bitincluding electrical circuitsNowOptical interconnect energy goalChallenge 1: Energy consumptionSignificant energy reduction, convenient when no metal patterns in air trench area•Standard process in some foundries•Can be further processed to have undercut•Significant thermal tuning efficiency improvement of 6x~20x, highest reported data: 58x (with undercut)Total energy consumption (calculated as 10x)Vertical: ~89 fJ/bit @ 25 GbpsLateral: ~160 fJ/bit @ 25 GbpsSubmilliwatt thermo-optic switches using freestanding silicon-on-insulator strip waveguides, OE, 2010Solution 1: air trench techniqueCurrent option: III-V-based laser on siliconFlip-chip Wafer bonding Epitaxial growth Challenge 2: on-chip light sourceSi does not lase (indirect bandgap), other CMOS compatible materials are in early stage of research.PHOTONICS ResearchPhotonics Research (PR) is an English ‐language, peer ‐reviewed open ‐accessjournal serving as an international platformfor optics researchers to sharetheoretical and applied research progress in optics andphotonics. PR is co ‐published by ChineseLaser Press (CLP) and OSA.Submit your research toEditor ‐in ‐Chief: Prof. Zhiping (James) Zhou, Peking UniversityDeputy Editor: Michael A. Fiddy, University of North Carolina, CharlotteThank you for your attention。