精品课件-微机原理及应用实践(英文版)陈志平-Chapter2

Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
Chapter２ MICROPROCESSOR-BASED SYSTEMS
2.1 Introduction 2.2 Architecture of 8086 Microprocessor 2.3 8086 CPU Registers 2.4 8086 Pins and Functions 2.5 8086 Memory Organization 2.6 8086 Memory and I/O Operation Cycles
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Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
CX register (Count) 计数寄存器 Destination Index (DI) 目标变址寄存器 Direction Flag (DF) 方向标志位 demultiplex 信号分离 DX register (Data) 数据寄存器 even address 偶地址 Execution Unit(EU) 执行单元 general-purpose registers 通用寄存器 Instruction Pointer (IP) 指令指针寄存器 instruction queue 指令队列 Interrupt enable Flag (IF) 中断标志位
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Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
KEY TERMS
address generation adder 地址加法器 Arithmetic [] Logical Unit (ALU) 算术逻辑单元 Auxiliary [] Flag (AF) 辅助进位标志位 AX register (Accumulator) 累加器 Bank High Enable ( BHE ) 总线高位有效信号 Base Pointer (BP) 基址指针 bus control logic 总线控制电路 Bus Interface Unit(BIU) 总线接口单元 BX register (Base) 基址寄存器 Carry Flag (CF) 进位标志位 Code Segment (CS) 代码段寄存器
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Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
logical address 逻辑地址 maximum mode (max-mode) 最大模式 minimum mode (min-mode) 最小模式 odd address 奇地址 offset address 偏移地址 Overflow Flag (OF) 溢出标志位 Parity Flag (PF) 奇偶校验标志位 physical address 物理地址 status and control flags 状态和控制标志 segment base 段基址 segment registers 段寄存器 Sign Flag (SF) 符号标志位 Source Index (SI) 源变址寄存器
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Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
Stack Pointer (SP) 堆栈指针 temporary-operand [] registers the bottom of the stack 栈底 the Data Segment (DS) 数据段寄存器 the Extra Segment (ES) 扩展段寄存器 the Flags Register (FR) 标志寄存器 the Stack Segment (SS) 堆栈段寄存器 the top of the stack 栈顶 Trap Flag (TF) 单步标志位 Zero Flag (ZF) 零标志位
In this chapter, we will present the features of the 80x86 microprocessor family and mainly discuss the architecture of 8086 microprocessor. Pin function, mode of operation, clock generation and bus timing etc of 8086 microprocessor will be covered, leaving the hardware and software details to the upcoming chapters. From this chapter you will learn that the 80x86 is a machine with many possibilities.
暂存寄存器
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ARCHITECTURE
2.1 Introduction Since the 80x86 microprocessor family has a typical basic structure, its arrival on the computer scene has quickly taken the lead in the personal computer market. In other words, the 80x86 processor is used everywhere, from dedicated control systems to fast network file servers. Today, the Pentium offers compatibility with all previous 80x86 machines, with many new architectural improvements.
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Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
The BIU is the 8086’s connection to the outside world. By interface, we mean the path by which it connects to external devices, like memory or I/O devices. The BIU is responsible for performing all external bus operations. 1Its functions include address generation, instruction fetching, instruction queuing, reading and writing of data operand for memory, inputting or outputting data for input/output peripherals, and bus control logic. These information transfers take place over the system bus.
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Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
OBJECTIVES Upon finishing this chapter, you will learn: Architecture of 8086 CPU(the operation of the
execution unit and the bus interface unit) 8086 CPU Registers(the internal registers array) Pins and Functions of 8086/8088 CPU Memory Segmentation and address organization Memory and I/O operation cycles
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Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
Intel 8086 is a 16 bit microprocessor, and it has 16 bit data bus and 20 bit address bus. However, the different microprocessor has different internal architecture and different features, but the internal architecture of Intel 8088 microprocessor is same as 8086 microprocessor except 8088 microprocessor has 8 bit data bus. They both employ parallel processing—that is, they are implemented with several simultaneously operating processing units. They can directly address 1 megabytes of memory. The memory used by 8086 microprocessor is bytes and each byte can be addressed uniquely with 20 bit addresses.
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Chapter 2 8086 MICROPROCESSOR ARCHITECTURE
2.2 Architecture of 8086 Microprocessor Figure 2.1 illustrates the internal architecture of the 8086 processor. It contains two processing units: the Bus Interface Unit (BIU) and the Execution Unit (EU). Each unit has dedicated functions and both operate at the same time. In essence, this parallel processing effectively makes the fetch, decoding and execution of instructions independent on 8088/8086 microprocessor systems. BIU and EU are shown on both sides of the dotted line in Figure 2.1. There will be a brief introduction to the two parts below.