Lattice fpga工具约束参数详解

1-100
1-99
Routing Resource Optimization Routing Delay Reduction Passes PLC Input Lim6 0-6 Off, Low, Medium, High
PLC Input Neighbor Size
Command Line Options
d Timing Performance Listed) July 20, 2006 Ver 1.0 Analysis
Specifies the global design frequency (in MHz). Improve Fmax.
Specifies the Area mode. For Precision: Specifies the encoding style to use with the design. For Synplify: Enables/disables the FSM Compiler and controls the use of FSM synthesis for state machines. When this is set to True (default), the FSM Compiler automatically recognizes and optimizes state machines in the design. It can improve area optimization if turn on, •Binary - Most area efficient. Will use a minimum number of registers to implement the state vector resulting in the smallest overall area. Binary is generally not the optimal encoding for FPGAs because of the abundance of registers these devices offer. Precision will use Binary for small FSMs in FPGAs. Turn on when the number of states is less than 5. •One-hot - Provides the fastest clock to out timing. One-hot FSM encoding uses a separate register for each bit of the state vector. The state register is connected directly to the FSM outputs providing the fastest clock to out timing. Onehot FSMs generally result in the fastest performance and are the most common encoding selected by Precision's Auto selection. Turn on when the number of states is > 5 and <= 16. •Two-hot - Offers a compromise between the area advantages of binary and the performance advantages of one-hot. Two hot FSM uses 2 to True, output bits driven to a will not one to define the decoding. For If it is set if you have an If this property is set register Synplify or Precision logical add I/O buffers to your design. example, to False (default), the synthesis tool will insert I/O buffers to your design. For hierarchical and mixed design, Disable_IO_Insertion should befanout i.e, the synthesis. When the specified fanout limit is achieved, logic will be duplicated and Fmax may Controls false, during I/O buffers should be added. be improved. Large fanouts may cause long delay and congestion, less resource. Setting this property to True causes the advanced retiming algorithms to be run. The default is False. Setting this property to True transforms Set/Reset on DFFs to Latches. The default is True.
1,2,…,5
Routing Passes Disable Timing Driven Routing Options Placement Iterations
1,2,…,30
True/False 0,1
0-99
Placement Start Point Placement Save Best Run
True/False Auto (default), Binary, One Hot, Two Hot, Random, or Gray for Precision. Treu/False for Synplify
Condition
the Area property is set to False.
Synthesis, Map, PAR Properties (Only Those Impact on Area and Timing Performance Listed) July 20, 2006 V Value Synthesize VHDL/Verilog File Property Frequency Area FSM Encoding
Sets the relative density (of available PFUs) at which the Programmable Functional Units (PFUs) within a device are to be packed. The mapper translates the factor into number of PFUs, that is, the number is the percentage of slices to pack to. For example, 90 means pack to 90% of slices on the chip (quite spread). 10% means pack to 10% of slices (quite dense)will not pack components from different top level modules into the same PFU. This affords PLACE & ROUTE MAP better placement choices through improved logic grouping. This Text property is made available after an initial design run. It is used to move registers across combinational logic to balance timing according to the constraints of tSU (INPUT_SETUP), tCO (CLOCK_TO_OUT), and fMAX (FREQUENCY). Retiming supports six timing preferences: INPUT_SETUP, CLOCK_TO_OUT, FREQUENCY, MULTICYCLE, MAXDELAY, and PERIOD. Other preferences have no effect on retiming. This property can take two options: EFFORT: Retiming Level of Effort option. Takes integer values 1-6, with 1 being the least effort and 6 the most. Default value for all devices is 4.High effort value may not always provide best results, as it may incur higher run time and register count. DETOUR: Retimingtiming-driven logic collapsing andDetour. Takesto further optimize the critical paths.least severity Allows you to apply estimation on severity of Routing optimization integer values 1-6, with 1 being the Timing Driven Mapping reads the preference file and calculates the slacks for all constrained paths. The mapping optimizes the critical paths based on the slack distributions. Specifies the effort level of the design from 1 (simplest designs) to 5 (most complex designs). The level is not an absolute; it shows instead relative effort. After you use PLACE & ROUTE for a while, you will be better able to estimate whether a design is simple or complex. If you place and route a simple design at a complex level, the design will be placed and routed properly, but the process will take more time than placing and routing at a simpler level. If you place and route a complex design at a simple level, the design may not route to completion or may route less completely (or with worse delay characteristics) than at a more complex level.