verilog 4位比较器

具体功能是：A和B进行比较，假若A>B，则AD输出高电平，A

Verilog四位比较器具体程序如下：

module bjq_qq;

reg[3:0] A,B;

wire AD;

wire DY;

parameter Dely=50;

bjq shit(A,B,AD,DY);

initial begin

A=4'd1;B=4'd5;

#Dely A=4'd5;B=4'd2;

#Dely A=4'd3;B=4'd6;

#Dely A=4'd10;B=4'd3;

#Dely A=4'd1;B=4'd1;

#Dely A=4'd7;B=4'd9;

#Dely A=4'd5;B=4'd4;

#Dely A=4'd6;B=4'd5;

#Dely A=4'd15;B=4'd3;

#Dely A=4'd12;B=4'd5;

#Dely A=4'd7;B=4'd1;

#Dely A=4'd4;B=4'd7;

#Dely A=4'd5;B=4'd2;

#Dely A=4'd7;B=4'd12;

#Dely A=4'd1;B=4'd5;

#Dely A=4'd7;B=4'd1;

#Dely A=4'd14;B=4'd0;

#Dely A=4'd6;B=4'd5;

#Dely A=4'd7;B=4'd3;

#Dely A=4'd3;B=4'd9;

#Dely A=4'd11;B=4'd1;

#Dely A=4'd6;B=4'd9;

#Dely A=4'd6;B=4'd5;

#Dely A=4'd7;B=4'd7;

#Dely A=4'd1;B=4'd5;

#Dely A=4'd7;B=4'd1;

#Dely $finish;

end

endmodule

module bjq(a,b,ad,dy);

input[3:0] a,b;

output ad;

output dy;

assign ad=(a>b);

assign dy=(a==b); endmodule

虚拟波形图为：