msp430AD采样并串口发送

#include

void clk_init()

{

P5SEL |= BIT4+BIT5; // Select XT1

UCSCTL6 &= ~(XT1OFF); // XT1 On

UCSCTL6 |= XCAP_3; // Internal load cap

UCSCTL0 = 0x0000;

UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive strength

UCSCTL3 = SELREF_0+FLLREFDIV_1; // Set DCO FLL reference = XT1

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL1 = DCORSEL_3; // Select DCO range 16MHz operation UCSCTL2 =249; // Set DCO Multiplier for 8MHz

// (N + 1) * FLLRef = Fdco

// (249 + 1) * 32768 = 8MHz __bic_SR_register(SCG0); // Enable the FLL control loop

UCSCTL4 |= SELS_0; // ACLK = LFTX1 (by default)

// __delay_cycles(250000);

}

void adc_init()

{

P6SEL |= 0x01; // Enable A/D channel A0

ADC12CTL0 = ADC12ON+ADC12SHT0_12+ADC12MSC; // Turn on ADC12, set sampling time

// set multiple sample conversion ADC12CTL1 = ADC12SHP+ADC12CONSEQ_2+ADC12DIV_0+ADC12SSEL_3; // Use sampling timer, set mode

ADC12MCTL0 |= ADC12INCH_1;

ADC12CTL1 = ADC12SHP+ADC12CONSEQ_2; // Use sampling timer, set mode

ADC12IE = 0x01; // Enable ADC12IFG.0

ADC12CTL0 |= ADC12ENC; // Enable conversions

ADC12CTL0 |= ADC12SC; // Start conversion

}

void uart1()

{

WDTCTL = WDTPW + WDTHOLD; // Stop WDT

P3SEL |= BIT3+BIT4; // P3.3,4 = USCI_A0 TXD/RXD

UCA0CTL1 |= UCSWRST; // **Put state machine in reset**

UCA0CTL1 |= UCSSEL_2; // SMCLK

UCA0BR0 = 9; // 1MHz 115200 (see User's Guide) UCA0BR1 = 0; // 1MHz 115200

UCA0MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0 UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** UCA0IE |= UCRXIE;

}

int main(void)

{

P1DIR |= 0x01;

//clk_init();

uart1();

int he;

adc_init();

__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled

__no_operation(); // For debugger

}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)

#pragma vector=ADC12_VECTOR

__interrupt void ADC12ISR (void)

#elif defined(__GNUC__)

void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12ISR (void)

#else

#error Compiler not supported!

#endif

{

switch(__even_in_range(ADC12IV,34))

{

case 0: break; // Vector 0: No interrupt

case 2: break; // Vector 2: ADC overflow

case 4: break; // Vector 4: ADC timing overflow

case 6: // Vector 6: ADC12IFG0 UCA0TXBUF = ADC12MEM0>>4; // Move results

P1OUT ^= 0x01;

_BIC_SR_IRQ(LPM0_bits);

case 8: break; // Vector 8: ADC12IFG1

case 10: break; // Vector 10: ADC12IFG2

case 12: break; // Vector 12: ADC12IFG3 case 14: break; // Vector 14: ADC12IFG4 case 16: break; // Vector 16: ADC12IFG5 case 18: break; // Vector 18: ADC12IFG6 case 20: break; // Vector 20: ADC12IFG7 case 22: break; // Vector 22: ADC12IFG8 case 24: break; // Vector 24: ADC12IFG9 case 26: break; // Vector 26: ADC12IFG10 case 28: break; // Vector 28: ADC12IFG11 case 30: break; // Vector 30: ADC12IFG12 case 32: break; // Vector 32: ADC12IFG13 case 34: break; // Vector 34: ADC12IFG14 default: break;

}

}