poc报告

POC DesignPurposeThe purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provided for simulation.TaskPOC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral (such as a printer or other output devices).Figure 1 Printer ConnectionFigure 1 shows the connecting of a printer to the system bus through the POC. The communication between POC and the printer is controlled by a “handshake” protocol illustrated in Figure 2.Figure 2 The handshake-timing diagram between POC and the printerThe handshaking process is described as follows: When the printer is ready to receive a character, it holds RDY=1.The POC must then hold a character at PD (parallel data)port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the character has been printed (e.g. 5 or 10ms), then set RDY=1 again when it is ready to receive the next character. (Suppose the printer has only a one character “buffer” register, so that each character must be printed before the next character is sent).In order to ease your design work, the further explanations of the POC operations and some design hints are given as follows:The buffer register BR is used to hold a character that has been sent via the system bus while that the character is being transferred to the printer. The status register SR is used for two control functions: SR7serves as a ready flag for system bus transfers to BR (like the printer RDY signal for transfers from POC to the printer), and SR0 is used to enable or disable interrupt requests from POC. If SR0=1, then POC will interrupt when it is ready to receive a character (i.e., when SR7=1). If SR0=0, then POC will not interrupt. The other bits of SR are not used and empty.The transfer of a character to POC via the system bus proceeds as follows. POC indicates that it is ready by setting SR7.The processor reads SR (by executing a polling or interrupt service routine) and, finding SR7=1, writes a character to BR. The POC clears SR7 when it loads this character into BR to indicate that another character should not be sent for the moment. POC then proceeds to transfer the character in BR to the printer by generating a pulse at TR. The processor, in the meantime, continues to fetch and execute instructions .If it should happen to read SR, it will find SR7=0 and hence will not attempt to send another character to the printer. When the printer is ready to receive another character, POC sets SR7.The transfer cycle can now repeatThe overall connection of the simulated printer and POCDesign description of the simulation connectionclk -- system clock.reset -- input signal that resets the whole system.cs-- enable signal.rw-- input signal of POC that is the control of reading datas from POC to CPU or writing datas from CPU to POCmode -- input signal .when set to ‘0’,represents the mode of polling ;when set to’1’, represents the mode of interrupt.a -- 3 bits address bus.”000” represents the state of idle.”001” represents thestate of transfer data.d -- 8 bits data bus between CPU and POC.pd-- 8 bits data busl between POC and Printer.rdy-- the signal which reprensents the state of printer.tr-- a pulse signal from POC to make the rdy be low-level.irq-- Interrupt signal from POC to CPU.Simulation results and explanation1.The simulation wave of printer moduleExplanation: When the printer is ready to receive a character, it holds RDY=1.The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). Then the printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the character has been printed (e.g. 5 or 10ms), then set RDY=1 again when it is ready to receive the next character.2.The simulation wave of polling mode without printerExplanation: In polling mode, the singal mode=’0’ and The irq signal is always ‘0’ ,rw and a are singals from cpu to poc to control the action of poc.rw=’1’ and A=’000’represents the state of idle.rw=’1’and A=’001’represents the state of transfer data and print. When a pulse signal tr arrive,the data is send to pd from d , After the tr signal we can see that the input rdy signal change to 0.3.The simulation wave of interrupt mode without printerExplanation: In interrupt mode,mode=1 and rw and A are signals from cpu to poc to control the action of poc.rw=’1’ and A=’000’ represents the state of idle.rw=’1’ and A=’001’ represents the state of transfer data and print.after a irq signal ‘1’is send to cpu,a data is send to br from cpu.then a pulse signal tr is send to printer,the data is send to pd from br at the same time , After the tr signal we can see that the input rdy signal change to 0.4.The simulation wave of poc with printer in both modeExplanation:There are two types working mode: In polling mode, the singal mode=’0’ and The irq signal is always ‘0’ ,rw and a are singals from cpu to poc to control the action of poc.rw=’1’and A=’000’represents the state of idle.rw=’1’and A=’001’represents the state of transfer data and print. In interrupt mode,mode=1 and rw and A are signals from cpu to poc to control the action of poc.rw=’1’and A=’000’represents the state of idle.rw=’1’and A=’001’represents the state of transfer data and print.after a irq signal ‘1’is send to cpu,a data is send to br from cpu. Then the data is send to pd from br at the same time.In both mode the POC design meets the requirement of experiment and the results match with theoretical results.Conclusions and DiscussionsIn both polling mode and interrupt mode.The POC design meets the requirement of experiment and the results match with theoretical results.In the simulation,I find it difficult to meet the requirement of experiment strictly in timing simulation. so I use functional simulation to test the circuit and have got the right results.Appendixpoc.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity poc isport(clk,reset,cs,rdy,rw: in std_logic;mode: in std_logic;a:in std_logic_vector(2 downto 0);d:in std_logic_vector(7 downto 0);tr,irq:buffer std_logic;pd:out std_logic_vector(7 downto 0));end entity poc;architecture behave of poc istype state_type is (idle,busy);signal state:state_type;signal sr,br: std_logic_vector(7 downto 0);begin process(clk)begin if(cs='1') thenif(clk'event and clk='1')thenif(reset='0')thenif(mode='0')then irq<='0';tr<='0';sr<="10000000";else irq<='1';tr<='0';sr<="10000001";end if;end if;if(reset='1')thenif(rw='1'and a="000")thenif(mode='0')then irq<='0';tr<='0';sr<="10000000";else sr<="10000001";tr<='0';irq<='1';end if;elsif(rw='1'and a="001")thenif(mode='0') thenif(rdy='1'and sr(7)='1') then br<=d;sr(7)<='0';end if;if(rdy='1'and sr(7)='0')then pd<=br;tr<='1';end if;if(rdy='0'and tr='1')then tr<='0';sr(7)<='1';end if;end if;if(mode='1')thenif(rdy='1'and irq='1')thenbr<=d;irq<='0';sr<="00000000";end if;if(sr(1)='0'and sr(7)='0')then pd<=br;tr<='1';end if;if(rdy='0'andtr='1')then tr<='0';sr<="10000001";end if;end if;end if;end if;end if;end if;end process;end behave;printer.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity printer isport(clk: in std_logic;tr: in std_logic;reset:in std_logic;rdy: buffer std_logic);end entity printer;architecture behave of printer issignal temp:integer:=0;beginprocess(clk)beginif(clk'event and clk='1')thenif(reset='0') then rdy<='1';end if;if(reset='1')thenif( tr='1')then rdy<='0';elsif(rdy='0'and tr='0') then temp<=temp+1;if(rdy='0'and temp=2)then temp<=0;rdy<='1';end if;end if;end if;end if;end process;end behave;。