clock gating的验证方法
电气测量技术及仪器
TP7512006021656基于微种群遗传算法和自适应B P算法的遥感图像分类/李仪，陈云浩，李京(北京师范大学资源学院)//光学技术.―2005,31(1).―17～20,23.介绍了采用微种群遗传算法和自适应BP算法相结合的混合遗传算法来训练前向人工神经网络（BPNN）的方法。
即先用微种群遗传学习算法进行全局训练，再用自适应BP算法进行精确训练，以达到加快网络收敛速度和避免陷入局部极小值的目的。
将该算法用于遥感图像分类，网络的训练速度及分类结果表明，该算法收敛速度较快，预测精度较高。
图8表3参12TP7512006021657基于小波变换和遗传算法的遥感影像匹配方法的研究/徐建斌，洪文，吴一戎(中国科学院电子学研究所)//电子与信息学报.―2005,27(2).―283～285.该文提出了利用小波分析和遗传算法实现遥感影像的匹配，在对参考影像和目标影像进行小波分解的基础上，利用遗传算法优良的全局寻优特点先对低分辨率的遥感影像进行匹配操作，然后逐级上推，最终实现全分辨率情况下的遥感影像的匹配。
实验结果表明，该算法不仅具有较高的匹配精度，而且具有较高的效率。
图7表1参13TP7512006021658基于改进小波域隐马尔可夫模型的遥感图像分割/郭松涛，孙强，焦李成(西安电子科技大学智能信息处理研究所)//电子与信息学报.―2005,27(2).―286～289.该文提出了一种基于改进小波域隐马尔可夫树（HMT）模型进行图像分割的方法。
该方法利用基于希尔伯特变换对的二维方向小波，这种小波变换具有平移不变性、方向检测性好的特点。
同时该方法还利用拓展HMT 对该改进小波域中尺度间的小波系数相关性进行建模。
并结合多背景融合技术进行遥感图像的分割，得到了优于已有文献的分割结果，而且与同类算法相比，降低了算法所需的计算量。
图7表0参8TP751.12006021659基于改进遗传算法的超光谱图像特征选择方法/刘颖，谷延锋，张晔(哈尔滨工业大学信息工程系)//哈尔滨工业大学学报.―2005,37(6).―733～735,747.提出的特征选择新方法充分利用遗传算法并行搜索、全局寻优的优点，并结合超光谱图像特征选择的具体应用，选择表征类别可分性的判别标准作为评价函数计算个体适应度，通过交叉和变异操作实现个体进化。
验证方法学论文集,面试专用
低功耗验证解决方案August 20, 2010林雪梅linxuemei@王凤海wangfenghai@王欣 wangxin@中星微电子有限公司摘要随着便携性要求的提高，低功耗设计的需求推动了低功耗设计技术在多电压，电压内部管理等技术上的突破。
以MTCMOS/ AVS等一系列技术为代表的设计方案越来越多的应用，让传统的数字电路验证技术受到了越来越大的挑战。
本文通过对现有解决方案的应用，将介绍如何引入业界标准的UPF流程完成多项低功耗设计的验证,以确保电源管理的正确实现。
ABSTRACTAs the requirements of portal devices keep increasing, new design techniques, including multi-voltage, MTCMOS, AVS, etc., are adopted in many low power devices. These design techniques further brings new verification challenges, which are new but critical. This paper, by applying existing solutions, introduces how to apply UPF flow, an industry standard, to verify low power designs. So the management of power supplies can be verified.1.0 简介嵌入式应用是目前SOC芯片最重要的应用之一。
在嵌入式应用，尤其是便携设备的应用中，功耗成为设计者越来越关注的因素。
20世纪80年代，大规模集成电路的发展导致了硬件描述语言（Verilog和VHDL）和综合工具的出现；到了90年代，设计复用以及IP的利用成为了IC设计经常采用的技术。
基于soc的信号跨时钟域传输验证方法研究
基于soc的信号跨时钟域传输验证方法研究 章节一：引言 随着现代电子设备的高度集成化和复杂化，系统芯片（SoC）的应用越来越广泛。SoC通常由多个时钟域组成，不同的时钟域之间需要进行信号传输，这就会涉及到跨时钟域传输的问题。由于时钟域之间的时钟频率不同，会导致信号传输的时序问题，因此跨时钟域传输的验证成为SoC设计中的重要问题之一。
章节二：传统跨时钟域验证方法 传统的跨时钟域验证方法主要包括手工仿真和形式化验证。手工仿真是一种基于测试向量的验证方法，通过手动编写测试用例来验证跨时钟域传输的正确性。但是手工仿真存在着测试用例不完备、测试时间长等问题。形式化验证则是一种基于数学推理的验证方法，可以通过数学方法证明跨时钟域传输的正确性。但是形式化验证需要对SoC进行建模，建模的复杂度较高，同时也存在着不完备性的问题。
章节三：基于仿真的跨时钟域验证方法 基于仿真的跨时钟域验证方法主要包括虚拟时钟和时钟插入两种方法。虚拟时钟是一种将多个时钟域映射到一个虚拟时钟域的方法，通过虚拟时钟域来实现跨时钟域传输的仿真验证。时钟插入则是一种在时钟域之间插入额外的时钟周期来实现跨时钟域传输的仿真验证。这两种方法都可以通过仿真来验证跨时钟域传输的正确性，但是需要对SoC进行修改，同时也存在着仿真时间长等问题。 章节四：基于形式化验证的跨时钟域验证方法 基于形式化验证的跨时钟域验证方法主要包括时钟同步和时钟抽象两种方法。时钟同步是一种通过同步器来实现时钟域之间的同步，从而实现跨时钟域传输的验证。时钟抽象则是一种将时钟域抽象成时钟信号的方法，通过对时钟信号的形式化验证来实现跨时钟域传输的验证。这两种方法都可以通过形式化验证来验证跨时钟域传输的正确性，但是需要对SoC进行建模，建模的复杂度较高。
章节五：结论 跨时钟域传输的验证是SoC设计中的重要问题之一，传统的跨时钟域验证方法存在着不完备性、测试时间长等问题。基于仿真的跨时钟域验证方法可以通过仿真来验证跨时钟域传输的正确性，但是需要对SoC进行修改，同时也存在着仿真时间长等问题。基于形式化验证的跨时钟域验证方法可以通过形式化验证来验证跨时钟域传输的正确性，但是需要对SoC进行建模，建模的复杂度较高。因此，需要根据具体的应用场景选择合适的跨时钟域验证方法。
低功耗Clock-Gating技术在SAR实时成像处理中的应用
低功耗Clock-Gating技术在SAR实时成像处理中的应用陈冰冰;邵洁;王贞松;赵荣彩
【期刊名称】《电子与信息学报》
【年(卷),期】2005(027)003
【摘要】功耗问题在SAR实时成像系统中是不容忽视的.该文以实时成像系统中的输入分机为研究平台,测试了信号处理中常用芯片DSP,SBSRM,FPGA在采用Clock-gating技术前后,功耗的变化.通过大量的实验结果,验证了Clock-gating技术在SAR实时信号处理中的可行性,对降低SAR实时成像系统,尤其是星载实时成像系统的功耗有一定的指导意义.
【总页数】5页(P449-453)
【作者】陈冰冰;邵洁;王贞松;赵荣彩
【作者单位】中国科学院计算技术研究所,北京,100080;北京市遥感信息研究所,北京,100085;中国科学院计算技术研究所,北京,100080;解放军信息工程大学,郑州,450002
【正文语种】中文
【中图分类】TP752
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芯片时钟和数据时序测试方法
芯片时钟和数据时序测试方法英文回答：Overview.Clock and data timing measurements are critical for ensuring the proper functionality and performance ofdigital circuits. These measurements characterize thetiming relationships between clock signals and data signals, which are essential for ensuring that data is transferred and processed correctly. There are various methods and techniques used to test chip clock and data timing, eachwith its own advantages and drawbacks.Testing Methods.1. Oscilloscope Measurement.An oscilloscope is a common tool for measuring clockand data timing. It allows for direct visualization of thesignals, providing a clear understanding of the signal characteristics. Oscilloscopes can be used to measure parameters such as frequency, duty cycle, rise/fall time, and jitter.2. Time Interval Analyzer (TIA)。
How To Successfully Use Gated Clocking
How To Successfully Use Gated Clockingin anASIC DesignDarren JonesMIPS Technologies, Inc.dj@ABSTRACTGated clocking is a true silver bullet for hardware designers. Using this technique, engineers can improve all three major performance metrics of a circuit: speed, area, and power. Unfortunately, EDA tools have traditionally lacked support for gated clocks. These limitations have relegated clock gating to the full-custom design community. However, new features in synthesis and static timing analysis tools have brought gated clocking to mainstream ASIC designers.This paper discusses the pitfalls that still exist to using gated clocks in an ASIC design. Furthermore, it suggests methodologies and workarounds that can be used to avoid these problems so that gated clocking can be used successfully. The paper explains how gated clocking impacts the following areas: logic synthesis, static timing analysis (STA), automatic test-pattern generation (ATPG), clock tree synthesis, and standard-cell library design.1.0Description of ProblemASIC designers primarily use positive edge-triggered D flip flops to generate registers and/or storage elements. These flip flops are clocked every cycle; if they need to hold their previous value, a recirculating MUX circuit is typically used. Figure 1 shows this circuit.Figure 1. Recirculating MUX SchematicWhile this circuit is conceptually simple, it can be improved upon in several ways. Figure 2 shows a functionally equivalent circuit using a gated clock. This circuit is higher performance because it removes the MUX from the timing-critical data input to the flops. Removing these MUXes also saves area. Finally, this circuit is lower power since the flops are not clocked in cycles they do not need to be clocked.NOTE: There are many possible ways of implementing gated clocking. However, most can be generalized to the circuit in Figure 2.Figure 2. Gated Clocking SchematicThe remainder of this paper uses this circuit as a basis for discussion, so a detailed explanation of the logic is needed. In this circuit, the positive pulse of the clock signal is either enabled or disabled by the gate signal. Thus, in any cycle when GATE is deasserted low, GCLK will remain low and no positive edge will be propagated to the downstream flip flops. The transparent-low CLK GATEDQ Q[MSB:LSB]D[MSB:LSB]01DQ GN CLKGCLKGATE GATE_PH2D QQ[MSB:LSB]D[MSB:LSB]CLK latch CLK nandlatch is used to hold the gate stable over the positive pulse of CLK in order to prevent clock glitching. In order to be glitch free, there is a setup and a hold requirement at the NAND gate.Figure 3. Clock Glitch Setup CheckFigure 3 shows the waveform for analyzing setup time checks. In this case, GATE changes late in the cycle. The setup requirement occurs at the positive edge of the clock at the NAND gate, CLK nand . The setup check analysis must use the following timing:•The clock path starts at CLK and ends at the NAND gate. The timing must be for delays of the positive edge of the clock.•The data path starts before GATE , which is itself generated from flip-flops and logic clocked by the positive edge of CLK , goes through the latch (D->Q), and ends at the NAND gate. The timing must be for either positive edge or negative edge of GATE , whichever is longer.Note that in this analysis, the latch is open and therefore, can be thought of as simply a delay element in the path. Ideally, this path would not be analyzed as a latch path.Figure 4. Clock Glitch Hold CheckFigure 4 shows the waveform for analyzing hold time checks. In this case, GATE changes early in the cycle, during the positive pulse of the clock. Since GATE_PH2 must be stable over the entire CLKGATEGATE_PH2GCLK CLK latchCLK nand SETUP CHECKCLKGATEGATE_PH2GCLK CLK latchCLK nandHOLD CHECKpositive pulse of the clock, it must have net positive hold time against CLK nand. There is a race here because GATE_PH2 is also launched from the negative edge of the clock, which opens the latch. The hold check analysis must therefore use the following timing:•The clock timing path starts at CLK and ends at the NAND gate. The timing must be for delays of the negative edge of the clock.•The data timing path starts at CLK, goes through the latch (GN->Q), and ends at the NAND gate. The timing must be for the negative edge of the clock to the latch and then for either positive edge or negative edge of GATE_PH2, whichever is shorter.It is advantageous if CLK latch is a little later than CLK nand since this would give additional hold time margin without impacting the setup check.2.0Gated Clocks and SynthesisSynopsis synthesis tools do have clock glitch checks built in. But, they sometimes do not do the correct analysis. However, the optimization algorithm is robust enough to overcome this problem and still achieve optimal results. This section explains how all this works.2.1 Enabling Clock Glitch CheckingFirst of all, you must enable clock glitch checks since they are disabled by default. To enable clock glitch checks, issue the following command (TCL):set_clock_gating_check-setup$setup_val-hold$hold_val Where:$setup_val is the amount of setup needed at the NAND gate on the data input to allow the output to be glitch free.$hold_val is the amount of hold time needed at the NAND gate to allow the output to be glitch free.NOTE: The above values should be proven using SPICE simulations.2.2 Setup Time ChecksSynopsys tools (Design Compiler, Physical Compiler, and Primetime) recognize the latch in the gating circuit and assume this is a latch path. The latch analysis algorithm divides the setup analysis into two parts, which I call frontside and backside paths:Frontside Path. This is the path in front of the latch. It includes all of the gating logic and ends at the D input of the latch. It is a normal logic path included in the CLK path group.Backside Path. This is the path in back of the latch. It starts at the latch output and ends at the NAND gate. This path is a clock gating check path.Synopsys’ latch analysis algorithm will first analyze the frontside path. It will borrow time across the latch so that the frontside path can meet timing. Then, it analyzes the backside path given theamount of borrowing it did on the frontside. What this tends to do is leave violations on the backside path, even though the frontside path appears to be meeting timing.While this algorithm does work well for generic latch-based designs, it is exactly the opposite of what is needed for the clock gating circuit. Since the backside path is actually a clock glitch check, it should take priority over the frontside path, which is a normal logic path. The analysis should first time the backside path, then set the borrowed time to the maximum available time such that there are no clock glitches. Then, the frontside path will correctly reflect the slack on the entire path. This is exactly what you want, since the synthesis tool cannot synthesize any logic in the backside path anyway.In spite of the above analysis problems, the synthesis tools will try to improve the frontside path, even if it appears to meet timing. Thanks to the latch optimization algorithm, the tool recognizes that a failure in the backside path can be improved by optimizing the frontside path. However, even this feature may not be enough to get correct results. In the cases where there is a failure on both the frontside and backside paths, the total path failure (the sum of frontside failure and backside failure), will be split into two parts. This will mask what may be one of the most critical paths in the design and the tool may not select these paths for optimization since separately, they do not appear to be the most critical paths.You could use set_critical_range if your worst violation is small. However, this solution can significantly increase synthesis runtimes. The recommended solution is to useset_max_time_borrow to limit the amount of borrowing so that the backside path just meets timing and all of the violation is seen on the frontside path. The exact command to use is given in the next section.2.3 Impact of Ideal ClocksAs the reader may recall, when an ideal clock is used, all clock endpoints are assumed to have perfect skew, but the clock uncertainty is subtracted to account for skew. With the gated clock circuit, you can see in Figure 2 that the clock to the latch and the NAND gate will be early when compared to the clock of the flip-flops. Thus, paths ending at these latches will have a reduced cycle time and require tighter timing than normal paths do.The above problem does not impact the clock glitch hold check, since this path is a 0-cycle path. However, it does impact the setup time optimization since by default, the tool will optimize for a full cycle, not a reduced cycle.The recommended workaround for this problem again uses set_max_time_borrow to limit the amount of time that can be shifted to the frontside path to account for this reduced cycle time. Combining this solution with the previous solution for the split paths gives the following command:set_max_time_borrow[expr$phase-$unc-$clkbufdelay-$dqdelay]\[get_clock$clk]Where:$phase is the phase time of the negative phase of the clock.$unc is the clock uncertainty at the latches$clkbufdelay is the propagation delay for the posedge of the clock through clock buffering that is downstream from the gating element, (including delay through the gating element) $dqdelay is the propagation delay through the latch.The phase time available for borrowing is reduced by three factors. First, clock uncertainty: there is still uncertainty about when the clock will arrive at the NAND gate, although this uncertainty may be less than the full-chip uncertainty. Second, the clock buffer delay: this factor is applied due to the early clock effect described in this section. Third, the latch D->Q propagation delay: this factor must be included because the delay through the latch itself is included in the backside path and is not available for borrowing into the frontside path.The above command forces synthesis to see the backside path just meet timing. At the same time, it forces the frontside path to use all the available time in the reduced cycle.2.4 Setup Time Check ReportingOne further ramification of the splitting of the gating path into frontside and backside paths is that the setup time check appears at first glance to be incorrect. The following shows a report from DesignCompiler for a sample backside setup clock gating check.Startpoint:U_gate_ph2(negative level-sensitive latch clocked by clk)Endpoint:U_gclk_n(gating element for clock clk)Path Group:clkPath Type:maxPoint Incr Path-----------------------------------------------------------clock clk(fall edge)50.0050.00clock network delay(propagated)12.0062.00time given to startpoint21.0083.00U_gate_ph2/D(LATCHN)0.0083.00rU_gate_ph2/Q(LATCHN)20.00*103.00rU_gclk_n/A(NAND2)0.00*103.00rdata arrival time103.00clock clk(rise edge)100.00100.00clock network delay(propagated)10.00110.00clock uncertainty-0.20109.80U_gclk_n/B(NAND2)0.00109.80rclock gating setup time0.00109.80data required time109.80-----------------------------------------------------------data required time109.80data arrival time-103.00-----------------------------------------------------------slack(MET) 6.80This report shows the data path beginning at the falling edge of the latch clock. As was described earlier, the correct setup analysis must start from the positive edge of the clock and propagatethrough the gating logic and then through the latch is if it were transparent. In fact, this is what the tool is doing. The following listing shows the report for the associated frontside latch setup path.Startpoint:U_internal_sig1(rising edge-triggered flip-flop clocked by clk) Endpoint:U_gate_ph2(negative level-sensitive latch clocked by clk)Path Group:clkPath Type:maxPoint Incr Path-----------------------------------------------------------clock clk(rise edge)0.000.00clock network delay(propagated)10.0010.00U_internal_sig1/CLK(DFF)0.0010.00rU_internal_sig1/Q(DFF) 3.00*13.00fU_internal_sig3/Y(INV)70.00*83.00rU_gate_ph2/D(LATCHN)0.00*83.00rdata arrival time83.00clock clk(fall edge)50.0050.00clock network delay(propagated)12.0062.00U_gate_ph2/GN(LATCHN)0.0062.00ftime borrowed from endpoint21.0083.00data required time83.00-----------------------------------------------------------data required time83.00data arrival time-83.00-----------------------------------------------------------slack(MET)0.00As can be seen, this path does in fact start from the positive edge of the clock and arrives at the input to the latch at time T=83. The backside analysis reproduces this path timing and shows time T=83 at the latch input. It then propagates timing through the open latch correctly to the NAND gate. The tool does a good job of obfuscating the true analysis, but it does in fact time the correct path.3.0Gated Clocks and Primetime STAPrimetime uses similar algorithms to its synthesis brethren for analyzing clock glitches. Again, these checks have to be enabled, since they are disabled by default:set_clock_gating_check-setup$setup_val-hold$hold_valMore importantly, the problems addressed during synthesis must also be addressed during STA:•STA does not have the analysis problem associated with ideal clocks as long as STA is run with detailed actual clock network delays.•STA does incorrectly divide the clock gate path into two separate paths, thus obscuring potential critical paths.•STA has a similar reporting deficiency for clock_glitch setup checks. However, as was true forsynthesis, STA does time the correct paths.The problem in the second bullet must be addressed differently for STA than it was for synthesis. In synthesis, we used estimated for clock timing. With STA, we have actual net delays, and so we can correct the borrowing for each latch individually to be 100% accurate. However, the spirit of the workaround is the same: use set_max_time_borrow to allow just enough time on the backside path for glitch-free operation while forcing all available slack to the frontside path. Here is the TCL code to use: (line numbering added for clarity)1:set timing_include_available_borrow_in_slack true2:set paths[get_timing_paths-group**clock_gating_default**\ -max_paths10000]3:foreach_in_collection path$paths{4:set slack[get_attribute$path slack]5:set tb[get_attribute$path time_lent_to_startpoint]6:set stpt[get_attribute$path startpoint]7:set_max_time_borrow[expr$tb+$slack]$stpt8:}As the reader may recall, by default, Primetime will only borrow enough time to exactly meet timing. Thus, while a latch path may have lots of slack on the backside, the frontside is normally reported as having 0 slack. From the timing reports, this makes it difficult to see if the path actually has 0 slack, or if it has positive slack that is just not being reported. The command on line1 allows Primetime to report positive slack for those paths that could borrow more time. This is done because we are going to push slack to the frontside and we want it to report positive slack instead of 0 slack.After line2, $paths will contain a collection of all the clock gating paths. We willset_max_time_borrow on each of these paths individually.We want to push all slack from the backside clock_gating check to the frontside logic path. The commands inside the loop get the backside slack and the time that was borrowed in order to get this result. Then, it adjusts the maximum borrow time of the frontside path according to the slack. Thus, if the clock_gating check was failing, this will reduce the available borrow time so that it will pass. If the backside path was passing, it makes all of this slack available to the frontside path. Accurate failures will now be lumped onto the frontside path.4.0Gated clocks and ATPGATPG is almost always one of the biggest concerns for ASIC designers when using gated clocks. In reality, it is not a difficult problem to solve. It breaks down into two parts- enabling scan testing, and optimizing ATPG results.4.1 Enabling Scan TestingThe most important thing is to be able to run scan tests. For this, the scan chain must be clocked when it is being shifted (when scan_enable is asserted). The easiest way to assure this is to disable all gating elements when scan_enable is asserted. This amounts to an OR gate on the GATE input, basically forcing GATE on when scan_enable is asserted.This OR gate can be placed in front of the latch or behind the latch. If it is in front, then it looks just like any other logic in front of the latch. If it is behind the latch, then there is one benefit and one penalty. The benefit is that it adds extra hold time margin for the clock glitch hold check. It does this by delaying the data signal, which helps the clock win the race.The penalty for putting the OR gate behind the latch is that the scan_enable signal must then be stable over phase1 of the clock, since it does not go through the latch. In practice this is not difficult to guarantee. This should not impact performance, since scan is only run at relatively slow speed.NOTE: The OR gate itself does impact the setup path, but this is unavoidable. The choice of its location in front of or behind the latch has no effect on the setup path, since during setup analysis the latch is open and the OR gate will be in the path no matter which location is chosen.4.2 Optimizing ATPG ResultsOnce you have forced clocks to run during scan shifting, the degree of coverage achieved is largely dependent on your ATPG tool. Popular ATPG tools can handle gated clock circuits. This means that they can properly model an unclocked flop and generate patterns which can detect faults in the gating logic.Using gated clocks does introduce one ATPG untestable fault: stuck-at-0 on the latch enable input, GN. Since the latch is included purely for timing reasons, if it is stuck open, then the circuit may still functionally pass, depending on timing. This is inherently untestable by scan test patterns. However, since the latch is needed to guarantee hold time, it is a zero-cycle path which may fail when the gate signal changes values early in a cycle. This makes faults of this nature more likely to be detectable during slower-speed operation. Timing analysis can be run to prove which faults will be detected and which will not affect proper operation of the circuit.Even if your scan tool does not support gated clocking, there is a workaround. You can replace all registers that use gated clocking with the recirculating MUX circuit just for ATPG. This workaround relies on the fact that the circuit shown in Figure 1 is functionally equivalent to the gated clocking circuit. Patterns which run on the recirculating MUX will also run on the gated clock circuit. This solution is not as accurate as using a more advanced ATPG tool which directly supports gated clocking, but it will generate legal patterns with decent coverage, if not perfect coverage.5.0Gated Clocks & CTS toolsFor some reason, most mainstream clock tree synthesis tools are relatively primitive and have trouble achieving good skew even with vanilla non-gated clock trees. As one might imagine, there will also be limitations when using a gated clock tree. Nonetheless, this section describes several guidelines to follow. If your CTS tool can support all of these guidelines, you are home free. If it cannot follow any of them, give up and do not use gated clocks. For most design teams, their CTS tool will be somewhere in between these two extremes. Success has been achieved using popular CTS tools and a little intelligent scripting.Do Not Skew-match the Latch or NAND gate clock endpoints with the Flops. Most CTS tools will automatically assume all clock endpoints should be skew-matched against all others. This is not true for the clock gating circuit. The latch clock and the NAND gate clock will necessarily be earlier than the flip-flop clocks and should not be skew-matched together.Do Skew-match Latch and NAND gate clock endpoints against each other. The previous rule is not meant to allow poor skew on the gating element clocks. You must still achieve good skew on these endpoints, when taken as their own group.Do Skew-match the gated flops with un-gated flops. Most designs using gated clocks will have some logic which is not gated. Make sure that the CTS tool skew matches all of the flops: gated and non-gated.Place the Latch and the NAND gate close together. These two cells need to have the same clock and have well-controlled delays on the nets between them. Placing them close together helps to achieve these goals.Route the Latch and the NAND gate on the same clock Subnet. There needs to be very tightly controlled skew between these two cells. Achieving this is most easily accomplished by connecting these two cells to the same physical wire.Make the Clock Gating circuit the leaf level Clock Driver. As stated previously, the latch clock is earlier than the clock to the flip-flops. How early it is may directly impact the maximum frequency of the design. Thus, the clock gating circuit wants to be at the leaf level of the clock tree. In other words, there should be an absolute minimum of clock buffering after the NAND gate. This rule implies that the entire clock gating circuit should be duplicated, not just the downstream buffers.6.0Gated Clocks & Cell LibrariesNow that you have read and understood the previous pitfalls, workarounds, and suggestions, there is one final suggestion which can solve many of the above problems all at the same time. If your standard cell library has a few strategic cells designed for clock gating, many of the previously documented problems go away. The cells required can be divided into two groups- the front-end gating cell and the backend clock driver.The front-end gating cell is comprised of the latch and the NAND gate. In addition, to help ATPG, we include an OR gate for enabling scan shifting. Figure 5 below shows the schematic for this, the GCK cell:Figure 5. GCK CellThis cell must be designed such that it never generates clock glitches. It would have the following timing arcs:•Setup and hold time requirements at the GATE input relative to the positive edge of CLK.•Setup time requirement at the SCAN_ENABLE input relative to the positive edge of CLK.•Hold time requirement at the SCAN_ENABLE input relative to the negative edge of CLK.•Delay from positive edge of CLK to the negative edge of GCLK_N.•Delay from negative edge of CLK to the positive edge of GCLK_N.The backend cell is a plain inverter used to invert GCLK_N to GCLK and drive downstream flip-flops. This cell should have a large variety of drive strengths, since the drive strength selections will largely determine how well skew can be matched. Furthermore, all of the backend cells should be the same size and have the same IO pin locations. This effectively means that all cells will be the size of the largest cell. The advantage of this is that it makes for easy swapping of these cells for improving clock skew. Since there are relatively few of these cells in the design, their size has little effect on overall chip size.By having these two types of cells, you will see the following benefits:•Clock gating checks are not necessary in synthesis and STA, since the clock is guaranteed to be glitch free.•The frontside path is seen as a regular cycle path by synthesis and STA due to the posedge requirements on the gate signal.•The ideal clock problem in synthesis can be addressed through a semi-customizeable synthesis model for the front-end gating cell. You can artificially increase the setup time requirement by the amount of clock insertion delay, thus squeezing the frontside path into a reduced cycle.•Scan testing is enabled because the gating cell is always enabled when SCAN_ENABLE is asserted.As you can see, these simple cells greatly simplify many of the problems inherent to clock gating.7.0Conclusions and RecommendationsTen years ago, virtually no mainstream ASIC design tools supported gated clocking. Now, Synopsys and other EDA companies have begun to address this design style. This paper showed how to successfully navigate various stages of chip design to successfully integrate gated clocks with your design.While most tools do not by default do the correct thing, they can be directed to the correct operation by a few intelligent scripts. Furthermore, a few strategic standard cells can also go a long way toward alleviating the remaining tool limitations. Even though manual work is still required, the benefits of gated clocking to performance, area, and power are well worth the effort needed to implement them successfully.8.0AcknowledgmentsIt was Soumya Banerjee who suggested that my work on clock gating might be useful to SNUG members.Copyright(r) 2002, MIPS Technologies, Inc. All rights reserved.。
后端基本概念
为了方便大家尽快找到需要的话题，经icfb版主建议，编辑这个数字后端的FAQ。
如果您是初学者，建议先搜索相关的资料，读读其他人的帖子，一些基本概念在那里都已经讨论过了。
如果您已经有2年以上的实战经验，下面这些雕虫小技就不太值得您去浪费时间了。
先说说作为一个有经验的后端（暫不包括DFT工程师和layout工程师）工程师，需要掌握哪些知识4个级别：1）知道一些基本概念，2）简单地掌握这门技术，3）熟练4）精通半导体工艺--2RTL coding -- 2综合-- 2时序约束-- 3APR -- 3DFT -- 2DRC/LVS -- 3仿真-- 2形式验证-- 2以下是FAQ分类：2楼：时序约束，STA3楼：综合DC/RC4楼：APR （floorplan，place，CTS，route）5楼：验证（LEC，DRC，LVS等）6楼：DFT7楼：低功耗8楼：面试9楼：名词解释时序约束，STA(1) clockQ1.1 什么是同步时钟？时钟频率是整倍数，并且相互之间的相位是固定而且相差可预知的，才可以称得上是同步时钟。
其他的都算异步时钟。
比如，5M，10M是同步2M，3M一般算异步一个时钟，输出到另一个芯片中，转一圈后，以同样的频率返回到自己的芯片，因为无法确定时钟在另一个芯片里面的latency，所以输出的时钟与输入的时钟算异步一个时钟进到2个PLL，就算那2个PLL的输出频率相同，一般也算是异步时钟，除非你de-skewQ1.2 如何处理同步时钟？设计要求严格的公司，就算是同步时钟，数据在同步时钟间传送时，依然要用meta-stability FF，可以set_false_path如果放松要求，不用meta-stability FF，则同步时钟之间是real path，做CTS时，同步时钟要clock tree balance。
注意不同频率的同步时钟的最小时间间隔被用来检查setup如果上升下降沿混用的话，setup的时间间隔就只有半个时钟周期了Q1.3 如何处理异步时钟？很简单，set_false_path注意要from A to B，同时要from B to AQ1.4 如何定义时钟？create_clock 如果指定某个pin/port，就是实时钟，如果没有指定pin和port，就是虚拟时钟巧妙利用waveform选项可以做出不同波形的时钟被定义成时钟的net，在综合时，自动带有ideal network和dont_touch的属性。
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clock gating的验证方法
Clock gating是一种常用的功耗优化技术，其原理是在时钟信号到达时钟门控器件之前将时钟信号屏蔽，以达到降低功耗的目的。
而针对这种技术，需要进行验证以保证其正确性和可靠性。
本文将介绍clock gating的验证方法。
1.功能仿真
功能仿真是验证clock gating的最基本方法。
通常使用的是基于RTL级别的仿真工具，通过对设计的时钟门控电路进行仿真，验证电路在激励下的输出是否符合预期。
仿真测试包括了针对时钟门控器件的开启和关闭信号的测试，以及对整个时钟域的时序分析等。
2.时序仿真
时序仿真是对时序电路进行验证的一种方法。
在clock gating设计中，时序仿真可以帮助验证时钟门控电路的时序逻辑是否正确。
时序仿真的过程是通过输入激励来模拟电路的时序行为，以检查电路的时序逻辑是否正确。
3.静态分析
静态分析是验证clock gating的一种方法。
它可以被用来检查设计中的一些潜在错误，比如说时钟门控器件的开启和关闭信号的正确性。
静态分析可以通过在设计中检查时钟门控器件的状态、时钟域
的分析和时序逻辑的检查等方法来实现。
4.形式化验证
形式化验证是一种验证方法，它可以对设计进行形式上的证明，以证明设计的正确性。
在clock gating设计中，形式化验证可以对时钟门控电路的逻辑进行证明，以证明其正确性。
形式化验证的过程是通过形式化建模、状态探索和证明等步骤来实现。
5.物理验证
物理验证是对设计进行布局和布线，以验证电路的物理特性是否符合预期的一种方法。
在clock gating设计中，物理验证可以通过对时钟门控电路的布局和布线进行验证，以验证电路的物理特性是否符合设计要求。
6.模拟验证
模拟验证是对设计进行模拟和分析，以验证电路的性能和可靠性的一种方法。
在clock gating设计中，模拟验证可以用来验证时钟门控电路的性能和可靠性。
模拟验证的过程是通过激励输入和电路响应的分析来实现。
clock gating的验证方法包括功能仿真、时序仿真、静态分析、形式化验证、物理验证和模拟验证等多种方法。
在设计中，需要根据
具体情况选择合适的验证方法，以保证设计的正确性和可靠性。