序列检测器的设计 实验报告
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EDA实验报告书
设计原理图及源程
序LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AA IS
PORT ( CLK ,DIN,RST : IN STD_LOGIC;
SOUT : OUT STD_LOGIC;
END AA;
ARCHITECTURE behav OF AA IS
TYPE states IS (s0, s1, s2, s3,s4,s5,s6,s7,s8);
SIGNAL ST,NST : states :=s0 ;
BEGIN
COM : PROCESS(ST,DIN) BEGIN
CASE ST IS
WHEN s0 => IF DIN = '1' THEN NST <= s1;ELSE NST<=s0; END IF; WHEN s1 => IF DIN = '0' THEN NST <= s2;ELSE NST<=s0; END IF; WHEN s2 => IF DIN = '1' THEN NST <= s3;ELSE NST<=s0; END IF; WHEN s3 => IF DIN = '0' THEN NST <= s4;ELSE NST<=s0; END IF; WHEN s4 => IF DIN = '1' THEN NST <= s5;ELSE NST<=s0; END IF; WHEN s5 => IF DIN = '1' THEN NST <= s6;ELSE NST<=s0; END IF; WHEN s6 => IF DIN = '1' THEN NST <= s7;ELSE NST<=s0; END IF; WHEN s7 => IF DIN = '0' THEN NST <= s8;ELSE NST<=s0; END IF; WHEN s8 => IF DIN = '0' THEN NST <= s2;ELSE NST<=s0; END IF; WHEN OTHERS => NST <= st0;
END CASE ;
END PROCESS;
REG: PROCESS (CLK,RST)
BEGIN
IF RST='1' THEN ST<=s0;
ELSIF ( CLK'EVENT AND CLK='1') THEN ST<=NST;
END IF;
END PROCESS REG;
SOUT<='1'WHEN ST=s8 ELSE '0' ;
END behav;
仿真波形
图
实验结果
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY SM1 IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
input1 : IN STD_LOGIC := '0';
input2 : IN STD_LOGIC := '0';
output1 : OUT STD_LOGIC
);
END SM1;
ARCHITECTURE BEHAVIOR OF SM1 IS
TYPE type_fstate IS (st1,st2,st3,st4,st5,st6,st7,st8,st0);