集成电路设计Ch5 process integration

Chapter 5 Process IntegrationOutline⏹Device Isolation⏹Interconnection⏹MOS technology⏹Bipolar technology5.1 Device isolationTerms •Modules:groups of processese.g.: isolation modulesinterconnection modules •Metrics of isolation modules: DensityProcess complexityYieldPlanarityParasitic effectsTraditional device isolationLocal oxidation of Silicon (LOCOS) isolationLOCOS isolationBird’s beak: lateral diffusion through stress relief oxide.Poly-buffered LOCOS (PBL)Reduced bird’s beak: less diffusion through thinner stress relief oxide.Sidewall masked isolation (SWAMI)Shallow trench isolation (STI)⏹1) Mask stack formation.⏹2) STI etch.⏹3) Liner oxidation.⏹4) Gap fill with CVD oxide.⏹5) CMP.⏹6) Hard mask removal.STI is a more scalable isolation technology than those based on LOCOS.Chemical-mechanical polishing (CMP) ConfigurationsCMP Application ExampleModule: STI etch and trench fill1) Sidewall angle control (70o to 90o).2) Corner rounding.CVD oxide: LPCVD furnace, APCVDDeep trench isolation (STI)Other isolation techniques •Silicon on Insulator isolation techniques •Semi-Insulating substrate5.2 Contact and interconnectionInterconnectionRequirements of InterconnectionPossible interconnect materialsElectrical Contacts to SiElectrical Contacts to Si⏹The depletion region constitutesa space charge layer in which there is a non-uniform internal field leading to E Fm and E Fn line up and energy band bending.☐The energy band in W regionmust bend to increase E c-E Fntowards the junction but keepsunchanged far away fromjunction.☐The bending is just enough forthe vacuum level to becontinuous and changing byΦm -Φn from SC to the metal.χΦmJ1 J2resistance than the neutral n-region. can now readily overcome theIt is also possible to obtainjunction betweenΦpis the work function for the p-type semiconductor.⏹There are more energetic electrons in the metal than in the CB of SC, which readily tunnel into the semiconductor in search of lower energy levels.⏹A fter contact, tunneling electrons pile in the CB of the semiconductor near the junction.–Equilibrium is reached when the accumulated electrons in the CB of the SC prevent further electrons tunneling from the metal, or when the Fermi level is uniform across the whole system from one end to the other.–In sharp contrast toSchottky junction, theconduction electrons oneither side of the junctionhave about the sameenergy and therefore thereis no barrier involvedwhen cross the junction ineither direction.⏹For Schottky junction☐n-type Semic: Φm> Φn☐p-type Semic: Φm< Φp⏹For Ohmic contact☐n-type Semic: Φm< Φn☐p-type Semic: Φm> Φpe.g.: Si = 4.01, Eg= 1.1, is it possible to get Ohmic contact with Al or Cu (ΦAl=4.28, ΦCu= 4.56) ?ΦnSi <4.56 Al seems possible but depends on the doped concentrationΦpSi>4.56 not possible How about AsGa?ΦnSi <4.78 Al and Cu seems possible but depends on the doped concentrationΦpSi>4.78 not possible•Due to existence of the defects at the junction interface, the barrier heights exist even though the work function of some metal lower than that of the n-type semiconductors.Contact Resistance Rc•PtSi is commonly used as a Schottky contact for lightly doped n-type Silicon.•Ohmic contact formation:Select metal Φ< Φn, or Φm> Φp;mHeavily dope the semiconductor and take somespecific processes such as annealing;✓when n >1019, depletion width is quite narrow whichresults in tunneling effect leading to very lowcontact resistance;✓Annealing makes metallization having goodadhesion to semiconductor.Make alloyed contacts for compoundsemiconductors: GeMoW, NiAuGe…Multilevel metallization⏹Due to the requirement of the high speed operation, it is basic to reduce the impedance and node/fringing capacitance of the interconnections.⏹As the results, the number of levels of interconnect on modern IC processing is constantly increasing.⏹Currently, 10 levels of interconnects are quite normal.⏹As lithography and etching have continued to improve, it is now possible to form lines whose spacings are much less than their thickness. This has driven leading edge technologies to abandon Al in favor of Cu.Multilever interconnect structurePlanarization TechniquesSpin-On Glass (SOG)SOG AnnealingDeposit and EtchbackChemical Mechanical Polishing (CMP)。