NXP ARM MCU Introduction - Cortex Core - 20100113_R

FETCH
ISR2
POP
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Wake-Up Interrupt Controller (WIC)
Not available prior to Revision 2 Cortex-M3 core Allows “automatic” wake-up while clocks are stopped
– Works in all power-down modes – Does not require separate enable for wake-up and interrupt
100 Throughput
8/16-bit
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8-bit LPC900(/01) 2-Clock LPC700 6-Clock
16-bit XA
1
C51X2 6-Clock
Memory Size 2 KB 64 KB 1 MB >16 MB
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NXP ARM-based 32-bit Microcontroller Portfolio
/products/CPUs/ARM_Cortex-M3.html
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Cortex-M3特点
– – – – – – – – 高性能 – 1.25 DMIPS/MHz 统一的Thumb-2指令集 简单的编程模型，100% C代码 低延迟中断响应 先进的低功耗模式 全面的调试和跟踪功能 灵活的内存保护单元 (MPU) 广泛的生态系统和工具支持
Choice of ARM cores •Match performance to application Common core platform •Common tool chain •Code reuse •Common IP •Easy migration •Lower learning curve

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What is Cortex-M3 Core?
‣ ‣ ‣ ‣ ‣ ‣ ‣ ‣ ‣
Harvard architecture with separate local instruction and data buses 3-stage pipeline with limited branch prediction Thumb-2® instructions ALU with support for H/W divide and single cycle multiply Built-in Nested Vectored Interrupt Controller (NVIC) with Wakeup interrupt controller (WIC) Automatic state save and restore for interrupts Advanced debug components Integrated low power modes Memory Protection Unit (MPU)
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Cortex-M3 Interrupts
Nested Vector Interrupt Controller (NVIC)
Cortex Interrupts have Low Latency
– 12 cycles vs. 24-42 cycles on ARM7TDMI
Processor state automatically saved and restored
– Large subset of 32-bit ARM instructions – Backwards compatible to 16-bit Thumb® instruction set
Includes 12 new instructions:
– Bit field, Table branch, If/Then, Multiply, Divide, etc.
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NVIC Latency Details
12-cycle interrupt latency
– 6-cycle register push (R0-R3, R12, LR, PC, xPSR) – 6-cycle interrupt address fetch
PUSH FETCH
ISR
POP
Pre-Emption
Hardware Divider
– Instruction takes from 2 - 12 cycles depending on dividend and divisor – Instruction is interruptible – The hardware divider is the main reason the Dhrystone MIPs are higher than ARM7
NXP Microcontrollers Introduction
NXP Semiconductors 2010
NXP Microcontroller Products & Cores
16/32-bit ARM ARM926EJ, ARM922T-S (LPC3000, LH7A4xx) ARM968E-S (LPC2900) ARM720T (LH795xx) ARM7TDMI-S (LPC2000, LH754xx) ARM Cortex-M3 (LPC1700) ARM Cortex-M0 (LPC1100) 51MX 6-Clock 80C51 12-Clock
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ARM7TDMI vs. Cortex-M3
FEATURES Architecture ISA Support Pipeline Interrupts Inter-Interrupt Latency Sleep Modes Memory Protection Dhrystone ARM7TDMI ARMv4T (von Neumann) Thumb®/ARM 3-stage FIQ/IRQ 24 – 42 cycles None None 0.95 DMIPS/MHz (ARM) 0.74 DMIPS/MHz (Thumb®) Power Consumption Area 0.28 mW/MHz 0.62 mm2 (core only) 0.19 mW/MHz 0.86 mm2 (core + peripherals) ARM Cortex M3 ARMv7-M (Harvard) Thumb-2® 3-stage + branch speculation NMI + 1 to 240 physical interrupts 12 cycles Integrated 8 region MPU 1.25 DMIPS/MHz
– High priority ISR runs before completion of low priority ISR
PUSH ISR1 POP PUSH ISR1 ISR2 POP
Tail-Chaining
– Consecutive ISRs skip POP and PUSH
PUSH ISR1
SC100™
低成本
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ARM Cortex-M Processors
Cortex-M family optimised for deeply embedded
– Microcontroller and low-power applications
ARM Cortex-A Series:
Applications processors for feature-rich OS and user applications
Memory footprint similar to Thumb® but with performance similar to ARM
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Math performance of Cortex-M3
Single Cycle Multiply
Calculation 16b x 16b 32b x 16b 32b x 32b 32b x 32b Result 32b 32b 32b 64b Clock Cycles 1 1 1 3-7*
Eliminates the need to periodically wake-up the controller and poll the interrupts
– Saves power
When the CPU enters power-down, sleep, or deep sleep modes by executing the WFI (Wait For Interrupt) instruction, the NVIC sends a mask of the current interrupt situation to the WIC This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately
– Dynamic reprioritization of interrupts
Interrupts set to the same priority level have a default hardware priority level Cortex replaces the FIQ on the ARM7TDMI with an NMI interrupt
Relative DMIPS/MHz
ARM7 (ARM) Cortex-M3
Relative Code Size
8051
ARM7 (ARM) Cortex-M3
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Thumb-2® mode
A new ARM instruction set that mixes 16 & 32-bit instructions