VHDL源代码
VHDL源代码：library ieee; --显示器彩条发生器use VGA isport(clk,mode :in std_logic; --扫描时钟/显示模式选择时钟d,hs,vs,r,g,b:out std_logic); --行，场同步/红，绿，蓝end VGA;architecture a of VGA issignal hs1,vs1,fclk,cclk,divide_clk,dly: std_logic;signal mmode :std_logic_vector(1 downto 0); --方式选择signal cnt :std_logic_vector(2 downto 0);signal fs :std_logic_vector(3 downto 0);signal cc :std_logic_vector(4 downto 0); --行同步/横彩条生成 signal ll :std_logic_vector(8 downto 0); --长同步/竖彩条生成 signal grbh :std_logic_vector(3 downto 1); --X 横彩条signal grby :std_logic_vector(3 downto 1); --Y 竖彩条signal grbx :std_logic_vector(3 downto 1); --文字signal grbt :std_logic_vector(3 downto 1); --图案signal grbp :std_logic_vector(3 downto 1);signal grb :std_logic_vector(3 downto 1);signal x :integer range 0 to 800;signal x1: integer range 0 to 800;signal y1: integer range 0 to 600;signal x2: integer range 0 to 800;signal x3: integer range 0 to 800;signal x4: integer range 0 to 800;signal x5: integer range 0 to 800;signal x7: integer range 0 to 800;signal x8: integer range 0 to 800;signal x9: integer range 0 to 800;signal x10: integer range 0 to 800;signal x11: integer range 0 to 800;signal y2: integer range 0 to 600;signal y3: integer range 0 to 600;signal y4: integer range 0 to 600;signal y5: integer range 0 to 600;signal y6: integer range 0 to 600;signal c: integer range 0 to 30;begingrb(3)<=(grbp(3) xor mode) and hs1 and vs1;grb(2)<=(grbp(2) xor mode) and hs1 and vs1;grb(1)<=(grbp(1) xor mode) and hs1 and vs1;process(mode)beginif mode'event and mode='1' thenif mmode="11" thenmmode<="00";elsemmode<=mmode+1;end if;end if;end process; --四种模式process (mmode)beginif mmode="00" then grbp<=grbx;elsif mmode="01" then grbp<=grbh; --选择横彩条 elsif mmode="10" then grbp<=grby; --选择竖彩条elsif mmode="11" then grbp<=grbh xor grby; --选择棋盘格 else grbp<="000";end if;end process;process(clk) --3/4分频 beginif clk'event and clk='1' thencnt<=cnt+3;dly<=cnt(2);end if;--if cnt<3 then-- divide_clk<='0';--elsif cnt<5 then-- divide_clk<='1';--else-- cnt<="000";--end if;end process;divide_clk<=(cnt(2) xor dly) and clk;process(divide_clk) --13分频beginif divide_clk'event and divide_clk='1' thenif fs=12 thenfs<="0000";elsefs<=fs+1;end if;end if;end process;process(fclk)beginif fclk'event and fclk='1' thenif cc=29 thencc<="00000";elsecc<=cc+1;end if;end if;end process;d<=fclk;process(cclk)beginif cclk'event and cclk='1' thenif ll=481 thenll<="000000000";elsell<=ll+1;end if;end if;end process;process(cc,ll)beginif cc>23 then --行同步hs1<='0';elsehs1<='1';end if;if ll>479 then --长同步 vs1<='0';elsevs1<='1';end if;end process;process(clk)beginif clk'event and clk='1' thenif hs1='0' thenx<=0;elsex<=x+1;end if;end if;end process;process(x,ll,cc,hs1,vs1)variable s1: integer range 0 to 3;beginif cc<3 then grbh<="111"; --竖彩条 elsif cc<6 then grbh<="110";elsif cc<9 then grbh<="101";elsif cc<12 then grbh<="100";elsif cc<15 then grbh<="011";elsif cc<18 then grbh<="010";elsif cc<21 then grbh<="001";else grbh<="000";end if;if ll<60 then grby<="111"; --横彩条 elsif ll<120 then grby<="110";elsif ll<180 then grby<="101";elsif ll<240 then grby<="100";elsif ll<300 then grby<="011";elsif ll<360 then grby<="010";elsif ll<420 then grby<="001";else grby<="000";end if;if x=4 thengrbx<="100";elsif x=180 thengrbx<="001";elsegrbx<="000";end if;if ll>20 and ll<24 thenif x<110 thengrbx<="100";end if;end if;if ll>30 and ll<33 thenif x<80 thengrbx<="100";end if;end if;if ll>445 and ll<449 thenif x>90 thengrbx<="001";end if;end if;if ll>437 and ll<440 thenif x>100 thengrbx<="001";end if;end if;--"湖"if ll>89 and ll<94 thenif x=100 or x=103 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>93 and ll<98 thenif x=102 or x=103 or x=104 or x=106 or x=108 then grbx<="110";end if;end if;if ll>97 and ll<102 thenif x=100 or x=103 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>101 and ll<106 thenif x=102 or x=103 or x=104 or x=106 or x=108 thengrbx<="110";end if;end if;if ll>105 and ll<110 thenif x=100 or x=102 or x=104 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>109 and ll<114 thenif x=100 or x=102 or x=103 or x=104 or x=106 or x=108 then grbx<="110";end if;end if;if ll>113 and ll<118 thenif x=106 thengrbx<="110";end if;end if;--"南"if ll>121 and ll<126 thenif x=104 thengrbx<="110";end if;end if;if ll>125 and ll<130 thenif x>99 and x<109 thengrbx<="110";end if;if ll>129 and ll<134 thenif x=104 thengrbx<="110";end if;end if;if ll>133 and ll<138 thenif x>99 and x<109 thengrbx<="110";end if;end if;if ll>137 and ll<142 thenif x=100 or x=108 thengrbx<="110";end if;end if;if ll>141 and ll<146 thenif x=100 or x=103 or x=105 or x=108 thengrbx<="110";end if;end if;if ll>145 and ll<150 thenif x=100 or x=102 or x=103 or x=104 or x=105 or x=106 or x=108 then grbx<="110";end if;end if;if ll>149 and ll<154 thenif x=100 or x=104 or x=108 thengrbx<="110";end if;if ll>153 and ll<158 thenif x=100 or x=102 or x=103 or x=104 or x=105 or x=106 or x=108 thengrbx<="110";end if;end if;if ll>157 and ll<162 thenif x=100 or x=104 or x=108 thengrbx<="110";end if;end if;--"大"if ll>165 and ll<170 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>169 and ll<174 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>173 and ll<178 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>177 and ll<182 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>181 and ll<186 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>185 and ll<190 thenif x=103 or x=105 thengrbx<="110";end if;end if;if ll>189 and ll<194 thenif x=102 or x=103 or x=106 thengrbx<="110";end if;end if;if ll>193 and ll<198 thenif x=101 or x=102 or x=107 thengrbx<="110";end if;end if;if ll>197 and ll<202 thenif x=100 or x=101 or x=107 or x=108 then grbx<="110";end if;end if;--"学"if ll>205 and ll<210 thenif x=102 or x=104 or x=106 thengrbx<="110";end if;end if;if ll>209 and ll<214 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>213 and ll<218 thenif x=100 or x=108 thengrbx<="110";end if;end if;if ll>217 and ll<222 thenif x=102 or x=103 or x=104 or x=105 or x=106 thengrbx<="110";end if;end if;if ll>221 and ll<226 thenif x=105 thengrbx<="110";end if;end if;if ll>225 and ll<230 thenif x=104 thengrbx<="110";end if;end if;if ll>229 and ll<234 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>233 and ll<238 thenif x=104 thengrbx<="110";end if;end if;if ll>237 and ll<242 thenif x=104 thengrbx<="110";end if;end if;if ll>241 and ll<245 thenif x=103 or x=104 thengrbx<="110";end if;end if;if vs1'event and vs1='1' thenif c=20 thenc<=0;case s1 iswhen 0 =>if x1=120 thens1:=1;elsex1<=x1+1 ; end if;when 1 =>if y1=350 thens1:=2;elsey1<=y1+1; end if;when 2 =>if x1=35 thens1:=3;elsex1<=x1-1; end if;when 3 =>if y1=280 thens1:=0;elsey1<=y1-1; end if;end case;elsec<=c+1;end if;end if;--"HU NAN DA XUE"x2<=x1+1;x3<=x1+2;x4<=x1+3;x5<=x1+5;x7<=x1+7;x8<=x1+8;x9<=x1+9;x10<=x1+10;x11<=x1+11;--y1<=250;y2<=y1+4;y3<=y1+8;y4<=y1+12;y5<=y1+16;y6<=y1+20;if ll>=y1 and ll<y2 thenif x=x1 or x=x5 or x=x7 or x=x8 or x=x11 thengrbx<="101";end if;end if;if ll>=y2 and ll<y3 thenif x=x1 or x=x5 or x=x7 or x=x8 or x=x9 or x=x11 then grbx<="101";end if;end if;if ll>=y3 and ll<y4 thenif x=x1 or x=x2 or x=x3 or x=x4 or x=x5 or x=x7 or x=x9 or x=x11 then grbx<="101";end if;end if;if ll>=y4 and ll<y5 thenif x=x1 or x=x5 or x=x7 or x=x10 or x=x11 thengrbx<="101";end if;end if;if ll>=y5 and ll<y6 thenif x=x1 or x=x5 or x=x7 or x=x10 or x=x11 thengrbx<="101";end if;end if;if ll>100 and 11<150 then --图案设计if ll>121 and ll<126 thenif x>43 and x<57 thengrbx<="100";end if;elsif x=50 thengrbx<="100";end if;end if;if ll>150 and 11<200 thenif ll>171 and ll<176 thenif x>60 and x<74 thengrbx<="010";end if;elsif x=67 thengrbx<="010";end if;end if;if ll>200 and 11<250 then if ll>221 and ll<226 then if x>74 and x<88 then grbx<="001";end if;elsif x=81 thengrbx<="001";end if;end if;end process;fclk<=fs(2);cclk<=cc(4);hs<= not hs1;vs<= not vs1;g<=grb(3);r<=grb(2);b<=grb(1);end a;。
EDA-常见实例源程序代码vhdl(可编辑修改word版)
第4 章用VHDL 程序实现常用逻辑电路4.1组合逻辑电路设计4.1.1基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; --构成与门f2<=a or b; --构成或门f<=not a; --构成非门f3<=a nand b; --构成与非门f4<=a nor b; --构成异或门f5<=not(axor b); --构成异或非门即同门end;4.1.2三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0);dataout: out std_logic_vector(7 downto0));end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' thendataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.33-8 译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')thencase dz iswhen "111"=> y<="01111111";when others=>y<="XXXXXXXX";end case;elseend if;end process;4.1.4优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') thenoutput <= "000" ;elsif (din(6)='0') thenoutput <= "100" ;elsif (din(5)='0') thenoutput <= "010" ;elsif (din(4)='0') thenoutput <= "110" ;elsif (din(3)='0') thenoutput <= "001" ;elsif (din(2)='0') thenoutput <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.57 段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0);led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => led7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" => led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101" => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null;end case;end process;end behave;4.1.6二-十进制BCD 译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0);end;architecture fpq1 of bcdymq isbeginp1: process(din)beginif din<10 thena< =din;b< =0;elsea< =din-10;b< =1;end if;end process p1;end;4.1.7多位加（减）法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3);c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);end if;end process ;end ;4.2时序逻辑电路设计4.2.1触发器RS 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity rsff isport(r,s,clk:in std_logic;q,qb:buffer std_logic);end rsff;architecture rsff_art of rsff issignal q_s,qb_s:std_logic;beginprocess(clk,r,s)beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') thenq_s <= '1' ;qb_s <= '0' ;elsif (s='0' and r='0') thenq_s <= q_s;qb_s <= qb_s;end if;end if;q_s <= q_s;qb_s <= qb_s;end process;end rsff_art;同步复位D 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity syndff isport(d,clk,reset:in std_logic;q,qb:out std_logic);end syndff;architecture dff_art of syndff isbeginprocess(clk)beginif (clk'event and clk='1') thenif (reset='0') thenq<='0';qb<='1';elseq<=d;qb<=not q;end if;end if;end process;end dff_art;JK 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity asynjkff isport(j,k,clk,set.reset:in std_logic;q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff issingal q_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif (set='0' and reset='1' ) thenq_s<='1';qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') thenif (j='0' and k='1' ) thenq_s<='0';qb_s<='1';elsif (j='1' and k='0' ) thenq_s<='1';qb_s<='0';elsif (j='1' and k='1' ) thenq_s<=not q_s;qb_s<=not qb_s;end if;end if;q<= q_s;qb<= qb_s;end process;end jkff_art;T 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic;q: out std_logic);end;architecture tff_art of tff issignal q_temp: std_logic;beginp1:process(clk)beginif rising_edge(clk) thenif t='1' then --当T=1 时T 触发器具有2 分频的功能q_temp<=not q_temp;elseq_temp<=q_temp;end if;end if;q<=q_temp;end process;q<=q_temp;end tff_art;4.2.2计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0);beginprocess(clk)beginif (clk'event and clk = '1') thenq1<=q1+1;end if;end process;q<=q1;end behave;一般计数器设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport( clk,rst,en,updown: in std_logic;cq: out std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbeginprocess(clk,rst,en,updown)variable cqi:std_logic_vector(3 downto 0);beginif rst='1' thencqi:=(others=>'0'); --计数器异步复位elsif (clk'event and clk = '1') then --检测时钟上升沿if en='1'then --检测是否允许计数（同步使能）if updown='0'thenif cqi<9 thencqi:=cqi+1; --允许计数,检测是否小于9elsecqi:=(others=>'0'); --大于9，计数值清零end if;elseif cqi>0 thencqi:=cqi-1; --检测是否大于0elsecqi:=(others=>'1'); ---否则，计数值置1end if;end if;end if;end if;cq<=cqi; --将计数值向端口输出end process;end behave;4.2.3分频器library ieee;use std_logic_1164.all;use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0);fout: out std_logic);end;architecture one of dvf issignal full: std_logic;beginp_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);beginif clk'event and clk='1'then --检测时钟上升沿if cnt8='''' thencnt8:=d; --当CNT8 计数计满时，输入数据D 被同步预置给计数器CNT8full<='1'; --同时使溢出标志信号FULL 输出为高电平elsecnt8:=cnt8+1; --否则继续作加1 计数full<='0'; --且输出溢出标志信号FULL 为低电平end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2; --如果溢出标志信号FULL 为高电平，T 触发器输出取反if cnt2='1'thenfout<='1';elsefout<='0';end if;end if;end process p_div;end;4.2.4移位寄存器library ieee;use ieee.std_logic_1164.all;entity shift isport(clk,c0: in std_logic; --时钟和进位输入md: in std_logic_vector(2 downto 0); --移位模式控制字d:in std_logic_vector(7 downto 0); --待加载移位的数据qb:out std_logic_vector(7 downto 0); --移位数据输出cn: outstd_logic); --进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0);signal cy: std_logic;beginprocess(clk,md,c0)beginif clk'event and clk='1' thencase md iswhen "001" => reg (0) <= c0 ;reg (7 downto 1) <= reg (6 downto 0);cy <= reg (7); --带进位循环左移when "010" => reg (0) <= reg (7);reg (7 downto 1) <= reg (6 downto 0); --自循环左移when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); --自循环右移when "100" => reg (7) <= C0 ;reg (6 downto 0) <= reg (7 downto 1);cy <= reg (0); --带进位循环右移when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数when others => reg<= reg ; cy<= cy ; --保持end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出end behav;4.3状态机逻辑电路设计4.3.1一般状态机设计library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1);comb_outputs : out integer range 0 to 15 );end s_machine;architecture behv of s_machine istype fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型beginreg: process(reset,clk) --主控时序进程beginif reset = '1' thencurrent_state <= s0; --检测异步复位信号elsif clk='1' and clk'event thencurrent_state <= next_state;end if;end process;com:process(current_state, state_inputs) --主控组合进程begincase current_state iswhen s0 => comb_outputs<= 5;if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8;if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12;if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when s3 => comb_outputs <= 14;if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2状态机的应用library ieee;use ieee.std_logic_1164.all;entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s0;when others => state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0';led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0';when s2=> led1<='0';led2<='1';led3<='0';when s3=> led1<='0';led2<='0';led3<='1';when s4=> led1<='0';led2<='0';led3<='1';when s5=> led1<='0';led2<='0';led3<='1';when others => null;end case;end if;end process p2;end ;第6 章EDA 仿真技术应用实例6.1 带使能和片选端的16：4 线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0);ei:in std_logic; --ei:enable inputgs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder isbeginprocess(d)beginif(d(0)='0' and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0' and ei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';'0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';end if;end process;end encoder;6.27 段显示译码器设计译码器设计源代码：library ieee;use ieee.std_logic_1164.all;entity decoder47 isport(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end decoder47;architecture art of decoder47 isbeginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' theny<="1111111"; --检查七段显示管是否正常elsif ibr='0' and a="0000" theny<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3带异步清零端的12 位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder12b isport(clr,cin: in std_logic;a,b: in std_logic_vector(11 downto 0);s: out std_logic_vector(11 downto 0);cout:out std_logic);end adder12b;architecture art of adder12b iscomponent adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8),s=>s(11 downto 8),cout=>cout);end art;6.4带异步清零/置位端的JK 触发器设计带异步清零/置位端的JK 触发器源程序如下：library ieee;use ieee.std_logic_1164.all;entity jkff_logic isport(j,k,clk,clr,set:in std_logic;q:out std_logic);end jkff_logic;architecture art of jkff_logic issignal q_s:std_logic;beginprocess(clk,clr,set,j,k)beginif set='0' thenq_s<='1'; --异步置位elsif clr='1' thenq<='0'; --异步复位elsif clk'event and clk='1' thenif (j='0') and (k='1') thenq_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') thenq_s<=not q_s;end if;end if;q<=q_s;end process;end art;6.5 4 位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b isport(d: in std_logic;ena: in std_logic; --使能端q: out std_logic);end latch1b;architecture art of latch1b isbeginprocess(d,ena)beginif ena='1' thenq<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package iscomponent latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component;end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begingetlatch:for n in 0 to 3 generate --用for_generate 语句循环例化4 个1 位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";end one;6.632 进制多样型计数器设计（1）32 进制同步加法计数器源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr,)beginif clr='1'thend1<=(others=>'0');d0<="0000"; --同步清零elsif clk'event and clk='1' thenif(d1=3 and d0=1)thend1<="0000";d0<="0000"; --计数到32 时清零elsif(d0=1) thend0<="0000";d1<=d1+1;elsed0<=d0+1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（2）32 进制同步减法计数器源程序32 进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr)beginif clr='1' thend1<="0000";d0<="0000"; --异步清零elsif clk'event and clk='1' thenif(d1=0 and d0=0) thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;32 进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic; --s=1 加法计数，s=0 减法计数dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_reversible issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr,s)beginif clr='1'thend1<="0000";d0<="0000"; --异步清零elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000"; --计数到31 时清零elsif(d0=1) thend0<="0000";d1<=d1+1;else d0<=d0+1;end if;elsif s='0' thenif(d1=0 and d0=0)thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（4）32 进制异步加法计数器源程序32 进制异步加法计数器源程序如下：①子模块D 触发器源程序设计。
vhdl 四输入表决器 二位二进制乘法器 一位二进制全减器等源代码及仿真波形
将8421BCD转换为余3码源代码：Library ieee;Use ieee.std_logic_1164.all;Entity bcd isPort(a:in std_logic_vector(3 downto 0);y:out std_logic_vector(3 downto 0));End;Architecture rtl of bcd isBeginProcess(a)BeginCase a isWhen"0000"=>y<="0011";When"0001"=>y<="0100";When"0010"=>y<="0101";When"0011"=>y<="0110";When"0100"=>y<="0111";When"0101"=>y<="1000";When"0110"=>y<="1001";When"0111"=>y<="1010";When"1000"=>y<="1011";When"1001"=>y<="1100";When others=>y<="ZZZZ";End case;End process;End;仿真图形：（仿真结果均有延时，大约20ns）四输入表决器源代码：Library ieee;Use ieee.std_logic_1164.all;Entity bjq isPort(i:in std_logic_vector(3 downto 0);f:out std_logic);End;Architecture nm2 of bjq isBeginProcess(i)Begincase i isWhen"0000"=>f<='0';When"0001"=>f<='0';When"0010"=>f<='0';When"0011"=>f<='0';When"0100"=>f<='0';When"0101"=>f<='0';When"0110"=>f<='0';When"0111"=>f<='1';When"1000"=>f<='0';When"1001"=>f<='0';When"1010"=>f<='0';When"1011"=>f<='1';When"1100"=>f<='0';When"1101"=>f<='1';When"1110"=>f<='1';When"1111"=>f<='1';When others=>f<='Z';End case;End process;End;仿真图形：2位二进制相乘电路源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity multi isport(A,B:in std_logic_vector(1 downto 0);F:out std_logic_vector(3 downto 0));end;architecture bhv of multi isbeginprocess(A,B)beginif(A="01" and B="01" )thenF<="0001";elsif(A="01" and B="10")thenF<="0010";elsif(A="01" and B="11")thenF<="0011";elsif(A="10" and B="01")thenF<="0010";elsif(A="10" and B="10")thenF<="0100";elsif(A="10" and B="11")thenF<="0110";elsif(A="11" and B="01")thenF<="0011";elsif(A="11" and B="10")thenF<="0110";elsif(A="11" and B="11")thenF<="1001";elseF<="0000";end if;end process;end;仿真图形：一位二进制全减器源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity subtracter isport(A,B,Ci:in std_logic;F,Co:out std_logic);end;architecture bhv of subtracter isbeginprocess(A,B,Ci)beginif(A='0' and B='0' and Ci='0')thenF<='0';Co<='0';elsif(A='0' and B='0' and Ci='1')thenF<='1';Co<='1';elsif(A='0' and B='1' and Ci='0')thenF<='1';Co<='1';elsif(A='0' and B='1' and Ci='1')thenF<='0';Co<='1';elsif(A='1' and B='0' and Ci='0')thenF<='1';Co<='0';elsif(A='1' and B='0' and Ci='1')thenF<='0';Co<='0';elsif(A='1' and B='1' and Ci='0')thenF<='0';Co<='0';elseF<='1';Co<='1';end if;end process;end;仿真图形：开关控制电路源代码：Library ieee;Use ieee.std_logic_1164.all;Entity switch_control isPort(a,b,c:in std_logic;y:out std_logic);End;Architecture nm5 of switch_control isBeginProcess(a,b,c);V ariable comb:std_logic_vector(2 downto 0);BeginComb:=a&b&c;Case comb isWhen"000"=>y<='0';When"001"=>y<='1';When"011"=>y<='0';When"010"=>y<='1';When"110"=>y<='0';When"111"=>y<='1';When"101"=>y<='0';When"100"=>y<='1';When others=>y<='X';End case;End process;End;仿真图形：。
EDA 常见实例源程序代码vhdl
第4章用VHDL程序实现常用逻辑电路4.1 组合逻辑电路设计4.1.1 基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; --构成与门f2<=a or b; --构成或门f<=not a; --构成非门f3<=a nand b; --构成与非门f4<=a nor b; --构成异或门f5<=not(a xor b); --构成异或非门即同门end;4.1.2 三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0);dataout: out std_logic_vector(7 downto0));end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' thendataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.3 3-8译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')thencase dz iswhen "000"=> y<="11111110";when "001"=> y<="11111101";when "010"=> y<="11111011";when "011"=> y<="11110111";when "100"=> y<="11101111";when "101"=> y<="11011111";when "110"=> y<="10111111";when "111"=> y<="01111111";when others=>y<="XXXXXXXX";end case;elsey<="11111111";end if;end process;4.1.4 优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') thenoutput <= "000" ;elsif (din(6)='0') thenoutput <= "100" ;elsif (din(5)='0') thenoutput <= "010" ;elsif (din(4)='0') thenoutput <= "110" ;elsif (din(3)='0') thenoutput <= "001" ;elsif (din(2)='0') thenoutput <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.5 7段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0);led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => led7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" => led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101" => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null;end case;end process;end behave;4.1.6二-十进制BCD译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0);end;architecture fpq1 of bcdymq isbeginp1: process(din)beginif din<10 thena< =din;b< =0;elsea< =din-10;end if;end process p1;end;4.1.7 多位加（减）法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3);c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);end if;end process ;end ;4.2 时序逻辑电路设计4.2.1 触发器RS触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity rsff isport(r,s,clk:in std_logic;q,qb:buffer std_logic);end rsff;architecture rsff_art of rsff issignal q_s,qb_s:std_logic;beginprocess(clk,r,s)beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') thenq_s <= '1' ;qb_s <= '0' ;elsif (s='0' and r='0') thenq_s <= q_s;qb_s <= qb_s;end if;q_s <= q_s;qb_s <= qb_s;end process;end rsff_art;同步复位D触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity syndff isport(d,clk,reset:in std_logic;q,qb:out std_logic);end syndff;architecture dff_art of syndff isbeginprocess(clk)beginif (clk'event and clk='1') thenif (reset='0') thenq<='0';qb<='1';elseq<=d;qb<=not q;end if;end if;end process;end dff_art;JK触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity asynjkff isport(j,k,clk,set.reset:in std_logic;q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff issingal q_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif (set='0' and reset='1' ) thenq_s<='1';qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') thenif (j='0' and k='1' ) thenq_s<='0';qb_s<='1';elsif (j='1' and k='0' ) thenq_s<='1';qb_s<='0';elsif (j='1' and k='1' ) thenq_s<=not q_s;qb_s<=not qb_s;end if;end if;q<= q_s;qb<= qb_s;end process;end jkff_art;T触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic;q: out std_logic);end;architecture tff_art of tff issignal q_temp: std_logic;beginp1:process(clk)beginif rising_edge(clk) thenif t='1' then --当T=1时T触发器具有2分频的功能q_temp<=not q_temp;elseq_temp<=q_temp;end if;end if;q<=q_temp;end process;q<=q_temp;end tff_art;4.2.2计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0);beginprocess(clk)beginif (clk'event and clk = '1') thenq1<=q1+1;end if;end process;q<=q1;一般计数器设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport( clk,rst,en,updown: in std_logic;cq: out std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbeginprocess(clk,rst,en,updown)variable cqi:std_logic_vector(3 downto 0);beginif rst='1' thencqi:=(others=>'0'); --计数器异步复位elsif (clk'event and clk = '1') then --检测时钟上升沿if en='1'then --检测是否允许计数（同步使能）if updown='0'thenif cqi<9 thencqi:=cqi+1; --允许计数,检测是否小于9elsecqi:=(others=>'0'); --大于9，计数值清零end if;elseif cqi>0 thencqi:=cqi-1; --检测是否大于0elsecqi:=(others=>'1'); ---否则，计数值置1end if;end if;end if;end if;cq<=cqi; --将计数值向端口输出end process;end behave;4.2.3 分频器library ieee;use std_logic_1164.all;use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0);fout: out std_logic);end;architecture one of dvf issignal full: std_logic;beginp_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);if clk'event and clk='1'then --检测时钟上升沿if cnt8=''11111111'' thencnt8:=d; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8full<='1';--同时使溢出标志信号FULL输出为高电平elsecnt8:=cnt8+1;--否则继续作加1计数full<='0'; --且输出溢出标志信号FULL为低电平end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2; --如果溢出标志信号FULL为高电平，T触发器输出取反if cnt2='1'thenfout<='1';elsefout<='0';end if;end if;end process p_div;end;4.2.4 移位寄存器library ieee;use ieee.std_logic_1164.all;entity shift isport(clk,c0: in std_logic;--时钟和进位输入md: in std_logic_vector(2 downto 0);--移位模式控制字d: in std_logic_vector(7 downto 0);--待加载移位的数据qb: out std_logic_vector(7 downto 0);--移位数据输出cn: out std_logic);--进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0);signal cy: std_logic;beginprocess(clk,md,c0)beginif clk'event and clk='1' thencase md iswhen "001" => reg (0) <= c0 ;reg (7 downto 1) <= reg (6 downto 0);cy <= reg (7); --带进位循环左移when "010" => reg (0) <= reg (7);reg (7 downto 1) <= reg (6 downto 0); --自循环左移when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); --自循环右移when "100" => reg (7) <= C0 ;reg (6 downto 0) <= reg (7 downto 1);cy <= reg (0); --带进位循环右移when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数when others => reg<= reg ; cy<= cy ; --保持end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出end behav;4.3 状态机逻辑电路设计4.3.1 一般状态机设计library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1);comb_outputs : out integer range 0 to 15 );end s_machine;architecture behv of s_machine istype fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型beginreg: process(reset,clk) --主控时序进程beginif reset = '1' thencurrent_state <= s0; --检测异步复位信号elsif clk='1' and clk'event thencurrent_state <= next_state;end if;end process;com:process(current_state, state_inputs) --主控组合进程begincase current_state iswhen s0 => comb_outputs<= 5;if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8;if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12;if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when s3 => comb_outputs <= 14;if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2状态机的应用library ieee;use ieee.std_logic_1164.all;entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s0;when others => state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0';led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0';when s2=> led1<='0';led2<='1';led3<='0';when s3=> led1<='0';led2<='0';led3<='1';when s4=> led1<='0';led2<='0';led3<='1';when s5=> led1<='0';led2<='0';led3<='1';when others => null;end case;end if;end process p2;end ;第6章EDA仿真技术应用实例6.1带使能和片选端的16：4线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0);ei:in std_logic; --ei:enable inputgs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder isbeginprocess(d)beginif(d(0)='0' and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0' and ei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';elsif(d="11111111" and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';end if;end process;end encoder;6.27段显示译码器设计译码器设计源代码：library ieee;use ieee.std_logic_1164.all;entity decoder47 isport(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end decoder47;architecture art of decoder47 isbeginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' theny<="1111111"; --检查七段显示管是否正常elsif ibr='0' and a="0000" theny<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3带异步清零端的12位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder12b isport(clr,cin: in std_logic;a,b: in std_logic_vector(11 downto 0);s: out std_logic_vector(11 downto 0);cout:out std_logic);end adder12b;architecture art of adder12b iscomponent adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8),s=>s(11 downto 8),cout=>cout);end art;6.4 带异步清零/置位端的JK触发器设计带异步清零/置位端的JK触发器源程序如下：library ieee;use ieee.std_logic_1164.all;entity jkff_logic isport(j,k,clk,clr,set:in std_logic;q:out std_logic);end jkff_logic;architecture art of jkff_logic issignal q_s:std_logic;beginprocess(clk,clr,set,j,k)beginif set='0' thenq_s<='1'; --异步置位elsif clr='1' thenq<='0'; --异步复位elsif clk'event and clk='1' thenif (j='0') and (k='1') thenq_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') thenq_s<=not q_s;end if;end if;q<=q_s;end process;end art;6.5 4位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b isport(d: in std_logic;ena: in std_logic; --使能端q: out std_logic);end latch1b;architecture art of latch1b isbeginprocess(d,ena)beginif ena='1' thenq<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package iscomponent latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component;end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begingetlatch:for n in 0 to 3 generate --用for_generate语句循环例化4个1位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";end one;6.6 32进制多样型计数器设计（1）32进制同步加法计数器源程序32进制同步加法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,)beginif clr='1'thend1<=(others=>'0');d0<="0000"; --同步清零elsif clk'event and clk='1' thenif(d1=3 and d0=1)thend1<="0000";d0<="0000"; --计数到32时清零elsif(d0=1) thend0<="0000";d1<=d1+1;elsed0<=d0+1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（2）32进制同步减法计数器源程序32进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr)beginif clr='1' thend1<="0000";d0<="0000"; --异步清零elsif clk'event and clk='1' thenif(d1=0 and d0=0) thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（3）32进制同步可逆计数器源程序32进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic; --s=1加法计数，s=0减法计数dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_reversible issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,s)beginif clr='1'thend1<="0000";d0<="0000"; --异步清零elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000"; --计数到31时清零elsif(d0=1) thend0<="0000";d1<=d1+1;else d0<=d0+1;end if;elsif s='0' thenif(d1=0 and d0=0)thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（4）32进制异步加法计数器源程序32进制异步加法计数器源程序如下：①子模块D触发器源程序设计。
VHDL语言编写数字钟源代码
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity clock isport (clk,clr,a,c,e,f,g:in std_logic;led_sel:out std_logic_vector( 2 downto 0);led:out std_logic_vector( 0 to 6);p:in std_logic_vector( 3 downto 0);b:in std_logic_vector(1 downto 0);d:out std_logic );end entity clock;architecture bhv of clock issignal m: integer range 0 to 999;signal hou1,hou0,min1,min0,sec1,sec0,s2:std_logic_vector(3 downto 0);signal rhou1,rhou0,rmin1,rmin0,rsec1,rsec0:std_logic_vector(3 downto 0);signal s1: std_logic_vector(2 downto 0);signal clk1,clk2,d1,d2:std_logic;signal n : integer range 0 to 1;beginp1:process(clk) --二分频beginif (rising_edge(clk)) thenif n=1 then n<=0;clk2<='1';else n<=n+1; clk2<='0';end if;end if ;end process;p2:process(clk)beginif (rising_edge(clk)) thenif m=999 then m<=0;clk1<='1';else m<=m+1; clk1<='0';end if;end if ;end process P2;p3: process(clk1,clr) ---时间设置beginif (clr='1') then sec0<="0000";sec1<="0000";min0<="0000";min1<="0000";hou0<="0000";hou1<="0000";elsif rising_edge(clk1) thenif a='1' then --校时if b="00" then hou1<=p;elsif b="01" then hou0<=p;elsif b="10" then min1<=p;elsif b="11" then min0<=p;end if;end if;if sec0>="1001" thensec0<="0000";if sec1>="0101" thensec1<="0000";if min0>="1001" thenmin0<="0000";if min1>="0101" thenmin1<="0000";if g='0'thenif hou1<"0010" thenif hou0="1001" thenhou0<="0000";hou1<=hou1+1 ;else hou0<=hou0+1;elsif hou1="0010" and hou0="0011" thenhou1<="0000";hou0<="0000";else hou0<=hou0+1;end if ;end if;if g='1'thenif hou1<"0001" thenif hou0="1001" thenhou0<="0000";hou1<=hou1+1 ;else hou0<=hou0+1;end if;elsif hou1="0001" and hou0="0001" thenhou1<="0000";hou0<="0000";else hou0<=hou0+1;end if ;end if;else min1<=min1+1;end if;else min0<=min0+1;else sec1<=sec1+1;end if;else sec0<=sec0+1;end if;end if ;end process P3;p4:process(clk) --数码管选通beginif(rising_edge (clk)) thenif s1="111" thens1<="000";else s1<=s1+1;end if;end if;-- led_sel<=s1;end process;p5:process(s1,f) ---闹铃显示beginif f='0'thencase s1 iswhen "000"=>s2<=sec0;led_sel<="000";when "001"=>s2<=sec1;led_sel<="001";when "010"=>s2<=min0;led_sel<="010";when "011"=>s2<=min1;led_sel<="011";when "100"=>s2<=hou0;led_sel<="100";when "101"=>s2<=hou1;led_sel<="101";when others=>null;end case;elsif f='1' thencase s1 iswhen "010"=>s2<=rmin0;led_sel<="010";when "011"=>s2<=rmin1;led_sel<="011";when "100"=>s2<=rhou0;led_sel<="100";when "101"=>s2<=rhou1;led_sel<="101";when others=>null;end case;end if;end process;p6:process(s2) --七段译码器beginif(s1<6) thencase s2 iswhen "0000"=>led<="0111111"; when "0001"=>led<="0000110"; when "0010"=>led<="1011011"; when "0011"=>led<="1001111"; when "0100"=>led<="1100110"; when "0101"=>led<="1101101"; when "0110"=>led<="1111101"; when "0111"=>led<="0000111"; when "1000"=>led<="1111111"; when "1001"=>led<="1101111"; when others=>null;end case ;else led<="0000000";end if;end process;p7:process(clk1,c) --整点报时beginif (rising_edge(clk))thenif c='1' thenif (min1="0101" and min0="1001" and sec1="0101") then if(sec0="0000"or sec0="0010" or sec0="0100" orsec0="0110" or sec0="1000")thend1<='1'and clk2;else d1<='0';end if;elsif (min1="0000" and min0="0000" and sec0="0000" andsec1="0000") thend1<='1';else d1<='0';end if ;end if ;end if ;end process;p8:process(clk,e) ---闹铃设置beginif (rising_edge(clk))thenif e='1' thenif b="000"then rhou1<=p;elsif b="001"then rhou0<=p;elsif b="010"then rmin1<=p;elsif b="011"then rmin0<=p;end if;end if;end if;end process;p9:process(clk) ---闹铃比较beginif(rising_edge(clk))thenif e='1'thenif(rhou1=hou1 and rhou0=hou0 and rmin1=min1 and rmin0=min0)then if(sec0="0001"or sec0="0010" or sec0="0011" orsec0="0011" or sec0="0100" )thend2<='1'and clk2;else d2<='0';end if;else d2<='0';end if;end if;end if;end process;d<=d1 or d2;end architecture bhv;。
数字电路实验 电子节拍器 VHDL源代码
八、源代码及注释--电子节拍器--分频器组模块dividers源代码--分频器组模块通过对50MHz的外部时钟进行分频，--产生其他模块所需的各种时钟频率并输出，--有60Hz、5000Hz、3000Hz、1500Hz、1000Hz，分别用5个进程实现。
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dividers is --定义实体dividersport(clk : in std_logic; --外部时钟输入clk_out60: out std_logic; --60Hz频率输出clk_out5000 : out std_logic; --5000Hz频率输出clk_out3000 : out std_logic; --3000Hz频率输出clk_out1500 : out std_logic; --1500Hz频率输出clk_out1000 : out std_logic); --1000Hz频率输出end dividers;architecture div of dividers issignal tmp5000 : integer range 0 to 4999; --分频得5000hz 的计数器大小signal tmp3000 : integer range 0 to 8332; --3000hz 3x10^9=50x10^6x60 use 3000hz signal tmp1500 : integer range 0 to 16665; --1500hzsignal tmp1000 : integer range 0 to 49999; --1000hzsignal tmp60 : integer range 0 to 416666; --60hzsignal clktmp5000 : std_logic; --分频得5000hz 的时钟信号signal clktmp3000 : std_logic;signal clktmp1500 : std_logic;signal clktmp1000 : std_logic;signal clktmp60 : std_logic;beginp5000: process(clk) --分频得5000hz 的分频器进程beginif clk'event and clk='1' then --对50MHz进行10000分频得5000hz 的频率if tmp5000=4999 then --达到5000hz 的计数器大小时归零tmp5000<=0;clktmp5000<=not clktmp5000; --5000hz 的时钟信号翻转一次elsetmp5000<=tmp5000+1; ----未达到5000hz 的计数器模值时计数器加一end if;end if;end process p5000; --分频得5000hz 的分频器进程结束p1500: process(clk) --以下各分频器原理同上beginif clk'event and clk='1' thenif tmp1500=16665 thentmp1500<=0;clktmp1500<=not clktmp1500;elsetmp1500<=tmp1500+1;end if;end if;end process p1500;p1000: process(clk)beginif clk'event and clk='1' thenif tmp1000=49999 thentmp1000<=0;clktmp1000<=not clktmp1000;elsetmp1000<=tmp1000+1;end if;end if;end process p1000;p3000: process(clk)beginif clk'event and clk='1' thenif tmp3000=8332 thentmp3000<=0;clktmp3000<=not clktmp3000;elsetmp3000<=tmp3000+1;end if;end if;end process p3000;p60: process(clk)beginif clk'event and clk='1' thenif tmp60=416666 thentmp60<=0;clktmp60<=not clktmp60;elsetmp60<=tmp60+1;end if;end if;end process p60;clk_out5000 <= clktmp5000; --输出分频得到的5000hz 频率clk_out3000 <= clktmp3000;clk_out1500 <= clktmp1500;clk_out1000 <= clktmp1000;clk_out60 <= clktmp60;end div; ———————————————————————————————————————--电子节拍器--速度设置模块set_speed源代码--速度设置模块实现速度在40至120内连续可调library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity set_speed isport(clk60 : in std_logic; --分频器60hz时钟输入vadd : in std_logic; --加按键输入vdec : in std_logic; --减按键输入clear : in std_logic; --置位键输入beat_v : out std_logic_vector(6 downto 0); --速度输出v_out0 : out std_logic_vector(3 downto 0); --速度个位二进制输出（对应0号数码管）v_out1 : out std_logic_vector(3 downto 0); --速度十位二进制输出（对应1号数码管）v_out2 : out std_logic_vector(3 downto 0)); --速度百位二进制输出（对应2号数码管）end set_speed;architecture set of set_speed issignal cn : integer range 40 to 120; --速度记录信号signal change_a : std_logic; --加按键输入按下记录信号signal change_d : std_logic; --减按键输入按下记录信号signal count_add : integer:=0; --加按键输入按下时长记录信号signal count_dec : integer:=0; --减按键输入按下时长记录信号signal a10 : integer range 0 to 99; --速度减去百位的数的记录信号signal a0 : integer range 0 to 9; --速度个位记录信号signal a1 : integer range 0 to 9; --速度十位记录信号signal a2 : integer range 0 to 1; --速度百位记录信号beginprocess(clk60,vadd,vdec)beginif clk60'event and clk60='1' thenif (vadd='1') then --若加键按下change_a<='1'; --加按键输入按下记录信号置1count_add<=count_add+1; --加按键输入按下时长记录信号加1if (count_add>60 and cn<=115) then --加按键输入按下时长记录信号大于60--即加按键按下时长大于1s（长按）--若速度小于115cn<=cn+5; --则速度连加5count_add<=count_add-60; --同时加按键输入按下时长记录信号减60 elsif (count_add>60 and cn>115) then --若速度大于115cn<=120; --速度只能增加到设置的上限120count_add<=0; --加按键输入按下时长记录信号置0change_a<='0'; --加按键输入按下记录信号置0end if;elsif (vdec='1') then --原理同加按键change_d<='1';count_dec<=count_dec+1;if (count_dec>60 and cn>=45) thencn<=cn-5;count_dec<=count_dec-60;elsif (count_dec>60 and cn<45) thencn<=40;count_dec<=0;change_d<='0';end if;elsif(vadd='0' and vdec='0') then --检测到无键按下时if (change_a='1' and count_add<60 and cn<120 ) then --若加键按下--且加按键输入按下时长记录信号小于60（短按）--且速度小于120cn<=cn+1; --则速度加1count_add<=0;change_a<='0';elsif (change_a='1' and count_add>=60 ) then --若加键长按count_add<=0;change_a<='0';if (cn<=115 ) then --原理同上cn<=cn+5;elsif (cn>115 ) thencn<=120;end if;elsif (change_d='1' and count_dec<60 and cn>40 ) then --原理同加按键cn<=cn-1;count_dec<=0;change_d<='0';elsif (change_d='1' and count_dec>=60 ) thencount_dec<=0;change_d<='0';if (cn>=45 ) thencn<=cn-5;elsif (cn<45 ) thencn<=40;end if;end if;end if;if clear ='1' then --实现置位功能cn<=80;count_add<=0;count_dec<=0;end if;if cn>=100 thena2<=1;a10<=cn-100;elsea2<=0;a10<=cn;end if;a1<= a10/10;a0<= a10-a1*10;end if;end process;v_out2<=conv_std_logic_vector(a2,4); --将速度的百位（十进制）转换为二进制后输出v_out1<=conv_std_logic_vector(a1,4);v_out0<=conv_std_logic_vector(a0,4);beat_v<=conv_std_logic_vector(cn,7); --将速度（十进制）转换为二进制后输出end set;--电子节拍器--节拍型选择模块set_rhythm源代码--节拍型选择模块可设置的节拍有1/4、2/4、3/4、4/4、3/8、6/8可选，--通过sel 按键选择，送到2个数码管显示，并把选好的节拍型输出到相关模块。
VHDL代码
VHDL代码[例1.4.26] 2输入与门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY and2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END and2; ARCHITECTURE one OF and2 IS BEGINy<= a and b;END one;[例2.5.1] 2输入与非门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END nand2; ARCHITECTURE one OF nand2 IS BEGINy<= a nand b;END one;[例2.5.2] 2输入或门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END or2;ARCHITECTURE one OF or2 IS BEGINy<= a or b;END one;[例2.5.3]非门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY hnot ISPORT(a : IN STD_LOGIC;y: OUT STD_LOGIC);END hnot; ARCHITECTURE one OF hnot IS BEGINy<= not a;END one;[例2.5.4] 2输入异或门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY xor2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END xor2; ARCHITECTURE one OF xor2 IS BEGINy<= a xor b;END one;[例3.8.1] 3线-8线译码器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY decoder38 ISPORT(a : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decoder38;ARCHITECTURE one OF decoder38 ISBEGINPROCESS (a)BEGINCASE a ISWHEN "000" => y<= "00000001";WHEN "001" => y<= "00000010";WHEN "010" => y<= "00000100";WHEN "011" => y<= "00001000";WHEN "100" => y<= "00010000";WHEN "101" => y<= "00100000";WHEN "110" => y<= "01000000";WHEN "111" => y<= "10000000";WHEN OTHERS =>null ;END CASE;END PROCESS;END one;[例3.8.2] 8线-3线优先编码器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY encoder83 ISPORT( d : IN STD_LOGIC_VECTOR(7 DOWNTO 0); encode: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END encoder83;ARCHITECTURE one OF encoder83 ISBEGINencode <= "111" when d(7) = '1' else "110" when d(6) = '1' else"101" when d(5) = '1' else"100" when d(4) = '1' else"011" when d(3) = '1' else"010" when d(2) = '1' else"001" when d(1) = '1' else"000" when d(0) = '1' ;END one;[例3.8.3] 4选1数据选择器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux41 isPORT (a,b,c,d : IN STD_LOGIC;s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);z : OUT STD_LOGIC);END mux41;ARCHITECTURE one OF mux41 ISBEGINPROCESS (s ,a,b,c,d)BEGINCASE s ISWHEN "00" => z<= a;WHEN "01" => z<= b;WHEN "10" => z<= c;WHEN "11" => z<= d;WHEN OTHERS =>z<= 'x';END CASE;END PROCESS;END one;[例4.8.1] 同步复位D触发器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff isPORT (d,clk,reset : IN STD_LOGIC;q : OUT STD_LOGIC);END d_ff;ARCHITECTURE one OF d_ff IS BEGINPROCESS (clk)BEGINIF clk'EVENT AND clk='1' THENIF reset='1' THENQ<='0';ELSE q<=d;END IF;END IF;END PROCESS;END one;[例4.8.2] 边沿JK 触发器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY jk_ff isPORT (j,k,clk : IN STD_LOGIC;q, qn : OUT STD_LOGIC);END jk_ff;ARCHITECTURE one OF jk_ff IS SIGNAL q_s : STD_LOGIC; BEGINPROCESS (j,k,clk)BEGINIF clk'EVENT AND clk='1' THENIF J='0' AND k='0' THENq_s<= q_s;ELSIF J='0' AND k='1' THENq_s<='0';ELSIF J='1' AND k='0' THENq_s<='1';ELSIF J='1' AND k='1' THENq_s<=NOT q_s;END IF;END IF;END PROCESS;q<=q_s;qn<=not q_s;END one;[例5.6.1] 十进制计数器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count10 isPORT (cp : IN STD_LOGIC;q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END count10;ARCHITECTURE one OF count10 ISSIGNAL count :STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGINPROCESS (cp)BEGINIF cp'EVENT AND cp='1' THENIF count <="1001" THENcount <="0000";ELSE count <= count +1;END IF;END IF;END PROCESS;q<= count;END one;[例5.6.2] 4位基本寄存器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY registerb isPORT (cp,reset : IN STD_LOGIC;data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END registerb;ARCHITECTURE one OF registerb ISBEGINPROCESS (cp)BEGINIF cp'EVENT AND cp='1' THEN IF reset='1' THENq<="0000";ELSEq<= data;END IF;END IF;END PROCESS;END one;。
北邮 VHDL时序逻辑电路设计部分实验VHDL源代码
（写的有点简陋，见谅哈,各位~~）VHDL时序设计逻辑电路设计（一）四位二进制减计数器（摘自网上）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count1 isport(ci:in std_logic; --计数信号reset: in std_logic; --异步复位load: in std_logic; --同步置数clk: in std_logic;d : in std_logic_vector(3 downto 0); --置数值q : buffer std_logic_vector(3 downto 0);co: out std_logic --计数溢出标志);end count1;architecture behave of count1 isbeginprocess(clk,reset)beginif(reset='0') thenq<="0000";elsif(clk'event and clk='1') thenif(load='1') thenq<=d;elsif(ci='1') thenif(q=0) thenq<="1111";co<='1';elseq<=q-1;co<='0';end if;end if;end if;end process;end behave;VHDL时序设计逻辑电路设计（二）（一）带异步复位的4位能自动启动环形计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY HUANXINGJISHU ISPORT(clk,rs:IN STD_LOGIC;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END HUANXINGJISHU;ARCHITECTURE behave OF HUANXINGJISHU ISSIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(rs,clk)BEGINIF rs='0' THEN Q<="0011";ELSIF(clk'event AND clk='1') THENCASE Q ISWHEN"0000"=>Q<="0001";WHEN"0001"=>Q<="0010";WHEN"0010"=>Q<="0100";WHEN"0011"=>Q<="0110";WHEN"0100"=>Q<="1000";WHEN"0101"=>Q<="1010";WHEN"0110"=>Q<="1100";WHEN"0111"=>Q<="1110";WHEN"1000"=>Q<="0001";WHEN"1001"=>Q<="0010";WHEN"1010"=>Q<="0100";WHEN"1011"=>Q<="0110";WHEN"1100"=>Q<="1000";WHEN"1101"=>Q<="1010";WHEN"1110"=>Q<="1100";WHEN"1111"=>Q<="1110";WHEN OTHERS =>Q<="0000";END CASE;END IF;END PROCESS;countout<=Q;END behave;（二）带异步复位的4位能自启动扭形计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY NIUHUAIJISHU ISPORT(clk,rs:IN STD_LOGIC;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END NIUHUAIJISHU ;ARCHITECTURE behave OF NIUHUAIJISHU ISSIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINPROCESS(rs,clk)BEGINIF rs='0' THEN Q<="0100";ELSIF(clk'event AND clk='1') THENCASE Q ISWHEN"0000"=>Q<="0001";WHEN"0001"=>Q<="0011";WHEN"0010"=>Q<="0101";WHEN"0011"=>Q<="0111";WHEN"0100"=>Q<="1001";WHEN"0101"=>Q<="1011";WHEN"0110"=>Q<="1101";WHEN"0111"=>Q<="1111";WHEN"1000"=>Q<="0000";WHEN"1001"=>Q<="0010";WHEN"1010"=>Q<="0101";WHEN"1011"=>Q<="0111";WHEN"1100"=>Q<="1000";WHEN"1101"=>Q<="1010";WHEN"1110"=>Q<="1100";WHEN"1111"=>Q<="1110";WHEN OTHERS =>Q<="0000";END CASE;END IF;END PROCESS;countout<=Q;END behave;VHDL时序逻辑电路设计（三）（一）带控制端的8位二进制寄存器：先生成一VHDL file文件，编译以下底层的D触发器文件：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DCHUFAQI ISPORT (d,clk:IN STD_LOGIC;q:OUT STD_LOGIC);END DCHUFAQI;ARCHITECTURE one OF DCHUFAQI ISBEGINPROCESSBEGINW AIT UNTIL clk='1';q<=d;END PROCESS ;END one;再在同一工程下生成一VHDL文件，源代码如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JICUNQI ISPORT(d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);oe,clk: IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END JICUNQI;ARCHITECTURE struc OF JICUNQI ISCOMPONENT DCHUFAQIPORT(d,clk:IN STD_LOGIC;q: OUT STD_LOGIC);END COMPONENT;SIGNAL temp:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(clk,oe)BEGINIF oe='1' THENq<="ZZZZZZZZ";ELSEq<=temp;END IF;END PROCESS;u0:DCHUFAQI PORT MAP(d(0),clk,temp(0));u1:DCHUFAQI PORT MAP(d(1),clk,temp(1));u2:DCHUFAQI PORT MAP(d(2),clk,temp(2));u3:DCHUFAQI PORT MAP(d(3),clk,temp(3));u4:DCHUFAQI PORT MAP(d(4),clk,temp(4));u5:DCHUFAQI PORT MAP(d(5),clk,temp(5));u6:DCHUFAQI PORT MAP(d(6),clk,temp(6));u7:DCHUFAQI PORT MAP(d(7),clk,temp(7));END struc;（二）带控制端的8位二进制锁存器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SUOCUNQI ISPORT(d:IN STD_LOGIC_VECTOR(7 DOWNTO 0);oe,clk:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END SUOCUNQI;ARCHITECTURE struc OF SUOCUNQI ISSIGNAL temp:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGINPROCESS(clk,oe)BEGINIF oe='0' THENIF clk='1' THENtemp<=d;END IF;ELSEtemp<="ZZZZZZZZ";END IF;q<=temp;END PROCESS;END struc;。
分频器VHDL
分频器的VHDL代码在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。
我们知道，在硬件电路设计中时钟信号是最重要的信号之一。
下面我们介绍分频器的VHDL 描述，在源代码中完成对时钟信号CLK 的 2 分频，4 分频，8 分频，16 分频。
这也是最简单的分频电路，只需要一个计数器即可。
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY clkdiv ISPORT(clk : IN STD_LOGIC;clk_div2 : OUT STD_LOGIC;clk_div4 : OUT STD_LOGIC;clk_div8 : OUT STD_LOGIC;clk_div16 : OUT STD_LOGIC);END clk_div;ARCHITECTURE rtl OF clk_div ISSIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk)BEGINIF (clk"event AND clk=" 1" ) THENIF(count=” 1111” ) THENCount <= (OTHERS =>" 0" );ELSECount <= count +1;END IF ;END IF ;END PROCESS;clk_div2 <= count(0);clk_div4 <= count(1);clk_div8 <= count(2);clk_div16 <= count(3);END rtl;对于分频倍数不是 2 的整数次幂的情况，我们只需要对源代码中的计数器进行一下计数控制就可以了，如下面源代码描述一个对时钟信号进行 6 分频的分频器。
vhdl代码编写
PROCESS
[label:] PROCESS (sensitivity list) [VARIABLE name type [range] [:= initial_value;]] BEGIN (sequential code) END PROCESS [label];
Example:DFF with Asynchronous Reset #1
sel：IN STD_LOGIC_VECTOR (1 DOWNTO 0)； y：OUT STD_LOGIC);
END mux4；
ARCHITECTURE rtl OF mux4 IS BEGIN PROCESS (input，sel) BEGIN IF (sel=“00”) THEN y<= input（0）； ELSIF（sel=“01”）THEN y<= input（1）； ELSIF（sel=“10”）THEN y<= input（2）； ELSE y<= input（3）； END IF;
VARIABLES are also restricted to be used in sequential code only (that is, inside a PROCESS, FUNCTION, or PROCEDURE). Thus, contrary to a SIGNAL, a VARIABLE can never be global, so its value can not be passed out directly.
10 ARCHITECTURE dff OF dff IS 11 BEGIN 12 PROCESS 13 BEGIN 14 WAIT ON rst, clk; 15 IF (rst='1') THEN 16 q <= '0'; 17 ELSIF (clk'EVENT AND clk='1') THEN 18 q <= d; 19 END IF; 20 END PROCESS; 21 END dff; 22 --------------------------------------
ies的.vh编译
ies的.vh编译
首先，要编译VHDL代码，你需要安装一个VHDL编译器。
常见
的VHDL编译器包括ModelSim，Xilinx ISE，Altera Quartus等。
这些编译器通常会将VHDL代码转换为可在FPGA或ASIC芯片上实现
的逻辑网表或者门级网表。
编译VHDL代码的过程通常包括以下步骤：
1. 编写VHDL源代码文件，通常以.vhdl或者.vh为扩展名。
2. 打开VHDL编译器的IDE或者使用命令行工具，导入你的VHDL代码文件。
3. 在IDE中设置编译选项，例如目标FPGA型号、时钟频率等。
4. 执行编译命令，编译器会对VHDL代码进行语法分析、综合
和布线等操作，最终生成一个可在目标芯片上实现的二进制文件。
在编译过程中，编译器会检查代码中的语法错误、逻辑错误和
时序问题，并生成相应的报告。
如果代码中存在错误，编译器会提
示你进行修正。
总的来说，VHDL代码的编译是将高级的硬件描述语言转换为可以在特定硬件平台上实现的低级逻辑表示的过程。
通过编译，我们可以验证代码的正确性，并最终将其加载到FPGA或ASIC芯片上。
希望这个回答能够帮助你更好地理解“ies的.vh编译”。