CDC—综合模版V1.01
DC_MQR_Template 质量报告模板_ENCN Rev1.0
No 2 ：Supplier Name 第二名：供应商名称
931
85.00% 742 80.00%
600
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70.00% 400 65.00%
60.00% 200 106 50 0 0 Tesco Mar-09 Dansk Apr-09 Monorail Apr-09 YanCheng Aug-09 Wuxi Sep-09 Versa Sep-09 Norman Oct-09 50.00% 106 106 117 119 123 55.00%
Delivery Months & Projects
Accumulated Builded Accumulated Nonconformance FPY(shown in %) Log. (FPY(shown in %))
5
QF.QA.1003 Rev1.0
01 Nov 2009 eddie.teh@
Monthly Quality Report – Month Year 月度质量报告 – xxxx 年 xx月
Eddie Teh Confidential Sensitive - not for further distribution 含机密与敏感信息-不得擅自发布
QF.QA.1003 Quality Report 质量报告 Rev 1.0
Total of Nonconformance 不合格总量 : xx deliveries 批货 Product Category 产品类别 ： BK25 / SRM Main Nonconformance area 主要不合格原因 ： xxxxx xxxxxx
DC综合
Set_clock_uncertainty 设置时钟不确定 性
Set_false_path 设置虚假路径
• False Path（伪路径）是指电路中的一些不 需要考虑时序约束的路径，它一般出现在 异步逻辑之中。
DC综合的三个阶段：
• 转译(translation)：
• Translation 是指用HDL语言描述的电路转化为用 GTECH库元件组成的逻辑电路的过程。GTECH是 Synopsys的通用工艺库，它仅表示了逻辑函数的功 能，并没有映射到具体的厂家工艺库，也就是说独 立于厂家工艺的。
• 优化(optimization)和映射(mapping) ：
• 例如我们现在要设置RESET的最大时延为5
Set_max_delay 设置最大延迟
首先选定reset端口,Attribute->Optimization Constraints->Timing Constraints… 点击OK,完成reset的延迟设置. 相对应的脚本命令是: dc_shell> set_max_delay 5 from RESET
• 那么，从输入端口经过路径N到触发器DFF2 的输入端所用的时间＝时钟周期－输入延 时
输出延时
• 那么，数据从触发器DFF3的D端到输出端口 所用的时间＝时钟周期－输出延时
这样，整个设计的路径就全部被约束了。
DC的使用流程
库文件简单说明
• 目标工艺库（Target_library）： • 是指将RTL级的HDL描述到门级时所需的标准单元综合库，它是
Set_wire_load_model设置连线负载模 型
ILI2117DS_v1.01_20150909
ILI2117ILI2117Capacitive Touch ControllerDatasheetVersion: V1.01Release Date: SEP. 09 ,2015ILI TECHNOLOGY CORP.8F, No.38, Taiyuan St., Jhubei City, Hsinchu County 302,Taiwan, R.O.CTel.886-3-5600099; Fax.886-3-5600055List of Chapters1DESCRIPTION (4)2FEATURE (4)3BLOCK DIAGRAM (4)4PIN CONFIGURATION (5)4.1QFN52(6X6MM2,0.4MM PITCH SIZE) (5)4.2P INOUT D ESCRIPTION (6)5ELECTRICAL CHARACTER (7)5.1A BSOLUTE M AXIMUM R ATINGS (7)5.2DC C HARACTERISTICS (7)5.3ESD I NFORMATION (8)5.4AC C HARACTERISTICS OF THE SDA AND SCL ON I2C INTERFACE (8)6PACKAGE INFORMATION (9)6.1QFN526X6X0.6MM3 (9)7APPLICATION (10)7.1R EFERENCE A PPLICATION C IRCUIT (10)7.2P OWER O N R ESET (11)List of FiguresFigure 3-1: ILI2117 Block Diagram (4)Figure 4-1: ILI2117 (QFN52) Package Diagram (5)Figure 5-1: The timing of I2C Interface (8)Figure 6-1: Package Information of QFN52 6x6x0.6mm3 (9)Figure 7-1 : Typical application circuit (10)Figure 7-2: Recommend power on reset timing (11)List of TablesTable 4-1: ILI2117 Pin Assignments (6)Table 4-2: Type Define (6)Table 5-1: Absolute Maximum Ratings (7)Table 5-2: Power Supply (7)Table 5-3: DC Characteristics (T opr = 25℃) (7)Table 5-4: ESD Information (8)Table 5-5: Characteristics of the SDA and SCL bus lines (8)Table 6-1: Package Information (9)1 DescriptionILI2117 is a single chip capacitive touch controller optimized for Mobile, Tablet, Industrial application. It is a SOC with specialized 32-bit MCU and 26 driving and 14 sensing channels. ILI2117 is designed to perform the best performance and supported up to 7‖ application. The 10-point touch is supported and report rate is up to 100Hz.2 Feature●Channel: 40 programmable capacitive driving and sensing channel (max TX/RX = 26/14)●Package: 52 pin, QFN 6x6mm2_0.4P●Cover Lens Thickness : 0.5mm~2mm(by TP structure)●Support TP Structure：GFF、GFM、OGS、on cell●Waterproof◆Water-spray: Robust single-touch drawing without false touch◆1cc: Robust single-touch drawing without false touch◆Puddle: No false touch, normal touch events after wiping out water●Support Smart Wake Up◆Support Letter : o,w,m,e,c,>,<,V,^, double click◆User Define●High Sensitivity◆Support different gloves up to 3.5mm.◆Support Passive Stylus 2phi●Tools◆Sensor Test Tool◆FPC Test Tool◆Tunning Tool3 Block DiagramFigure 3-1: ILI2117 Block Diagram4 Pin Configuration4.1 QFN52 (6x6mm 2, 0.4mm pitch size)Figure 4-1: ILI2117 (QFN52) Package DiagramRX2RX1RX0GNDTX0TX1TX2TX3TX4TX5TX6TX7TX8RX3TX9RX4TX10RX5TX11RX6TX12RX7TX13RX8TX14RX9TX15RX10TX16RX11TX17RX12TX18RX13TX19VDD TX20VGHTX21VDD16GNDINTTXNCSDASCLVDDIORSTNTX25TX24TX23TX224.2 Pinout DescriptionTable 4-1: ILI2117 Pin AssignmentsTable 4-2: Type Define5 Electrical Character5.1 Absolute Maximum RatingsStresses above those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or under any other conditions above those indicated in the operational sections of this specification are not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.Table 5-1: Absolute Maximum Ratings5.2 DC CharacteristicsTable 5-2: Power SupplyTable 5-3: DC Characteristics (T opr = 25℃)b400pF for standard mode and 300pF for fast mode. If C b smaller than 400pF/300pF, I2C circuit can chose higher impedance for saving sink power. The minimum impedance was defined under I d (sink current) of 3mA. All the above condition was defined with internal pull high impendence of 4.7k to 5.3k.*2. The power consumption depends on sensor loading condition.5.3 ESD InformationTable 5-4: ESD Information5.4 AC Characteristics of the SDA and SCL on I2C interfacet fFigure 5-1: The timing of I2C InterfaceTable 5-5: Characteristics of the SDA and SCL bus lines6 Package Information6.1 QFN52 6x6x0.6mm3(Unit: mm)Figure 6-1: Package Information of QFN52 6x6x0.6mm3Table 6-1: Package Information7 Application7.1 Reference Application CircuitFigure 7-1 : Typical application circuitNote:1. SCL and SDA pins have internal pull high 4.7K ohm resistor.7.2 Power On ResetTo avoid the IC operate in the wrong power condition. We recommend RSTN keep low during VDD power on. At the same time RSTN has minimum slew rate requirement for sure that the interface power detection function works well.Figure 7-2: Recommend power on reset timingDocument Revision History。
CDC基本知识
TECHNICAL PAPERCLOCK DOMAIN CROSSINGCLOSING THE LOOP ON CLOCK DOMAIN FUNCTIONAL IMPLEMENTATION PROBLEMSTABLE OF CONTENTS1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2CDC basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 3Structural design for synchronization (s CDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4Data stability (f CDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5 A complete CDC solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 6EDA tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 7Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 8References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12TABLE OF FIGURESFigure 1Single clock domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure 2The CDC path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure 3Metastability basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure 4Two flip-flop synchronizer solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Figure 5Control path and data path synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Figure 6Convergence issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 7Divergent crossover path issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 8Fanout of metastable signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 9Effects of fanout of metastable signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 10Reconvergence and waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 11200MHz signal synced into a 166MHz domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 12Timing-closure–only methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 13Methodology with CDC verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 14f CDC checks and their locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 15Handshake check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 16Encounter Conformal CDC detects structural design issues with synchronization . . . . . . . . . .111OVERVIEWShrinking device sizes and increasingly complex designs have created multimillion-transistor systems running with multiple asynchronous clocks with frequencies as high as multiple gigahertz. SoC systems have multiple interfaces, some using standards with very different clock frequencies. Several modern serial interfaces are inherently asynchronous from the rest of the chip. There is also a trend toward designing major sub-blocks of SoCs to run on independent clocks to ease the problem of clock skew across large chips.Design methodologies have traditionally focused on partition-based implementation and verification. Often these partitions are based on clock domains. The cross-clock domain crossing (CDC) signals pose a unique and challenging issue for verification. Traditional functional simulation is inadequate to verify clock domain crossings. While static timing analysis (STA) is an integral part of the timing closure solution, little attention has been paid to addressing proper clock domain implementation and verification.Existing methods provide an ad hoc partial verification that is manual, time consuming, and error prone.If the sources of potential errors are not addressed and verified early on, designs can end up with functional errors that are only detected late in the design cycle—or even worse, during post-silicon verification. The cost of fixing errors at this stage is enormous. We know of large system houses in which chips are “dead in the water” due to CDC problems.Several errors could be caused by cross-CDC signals:•Structural issues (s CDC):If the data input to a storage element changes too close to a clock edge, the element may go into a metastable state and the output cannot be reliably used. Asynchronous clock domain crossings are particularly prone to metastability failures. To address this issue, the circuit must be designed to “buy time” so the metastable signal can settle to a stable value, typically using synchronizers.After completing the synchronization, the structures beyond the synchronizers still matter. For example, the design must ensure that the synchronized signals do not converge. Reconvergence can create functional errors.•Functional errors (f CDC):Designers must ensure that the stability and functionality on either side of the CDC circuit are handed over properly. Otherwise, there could be loss of signal values for signals passing between clock domains, with data instability in the receiving clock domain.Only automatic formal verification techniques can ensure that multiclock designs are correct prior to tapeout. The CDC verification solution must address this verification challenge, while maximizing overall productivity and effectiveness. The CDC solution needs to cover clock domain analysis and structural and functional verification, addressing both register-transfer–level (RTL) and gate-level verification needs. Utilizing the Cadence®CDC solution enables development teams to reduce the overall verification effort and lessen the risk of costly re-spins due to asynchronous clock domain crossing errors.2CDC BASICSThe design issues and challenges of handling the signal crossing domains will be discussed later in this paper. First, let’s look at some CDC basics.2.1CLOCK DOMAINSA clock domain is defined as that part of the design driven by either a single clock or clocks that have constant phase relationships. A clock and its inverted clock or its derived divide-by-two clocks are considered a clock domain (synchronous). Conversely, domains that have clocks with variable phase and time relationships are considered different clock domains.In Figure 1, the design has a single clock domain because the divCLK is the derived divide-by-two clock of the master clock CLK.In Figure 2, multiple clocks come from different sources. The sections of logic elements driven by these clocks are called clock domains, and the signals that interface between these asynchronous clock domains are called the clock domain crossing (CDC) paths. The DA signal is considered an asynchronous signal into the clock domain —no constant phase and time relationship exists between CLK A and CLK B.Figure 2: The CDC path2.2ASYNCHRONOUS SIGNAL BASICSAsynchronous signals, including CDC signals, have the potential to become metastable.2.2.1MetastabilityThe proper operation of a clocked flip-flop depends on the input being stable for a certain period of time before and after the clock edge. If the setup and hold-time requirements are met, the correct output will appear at a valid output level (either VoL or VoH) at the flip-flop output after a maximum delay of t CO (the clock-to-output delay). However, if these setup and hold-time requirements are not met, the output of the flip-flop may take much longer than t CO to reach a valid logic level. This is called unstable behavior, or metastability.As Figure 3illustrates, if CLK B samples DA while DA is changing (at the rising edge of CLK and falling edge of D), then DB will be metastable.Figure 3: Metastability basicsMetastability cannot be avoided, but a solution for handling the metastable signal enables proper functioning of the design.2.2.2Mean time between failuresThe metastability occurrences can be predicted by using the mean time between failures (MTBF) formula:Where C1and C2are constants that depend on the technology used to build the flip-flop; tMET is the duration of the metastable output; and fclk and fdata are the frequencies of the synchronous clock and the asynchronous input, respectively.3STRUCTURAL DESIGN FOR SYNCHRONIZATION (s CDC)3.1SYNCHRONIZATION (CONTROL PATHS)Designers can use special metastable hardened flops for increasing the MTBF . For example, in Figure 4, a synchronizer flop is used following the signal DB. So, instead of the metastable signal DB being used in the function downstream as in Figure 3, the stable signal DB2 is used in the logic downstream.Figure 4: Two flip-flop synchronizer solution3.2SYNCHRONIZATION (CONTROL AND DATA PATHS)Designs typically have control paths and data paths. As shown in Figure 5, the control signals are usually flop-synchronized while the data paths use the synced-in control signals to synchronize the data path. The data path uses a controlled synchronizer MUX to do the domain crossing. This control MUX is sometimes called D-MUX, MUX synchronizer, or sync MUX. We use the term MUX synchronizer , which is a synonym for MUX synchronization scheme.Figure 5: Control path and data path synchronizationMTBF=e C2*tMETC 1 * fclk * fdataThe MUX synchronizer has a critical requirement for all input in terms of the domains and functionality:•The select input of the MUX comes from the destination domain (domain into which the signal is being synchronized)•One of the MUX inputs is coming from the destination domain—that is, the holding loop•The MUX inputs can be source, destination, or user-specified static signals•The logic between the MUX synchronizer and the destination flop is driven by the destination domain or static signals3.3CONVERGENCE IN THE CROSSOVER PATHClock domain crossover paths are false paths for timing tools; any logic in this path must be carefully crafted and verified, because the logic can cause glitches and create functional errors downstream.In Figure 6, although the two source flops give the pulse at the same time, the propagation delay (T d) in post-layout masks out the pulse. Since it is a false path (ignored by the timing tool), the design techniques should consider these occurrences.3.4DIVERGENCE IN THE CROSSOVERA divergent logic style to multiple synchronization paths runs the risk of causing functional errors. As Figure 7 illustrates, due to the propagation delay and different metastable settling times, the Fsm1_en and Fsm2_en could start at different times. This type of structure should be avoided by fanning out a single FSM enable after synchronization to the two FSMs.3.5DIVERGENCE OF METASTABLE SIGNALSMetastable signals are unstable signals, and circuit designs must be put in place to squelch this behavior. The usual style is to loop back to the generating flop—that is, the MUX loop (as shown in Figure 8).A divergence in the metastable signal can cause functional errors, as seen in Figure 9: DB1 and DB2 came out at two different clock edges as the settling and latching values of these metastable signals to the two flops are at different times.Figure 9: Effects of fanout of metastable signal3.6RECONVERGENCE OF SYNCHRONIZED SIGNALSOnce synchronization is completed, the structures beyond the synchronizers still matter. The design must ensure that the synchronized signals do not converge—reconvergence can create functional errors. In Figure 10, the post-synchronization logic can cause a glitch in the signal DB.Figure 10: Reconvergence and waveform4DATA STABILITY (f CDC)Up to this point, we have discussed the structural issues and styles needed to have proper synchronization across two asynchronous clock domains. The functionality of the holding and latching circuit across the CDC path should ensure the proper transfer of the signal. The holding of the source register and the latching of the destination register across the CDC path must be properly designed. Otherwise, issues such as shown in Figure 11(data loss) affect the proper functioning of the circuit. This problem is prevalent when a fast clocked signal is synced into a slow clocked signal. The functionality should be built into the circuits for such CDC paths.Figure 11: 200MHz signal synced into a 166MHz domain4.1EXAMPLE OF f CDCWhen a signal from a fast clock domain crosses over to a slow clock domain, design aspects must ensure that the signal from the fast clock domain is held long enough to be captured properly by the destination domain. There could also be a scenario in which phase-shifted signals of a slow clock are interacting, and the resulting signal’s clock changes every phase. This situation would not be captured by the destination clock, resulting in loss of data.In Figure 11, a 200MHz signal is being synced into a 166MHz domain. The source signal DA must be held for at least two clocks to ensure a capture edge will always fall in this width. This is not the case in Figure 10, however, which shows a capture once, but not the second time (DB). The capture edge is asynchronous and can arrive at any time of the source signal. If the DA signal were stretched to two cycles, there would definitely be an edge for CLK B to capture the signal.4.2GRAY ENCODINGA problem for multiclock designs is loss of the relationship between signals—either bits of a bus or independent signals—when crossing clock domains, which can cause unpredictable results.For multibit signals such as buses, the usual solution is to use a G ray code when crossing a clock domain boundary. A G ray code ensures that only a single bit changes as the bus counts up or down. This makes it possible to detect whether all bits have been captured together by the receiving clock or if they have been skewed across multiple clock cycles due to metastability or differing delays among the bus bits.For example, in an asynchronous FIFO, the read and write pointers cross over to the write and read clock domains, respectively. These pointers are control signals that are flop-synchronized. The signals are G ray-encoded prior to the crossover.5 A COMPLETE CDC SOLUTIONCurrent methodologies that focus on timing closure run the risk of re-spins and iteration due to the clock domain issues previously discussed. However, timing closure ensures that the violations within a clock domain are fixed, while those between the domains are false paths, that is, unchecked. As part of the verification strategy, the synchronization errors—i.e., between clock domains—should be eliminated at the RTL stage itself. In the timing-closure–only methodology (see Figure 12), these errors are checked during the end stages of the design cycle, i.e., in the gate simulation with SDF backannotation, a static verification tool adds value.A complete CDC solution addresses all the functional aspects of multiclock SoC design verification.The structural checks are done for s CDC issues, and formal analysis is used to validate the f CDC issues.Figure 12: Timing-closure–only methodologyAdding CDC verification in the early design stages verifies and validates the unverified portion of the design (see Figure 13).Figure 13: Methodology with CDC verification5.1CLOCK DOMAIN PARTITIONThe major step in the setup for a CDC check is the proper partitioning of designs into asynchronous domains. Propagation and extraction techniques can aid the user in partitioning. Propagation is the forward flow of the user-defined clock attributes through different design structures. The user can control the forward propagation. Extraction builds the domain partition by starting from the clock pin of each flop and creating different clock trees.Because the possibility exists that more domains could be created than the designer envisioned, a utility should be provided to associate clocks and data pins and ports. The clock domain partitions also depend on constraints in the design for the correct flow of the paths, so there should be a way to constrain the design and declare static signals. Configuration register information should be used in conjunction with the utilities to correctly define the clock domain partitions.5.2CDC PATH RULES AND VALIDATIONOnce the clock domains are properly identified, the CDC paths become apparent. A rule-based technique can then be used and applied to the CDC paths. The rules can specify the synchronization scheme (flop or MUX), the allowable structures in the crossover path and the paths in the synchronizer, and the area of application of the rule. Tools can provide either global or local rules.A CDC path is extracted and the set of user-specified rules is applied. It is either a flop synchronizer, MUX-based synchronization, or user-defined synchronizer module; if any rule passes, this CDC path is validated. The structures in the crossover path and the metastable path are analyzed based on the user-specified rule. The reconvergence of CDC signals should be applied only to the flop-based synchronizers, and analysis should start after the specified flop rule. A rule R1 may specify a three-flop synchronizer from CLK 1 to CLK 2; and another rule (for example, R2) may specify a two-flop synchronizer from CLK 3 to CLK 2. The reconvergence check should start analysis after three flops to data paths from CLK 1 to CLK 2 and two flops to data paths from CLK 3 to CLK 2, and see if the two CDC paths converge.Once the structural analysis has been completed, the formal analysis and techniques can be used to verify the stability of all the signals in the CDC path. This formal analysis checks that the hold logic and the latching logic have correct functionality. For vectors that are flop-synchronized, formal analysis can be used to create a property to ensure that the vector is G ray-encoded.5.3FUNCTIONAL CHECK AND DETAILSAs shown in Figure 14 and Figure 15, the functional check can be broadly classified into five checks:•Source data (SD) stability•Destination data (DD) stability•MUX enable (ME) stability that applies only to MUX schemes•Single-bit (SB) checks that apply only to vectors that are flop-synchronized•Handshake (HS) assertion for the flop-based signalsFigure 14: fCDC checks and their locations5.3.1Source data stabilityThe SD check ensures that the holding logic is functioning correctly; that is, the data is held properly until it is latched by the destination.5.3.2Destination data stabilityIf there is logic in the CDC path, even though the hold logic of each source is stable, the combination and computation could affect the holding at the destination. The DD check ensures that data at the destination is stable until it is latched.5.3.3MUX enable stabilityFor a MUX-based synchronization scheme, when the enable is activated, the data points in the MUX should not change. Hence, the output of the MUX should be stable until the destination domain captures the data.5.3.4Single-bit checkWhen a vector crosses over into an asynchronous domain, the vector is usually G ray-encoded. The single-bit check ensures that this rule is applied to all control vectors, and formally proves that there is one bit change under any given scenario.5.3.5 Handshake checkThe HS check (see Figure 15) looks at two or more CDC paths and the data flow, and checks to see that there is a response to all the transmitted signals. That is, it checks for a transmit-receive protocol. This check involves intense user intervention, because automatic analysis of signals involved in a handshake protocol is not trivial.Figure 15: Handshake check5.4DIAGNOSISFailures should be viewed with a proper schematic viewer that uses color-coding to depict different domains for ease of use. Also, backannotation to the source code helps in debugging and fixing the code. The waveform can be shown for the failures in the functional stability checks.6EDA TOOLSMany EDA tools with different business models are on the market. EDA vendors include Cadence, 0-In, Atrenta, @HDL, Mentor, and Synopsys. Cadence Encounter Conformal CDC capability (part of Encounter Conformal ASIC Equivalence Checker) is one of the leading products in this area. Its strength lies in its quality, flow, ease of diagnosis, and gate-level modeling expertise drawn from Encounter Conformal LEC (Logic Equivalence Checker). Leading SoC design houses are using the product to create complete CDC solutions.6.1ENCOUNTER CONFORMAL CDC CAPABILITIESThe Encounter Conformal CDC verification solution performs the following functions:•Clock domain partition and topology checks–Proper clock tree definition and propagation–Known and unknown generated domains•Structural checks for CDC path validation–Proper implementation of synchronizers to prevent metastability problems–Checks for convergence in the crossover path–Checks for divergence in the crossover–Checks for divergence of metastable signals–Checks for reconvergence of synchronized signals•Functional checks–Proper data stability across clock domain boundaries, for both source data stability and destination data stability–Proper MUX enable stability across clock domain boundaries–Single-bit change (G ray encoding) checks for vectors•Extensive diagnosis capabilities6.2EXAMPLEFigure 16shows how the Encounter Conformal CDC solution detects the structural design issues with synchronization (s CDC), as previously discussed. Encounter Conformal CDC detects a convergence in the crossover to-path (as explained in section 3.3).Figure 16: Encounter Conformal CDC detects structural design issues with synchronization7CONCLUSIONWith a growing number of clocks in today’s SoC designs, increased design complexity, and pressure for first silicon success, all clock and timing issues have become a verification challenge.Existing methods provide an ad hoc partial verification that is time consuming and error prone. Automatic formal verification techniques are needed to ensure that multiclock designs are correct prior to tapeout. The solution must also prevent sources of failures in multiclock designs, such as metastability.A clock domain crossing (CDC) verification solution must address this verification challenge, while maximizing overall productivity and effectiveness. It needs to cover clock domain analysis and structural and functional verification, addressing both RTL and gate-level verification needs. With the Cadence Encounter Conformal CDC solution, development teams can reduce the overall verification effort and the risk of related re-spins.The Encounter Conformal CDC solution includes the following benefits:•Pinpoints problems quickly–Automatic detection of clock domains and crossings–Structural verification of multiple clock domain synchronization–Functional verification for data stability violations•Automates error-prone manual post-static timing analysis process•Reduces risk of clock-related re-spins•Prevents late clock-related iterations in the design cycle8REFERENCESMetastability in Altera Devices.Altera Application Note 42. May 1999.Bahukhandi, Ashirwad. Metastability. Lecture Notes for Advanced Logic Design and Switching Theory. January 2002. Cummings, Clifford E. Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs. SNU G 2001. Haseloff, Eilhard. Metastable Response in 5-V Logic Circuits. Texas Instruments Report. February 1997.Nystrom, Mika, and Alain J. Martin. Crossing the Synchronous-Asynchronous Divide. WCED 2002.Patil, G irish, IFV Division, Cadence Design Systems. Clock Synchronization Issues and Static Verification Techniques. Cadence Technical Conference 2004.Smith, Michael John Sebastian. Application-Specific Integrated Circuits. Addison Wesley Longman, 1997, Chapter 6.4.1. Stein, Mike. Crossing the abyss: asynchronous signals in a synchronous world. EDN design feature. July 24, 2003. Wakerly, John. Digital Design Principles and Practices. Prentice Hall, 2000.Cadence Design Systems, Inc.Corporate Headquarters2655 Seely AvenueSan Jose, CA 95134800.746.6223408.943.1234© 2004 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Conformal are registered trademarks and Encounter is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders.5472B 12/04。
第6讲利用CDC实现绘图程序
6.1.1续
应用程序使用GDI可以对三种类型的图形进行操作： 文本操作、矢量图形操作和光栅图形操作（图像操作）。 (1)文本操作是以逻辑坐标为单位来计算文本的输出位置， 用户可以通过各种GDI函数来作出具有各种效果的文本。 (2)矢量图形指的是利用画点、直线、曲线（折线、贝塞 尔曲线等）、多边形、扇形、矩形等函数所绘制的图形。 (3)光栅图形操作是指以光栅图形函数对以位图形式存储 的数据进行操作，它包括各种位图和图标的输出，其在屏 幕上表现为对若干个行和列的像素操作。光栅图形操作是 直接从内存到显存的拷贝操作，其缺点是需要额外的内存 空间，优点是操作速度快。
从MFC示例开始
利用类向导，生成一个名为MfcExam的标准MFC多文档工程
类视图
资源视图
文件视图
视图区，也叫客户区，对应的类是CMfcExamView，所有有 关视图区的显示，都是在CMfcExamView中的 OnDraw 函数 中完成
6.1 图形绘制的基本知识
6.1.1 图形操作的接口——GDI 6.1.2 图形操作有关的CDC类 6.1.3 CDC的内容
SetBkColor(RGB(255,0,0);
6.2.2续1
2．控制文本的背景色
在设备描述表中有两项可以影响背景，一个是背景色，另 一个是背景模式。背景模式可以为透明的（Transparent）或 不透明的（Opaque），缺省为不透明的。当背景模式为不透 明时，按背景颜色的值填充字符的空余部分，如果背景模式 为透明的，将不用背景颜色填充，保留屏幕上原来的颜色。 背景模式可用函数SetBkMode来设置，它设置当前的背景模 式并返回原来的背景模式，该函数的原型为：
CDCS specimen C - collated simulation documents
Certificate for Documentary Credit Specialists (CDCS®) – 601/1159/8Session code: Specimen paper C (electronic)Length of examination: 3 hours__________________________________________________________________________Simulation Exercises 1–3Applicable current ICC rules apply throughout.Instructions to candidates1. You can print this document out before answering the Specimen Paper B questions. Pleasenote: Specimen Paper B is only available in an electronic format.2. The simulation documents will also be available within the specimen paper itself.The London Institute of Banking & Finance is a registered charity, incorporated by Royal Charter.SIMULATION 1DocumentsIssuing Bank in People’s Republic of China Irrevocable Documentary Credit Number 2451Place and Date of issue: 15 June XXXXExpiry Date and Place of Presentation for Documents: 31 August XXXX New York Applicant:China Machinery & Steel Co.Beijing (One Special Square)Advising Bank:Credit available with the ABC Bank New York by sight payment.Beneficiary:Export Machines, Inc.One PlazaNew York, NYFAX 347-111-2225Amount:About USD 800,000.00Partial Shipments: Not AllowedTranshipment: Not AllowedInsurance covered by applicant.Shipment from USA port to ShanghaiDocuments:•Original commercial invoice covering 2 compressors and 1 turbine for power plant CFR Shanghai Incoterms 2010•Full set bills of lading issued to order of shipper and endorsed in blank marked “notify applicant”Other conditions•Import licence 12345•Goods to be of US originWe hereby issue the documentary credit in your favour. It is subject to the UCP 600.Name and signature of the Issuing Bank in People’s Republic of China.P. J ChinP.J. ChinEXPORT MACHINES, INC.ONE PLAZANEW YORK, N.Y.FAX 347-111-2224/2228FINAL TAX INVOICESOLD TO:CHINA MACHINERY & COPPER CO.ONE SPECIAL SQUAREBEIJING, P.R. CHINAINVOICE NO. 913QUANITIES: 2 COMPRESSORS FOR ATOMIC/SOLAR PLANT1 TURBINE FOR SOLAR POWER PLANTCFR SHANGHAI USD 890,000.00TWO BOXES OF SPARE PARTS FREE OF CHARGESIMULATION 2DocumentsINCOMING SWIFT MT700FROM ISSUING BANK FIRST BANK OF NAPLES, NAPLES, ITALYTO ADVISING BANK INDIAN BANK, NEW ROAD, CALCUTTA, INDIA27: SEQUENCE OF TOTAL 1/140A: FORM OF DOCUMENTARY CREDIT IRREVOCABLE20: DOCUMENTARY CREDIT NUMBER DJM 23245640E: APPLICABLE RULES UCPURR LATEST VERSION31C: DATE OF ISSUE XX060231D: DATE AND PLACE OF EXPIRY XX0307, CALCUTTA50: APPLICANT CAESAR CONSTRUCTION, VIA ROMA, NAPLES, ITALY 59: BENEFICIARY BUILD-IT INDUSTRIES, 3RD FLOOR, STAR BUILDINGCALCUTTA, INDIA32: CURRENCY AND AMOUNT EUR30000,0041A: AVAILABLE WITH/BY INDIAN BANK, NEW ROAD, CALCUTTA, INDIABY PAYMENT41C: DRAFTS AT SIGHT42A: DRAWEE INDIAN BANK43P: PARTIAL SHIPMENTS NOT ALLOWED43T: TRANSHIPMENT ALLOWED44A: ON BOARD/TAKING IN CHARGE MUMBAI44B: FOR TRANSPORTATION TO NAPLES44D: SHIPMENT PERIOD FIRST HALF OF FEBRUARY45A: DESCP OF GOODS AND/OR SERVICES 35 TONNES OF FAST SETTING CONCRETE MIX46A: DOCUMENTS REQUIRED +COMMERCIAL INVOICE DULY SIGNED BY BENEFICIARYSHOWING CFR NAPLES+FULL SET 3/3 ORIGINAL BILLS OF LADING, NOTIFY THEAPPLICANT AND MARKED FREIGHT PREPAID.47A: ADDITIONAL CONDITIONS SHIPPING MARKS B 724 1-60 TO BE STATED ON ALLDOCUMENTS71B: CHARGES ALL BANKING CHARGES OUTSIDE OF ITALY ARE FORACCOUNT OF BENEFICIARY48: PRESENTATION PERIOD 21 DAYS49: CONFIRMATION INSTRUCTIONS WITHOUT53A: REIMBURSING BANK EURO BANK FRANKFURT78: INSTRUCTIONS TO THE PAYING/ YOU ARE AUTHORIsED TO CLAIM REIMBURSEMENT ACCEPTING/NEGOTIATING BANK FROM THE REIMBURSING BANK72: SENDER TO RECEIVER INFORMATION PLEASE ACKNOWLEDGE RECEIPT****MESSAGE PASSED AUTHENTICATION****Name of signatoryK DevK. DevSignature For Build-It IndustriesShipper:Build-It Industries: New Road Calcutta, IndiaConsignee: Caesar Construction, Via Roma, Florence, ItalyABC LINEBILL OF LADING FOR COMBINED TRANSPORT SHIPMENT OR PORT TO PORTB/L Reference number: AP213/25Marks & No. of Goods description: Gross weightMeasurement Numbers:Packages:Kg: cubic metres: B 72460 Cases CaseCasaes CONCRETE MIX33,000 375 MADE IN UK 1-60No. of original Bills of Lading: TWO (02)Place and date of issue:Calcutta, 15 February XXNotify: Port of discharge NAPLESOcean vesselThe Pride of MumbaiPort of loading: MumbaiShipped on board the vessel, the goods orpackages said to contain the cargo described inapparent good order unless otherwise stated herein.Signed:A McCleishFor ABC Line as the carrierSIMULATION3Documents Irrevocable Standby Credit Application FormApplicant:Enterprise Electronics Company North Point StreetHong Kong Issuing Bank: Premium Bank Kennedy Town Road Hong KongDate of Application: 01 December 2XX1 Expiry Date and Place for Presentation of documentsIssue by:Airmail Courier Expiry Date: 30 June 2XX2Place for Presentation: Buenos Aires, ArgentinaTeletransmissionBeneficiary:Buenos Aires Port AuthorityBuenos Aires, ArgentinaAdvising Bank:Big Apple Bank New York, New York Amount in figures and words (Please use ISO Currency Codes):USD 500,000 (US dollars five hundred thousand)Confirmation of the Credit:not requested requested authorised if requestedby Beneficiary Credit available with Nominated Bank: Big Apple BankNew York, New YorkCredit is to contain an automatic extension clause with (specify all that apply): i. a notification period of (__45__) days in the event of non-extension;ii. multiple renewal period(s) of (__6 months__);iii. a final expiration date of _1 July 2XX4_________________. by payment at sightby deferred payment at:by acceptance of drafts at: by negotiation:All banking charges, other than Issuing Bank’s charges, are for account of: BeneficiaryApplicant Against the documents detailed herein: and Beneficiary’s drafts(s) drawn on:Description of transaction:Backstop for issuance of a Bank Guarantee by Gaucho Bank on behalf of Enterprise Electronics Argentina S.A. based on the local standard format to guarantee lease payment obligations at the Buenos Aires Port Authority under a certain Lease Agreement. The Standby credit will be effective after the Lease Agreement is signed.Documents:Beneficiary’s authenticated SWIFT/Telex or written statement stating the amount of any drawing hereunder represent funds due and payable because:A) it has become necessary for Gaucho Bank to make payment under its garantia bancaria issued on behalf of Enterprise Electronics Argentina S.A., in favor of the Port Authority, Buenos Aires, ArgentinaORB) we received a notice of non-renewal of expiry date of Standby Letter ofCredit No. ____ issued by Premium Bank and substitute Letter of Credit orsecurity has not been providedORC) we received a notice of non-renewal of the expiry date for the confirmationof Standby Letter of Credit issued by Premium Bank and substitute Letter ofCredit or security has not been provided.Additional Instructions:1. The letter of credit is assignable.2. Letter of credit to be confirmed by Premium Bank Hong Kong.3. Incorporate the following clause in the Standby credit:Each presentation honored by us shall immediately reduce the amount available to be drawn hereunder by the amount of the payment made in respect of such presentation. In addition, the amount available to be drawn under this letter of credit shall be reduced, automatically and without amendment, on each date (each, an “Automatic Reduction Date”) set forth in the following automatic reduction schedule by the amount (the “Reduction Amount”) set forth opposite such date. However, such scheduled reduction amount(s) shall be reduced, or offset, by the amount of any payment made by us against a drawing made on or prior to the relevant automatic reduction date. We request you to issue on our behalf and for our account your Irrevocable Standby Credit in accordance with the above instructions (marked ( ) where appropriate). This Credit will be subject to the International Standby Practices (1998 Revision) Publication No. 590 of the International Chamber of Commerce, Paris, France, insofar as they are applicable.AUTOMATIC REDUCTION SCHEDULE AUTOMATIC REDUCTION AMOUNT DATE1 July 2XX2 USD100,000 1 January 2XX3 USD100,0001 July 2XX3 USD100,000 1 January 2XX4 USD100,000 1 July 2XX4 USD100,000 James T. Chen JT Chen ____Name and signature of the Applicant。
JXI5020 Preliminary Datasheet V1.01-CN
©聚积科技2009台湾新竹市埔顶路18号6F 之4电话：+886-3-579-0068，传真：+886-3-579-7534 E-mail: info@初始规格书JXI502016位恒流LED 驱动器特色z 16个恒流输出通道 z恒流输出值不受输出端负载电压影响恒流范围值， 3~45mA@V DD =5V ； 3~30mA@V DD =3.3V z极为精确的电流输出值，通道间差异值：<±1.5％(一般值); <±2.5％(最大值)； 芯片间差异值：<±1.5％(一般值); <±3.0％(最大值)。
z 利用一个外接电阻，可设定电流输出值z 快速的输出电流响应，OE ：70ns(保持输出一致性的条件下) z 高达25MHz 时钟频率 z 具Schmitt trigger 输入装置 z 操作电压：3.3/5.0伏特 z无铅环保包装产品说明JXI5020是利用最新PrecisionDrive™技术，专为 LED 显示面板设计的驱动IC ，它内建的CMOS 位移缓存器与栓锁功能，可以将串行的输入数据转换成平行输出数据格式。
JXI5020的输入电压范围值为3.3伏特至5伏特，提供16个电流源，可以在每个输出级提供3~45mA 定电流量以驱动 LED ；且单一颗IC 内输出通道的电流差异小于±2％@I OUT=25m ，±2.5％@I OUT =3mA ；多颗IC 间的输出电流差异小于±3%；电流随着输出端耐受电压(V DS )变化，被控制在每伏特0.1%；且电流受供给电压(V DD )、环境温度的变化也被控制在1%。
使用者可以经由选用不同阻值的外接电阻器来调整 JXI5020各输出级的电流大小，藉此机制，使用者可精确地控制LED 的发光亮度。
JXI5020的设计保证其输出级可耐压17伏特，因此可以在每个输出端串接多个LED 。
CDC--学生基本信息模板
1、年级的书写方式为：“小学XX年级”、“初中XX年级”。
班级的书写方式为：“1”、“2”。
2、填写时请务必参照示例数据的格式来进行填写。
3、以上所有列名，其中深灰色部分红色字体的为必填项！，浅灰色部分绿色字体的为选填项！以下数据为示例数据:小学一年级11111110004张玉女20040222汉族健康或良好小学一年级11111110005汪峰男20040212汉族一般或较弱小学一年级21111110006张华女20040203汉族一般或较弱小学一年级21111110007李行亮男20050921汉族一般或较弱小学二年级11111110008李倩女20030312汉族一般或较弱小学二年级11111110009李虎男20040124汉族一般或较弱小学三年级21111110010王野男20031010汉族一般或较弱小学三年级21111110011张晓女20050112汉族一般或较弱真实数据请从第17行开始填写：初三820123040406许海燕女19991014汉族健康或良好初三820123040306钟立庆男20001001汉族健康或良好初三820123040260陈皆传男20001129汉族健康或良好初三820123040409刘华琳女20001129汉族健康或良好初三820123040448钟国庆男19991001汉族健康或良好初三820123040037卢峥男20000713汉族健康或良好初三820123040105曾城男20000312汉族健康或良好初三820123040453严永春女19990306汉族健康或良好初三820123040374卢倩女20000527汉族健康或良好初三820123040416叶志超男20000622汉族健康或良好初三820123040169卢海瑞男20000426汉族健康或良好初三820123040151刘蕾磊女20000229汉族健康或良好初三820123040369钟俊丽女20000903汉族健康或良好初三820123040074陈懋睿男20000708汉族健康或良好初三820123040350龙甜甜女19991125汉族健康或良好初三820123040075袁从玲女20000207汉族健康或良好初三820123040163何欣雨女20000618汉族健康或良好初三820123040106梁珊女20010412汉族健康或良好初三820123040180叶紫慧女20000109汉族健康或良好初三820123040426李家明男20000316汉族健康或良好初三820123040044郭宗栊男20001030汉族健康或良好初三820123040064李磊男20000226汉族健康或良好初三820123040290张子龙男20000728汉族健康或良好初三820123040479钟娟女19990106汉族健康或良好初三820123040205董颖女19991203汉族健康或良好初三820123040397郭幼林男19981020汉族健康或良好初三820123040283张燕琦女20000126汉族健康或良好初三820123040187严富男20000820汉族健康或良好初三820123040315严洁羽女20001101汉族健康或良好初三820123040219钟慧灵女19991006汉族健康或良好初三820123040120黄以容男20000610汉族健康或良好初三820123040337陈龙男20010113汉族健康或良好初三820123040338邹治芳女19991126汉族健康或良好初三820123040342黄洁女20000725汉族健康或良好初三820123040207伍滨男19990408汉族健康或良好初三820123040460幸泽荣男19991210汉族健康或良好初三820123040082叶娟女19990927汉族健康或良好是是否是否否是是否是是否是是否是是否是否否是是否是是否15742是否否16861.3是是否15643.4是是否16249.5是是否16047.7是是否17076是否否17256.8是是否16661是是是163.555.7是是否16760.9是是否17464.2是是否15742.8是是否16045.2是是否16447.3是是否15543.4是是否15536.5是是否15337.1是是否16242.2是是否16048.6是是否16248.1是是否17046.7是是否17048.3是是否17555.4是是否16555.1是是否161.585.5是是否17496是是否15742.5是是否14936.8是是否16243.2是是否15747.9是是否16750.3是是否16447.8是是否14546是是否16249.2是是否16550.8是是否16769.2是是否16045.3身份证件号。