自动售饮料机 Verilog语言

自动售饮料机 Verilog语言
(1)分频模块(实现1s灯变换一次)
module half_clk(
input clk_in,
input rst,
output reg clk_out
);
reg [24:0]count;
always @(posedge clk_in or posedge rst )
if(rst) begin clk_out<=0; count<=0; end
else begin
if(count==24999999) begin clk_out<= ~clk_out; count<=0; end
else count<=count+1;
end
endmodule
(2)实现模块
module toubi(rst,clk,K1,K2,K5,L0,L1,L2,L3,L4) input rst,clk,K1,K2,K5;
output reg L0,L1,L2,L3,L4;
reg [2:0]state;
parameter
s0=3'b000;
s1=3'b001;
s2=3'b010;
s3=3'b011;
s4=3'b100;
always @(posedge clk or posedge rst)
if(rst) begin state<=s0;L0<=0;L1<=0;L2<=0;L3<=0;L4<=0; end else
case(state)
s0:if(k1==1) begin
state<=s1;L0<=0;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k2==1) begin
state<=s2;L0<=0;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k5==1) begin
state<=s0;L0<=1;L1<=0;L2<=0;L3<=0;L4<=0; end s1:if(k1==1) begin
state<=s2;L0<=0;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k2==1) begin
state<=s4;L0<=0;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k5==1) begin
state<=s0;L0<=1;L1<=1;L2<=0;L3<=0;L4<=0; end s2:if(k1==1) begin
state<=s3;L0<=0;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k2==1) begin
state<=s4;L0<=0;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k5==1) begin
state<=s0;L0<=1;L1<=0;L2<=1;L3<=0;L4<=0; end s3:if(k1==1) begin
state<=s4;L0<=0;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k2==1) begin
state<=s0;L0<=1;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k5==1) begin
state<=s0;L0<=1;L1<=0;L2<=0;L3<=1;L4<=0; end s4:if(k1==1) begin
state<=s0;L0<=1;L1<=0;L2<=0;L3<=0;L4<=0; end
else if(k2==1) begin
state<=s0;L0<=1;L1<=1;L2<=0;L3<=0;L4<=0; end
else if(k5==1) begin
state<=s0;L0<=1;L1<=0;L2<=0;L3<=0;L4<=1; end
endcase
endmodule
(3)top模块
module toubitop(
input rst,clk,K1,K2,K5;
output reg L0,L1,L2,L3,L4;
);
wire clk_out;
half_clk A1(clk,rst,clk_out);
toubi A2(clk_out,rst,K1,K2,K5,L0,L1,L2,L3,L4); endmodule
(4)测试模块
`timescale 1ms / 1ms
////////////////////////////////////////////////////////////////////
////////////
// Company:
// Engineer:
//
// Create Date: 15:02:00 12/10/2013
// Design Name: toubitop
// Module Name: D:/Xilinx/shiyan2/kkk/test.v
// Project Name: kkk // Target Device: // Tool versions: //
Description: //
// Verilog Test Fixture created by ISE for module: toubitop
//
// Dependencies: //
// Revision:
// Revision 0.01 - File Created
// Additional Comments: //
////////////////////////////////////////////////////////////////////
////////////
module test;
// Inputs
reg clk;
reg rst;
reg K1;
reg K2;
reg K5;
// Outputs
wire L0;
wire L1;
wire L2;
wire L3;
wire L4;
// Instantiate the Unit Under Test (UUT)
toubitop uut (
.clk(clk),
.rst(rst),
.K1(K1),
.K2(K2),
.K5(K5),
.L0(L0),
.L1(L1),
.L2(L2),
.L3(L3),
.L4(L4)
);
always #500 clk=~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
K1 = 0;
K2 = 0;
K5 = 0;
// Wait 100 ns for global reset to finish
#100 rst=1;
#100 rst=0;
#1000 K1=1;
#1000 K1=0;
#1000 K1=1;
#1000 K1=0;
#1000 K2=1;
#1000 K2=0;
#1000 K2=1;
#1000 K2=0;
// Add stimulus here
end
endmodule