allegro导出DXF时提示cnv文件出错

allegro中 DXF的导出和导入步骤以及注意的问题

本文主要介绍在allegro 16.5中，导入dxf文件的方法。

工程实践基于珠海鼎芯imx6核心板，电脑系统win7/64位。

DXF导出：
1. 把要导出的显示出来；
2.然后file ，export，dxf；
3.设置好units ，一般默认即可；
4.点击edit映射层；
5.Ok后返回，export；
DXF的导入：（重点）这部分容易出错
1.首先在allegro中设立一个层，用来放上面要导入的dxf；（也可以后续在dxf导入界面新增subclass实现）
2.setup，sub classes；一般在board geometry下建立一个自己命名的层；
3.file；import；dxf；
DXF的导出和导入步骤以及注意的问题
4.记得在incremental addition中打上勾；否则会出现问题；
5.点击edit/view layers...；把他们映射到在board geometry中建立的层；
6.点击OK后返回，import 即可；。

Allegro使用问题汇总

allegro使用汇总2010-06-21 15:31:10| 分类： cadence |字号订阅1.如何在allegro中取消花焊盘(十字焊盘)set up->design parameter ->shape->edit global dynamic shape parameters->Thermal relief connects ->Thru pins ,Smd pins -> full contact2.allegro 中如何设置等长setup -> constraints->electrical->net->routing->Min Max Propagation delays选择要等长的net->右击->create->pin pair->选择pin修改 prop daly 的min 和max项3.如何设置allegro的快捷键修改文件 $inst_dir\share\pcb\text\env 或 $inst_dir\pcbevn\env快捷键定义如下:alias F12 zoom outalias ~R angle 90 (旋转90 度)alias ~F mirror (激活镜相命令)alias ~Z next (执行下一步命令)alias End redisplay(刷新屏幕)alias Del Delete(激活删除命令)alias Home Zoom fit(全屏显示)alias Insert Define grid(设置栅格)alias End redisplayalias Pgdown zoom outalias Pgup zoom inalias F12 custom smoothalias Pgup slidealias Pgdown donealias Home hilightalias End dehilightalias Insert add connectalias Del Delete4.如何在allegro中删除有过孔或布线的层时不影响其他层1.输出specctra的dsn文件allegro->file->export->router->demo.dsn->run2.产生session文件specctra(pcb router)->file->write->session->demo.ses->ok3.删除某一层中的布线和过孔delete(ctrl+D)->..4.删除allegro中的板层setup->cross section->鼠标右键->delete5.导入session文件allegro->file->import->router->demo.ses->run也可先将通过该层的过孔先替换成顶层焊盘,删除该层以后再替换回来5.如何在Allegro中同时旋转多个零件1.Edit->Move 在Options中Rotation的Point选User Pick2 再右键选Term Group 按住鼠标左键不放并拉一个框选中器件多余的可用Ctrl+鼠标左键点击去掉.3. 选好需整体旋转的器件后右键complete.4. 提示你Pick orgion 鼠标左键选旋转中心.5 下面右键选rotate 即可旋转了.6.allegro 16.0 透明度设置display->colour/visibility->display->OpenGL->Global transparency->transparent7.allegro Drill hole size is equal or larger than smallest pad size.Pad will be drilled away.提示Drill hole size is equal or larger than smallest pad size.Pad will be drilled away.不用理睬这一提示8.ALLEGRO 如何生成钻孔文件Manufacture -> NC -> Drill Customization->auto generate symbolsManufacture -> NC -> Drill LegendManufacture -> NC ->NC parameters->enhanced excellon format->closeManufacture -> NC -> NC Drill->auto tool select->optimize drill head travel9.CAM350如何正确导入钻带文件导进去后MACRO->PLAY->选择(CAM350--SCRIPTS)PADS_DRILL->选择钻带的REP文件还没测试过，rep文件从哪儿来的呢10.allegro 如何设置route keepin,package keepin1.setup->area->route keepin,package keepin ->画框2.edit ->z-copy->options->package keepin,route keepin->offset->50->点击外框11.allegro 中如何禁止显示shape完全禁止的方法没找到setup->user preference editor->display->display_shapefill->输入一个较大的数shape在显示时就不是那么显眼了set-user preference editor-shape-no shape fill(v)12.如何在allegro设置自定义元件库路径在下面两个位置添加自定义元件的路径Setup->User Preferences Editor->Design_paths->padpathSetup->User Preferences Editor->Design_paths->psmpath1.在allegro中如何修改线宽在Allegro的Setup－>constraints里的set standard values中可定义每一层走线的宽度，比如，可以定义VCC和GND的线宽为10 Mil。

Allegro输出DXF文件操作指导

Allegro输出DXF文件操作指导Allegro支持输出DXF文件，用于检查PCB的结构，具体操作如下1.首先在PCB上打开需要的输出的层面，需要哪层开哪层，如下图所示2.点击file-export3.弹出一个对话框，输入文件名，格式选择Reversion14 ，单位选择mm，精度选择44.然后点击Edit5.会出现一个对话框，选择select all ，勾选Use layer names。

，最后点击Map6.最后点击ok7.回到页面，点击export8.可以看到DXF文件已经输出9.打开DXF文件的样式如下图This section is describe what the function allegro have ,helpfully could let user know more about allegroAllegro Design and Analysis includes design authoringPCB layout and Library and Design Data ManagementWith. It can ensure the end-to-end design of PCB with high quality and efficiencyRealize smooth data transfer between tools, shorten PCB design cycle, and shorten productMarket time1. Design authoringProvide a flexible logic constraint driven flow, management design rules, network hierarchy,Bus and differential pair.1.1.1 Main features and functionsThrough hierarchical and design "derivation" function, improve the original of complex designMap editing efficiency.Powerful CIS helps users quickly determine part selection and accelerate design flowAnd reduce project cost.1.2.1 Main featuresSchematic designers and PCB design engineers can work in parallel. Advanced design efficiency improves functions, such as copying the previous schematic design Select multiplexing with or by page. Seamless integration into pre simulation and signal analysis.1.2.2 Main FunctionsProvide schematic diagram and HDL/Verilog design input.Assign and manage high-speed design rules.Support netclasses, buses, extension networks and differential pairs. Powerful library creation and management functions.Allows synchronization of logical and physical designs.Realize multi-user parallel development and version control.Pre integration simulation and signal analysis.Support customizable user interface and enterprise customization development.1.3 o Allegro n Design Publisher1.3.1 Main Features and FunctionsAllows you to share designs with others using PDF files.The entire design is represented in a single, compact PDF format. Improve design readability.Provide content control - users can select the content to be published.1.4 Allegro A FPGA m System Planner1 1.4.1 Main features and functionsComplete and scalable FPGA/PCB collaborative design technology for ideal "Design and correct "pin assignment.Scalable FPGA/PCB protocol from OrCAD Capture to Allegro GXLSame as the design solution.Shorten the optimization pin allocation time and accelerate the PCB design cycle.2. B PCB layoutIt provides expandable and easy to use PCB design (including RFPCB) Then drive PCB design solution. It also includes innovative new automatic deliveryMutual technology can effectively improve the wiring of high-speed interfaces; Apply EDMD (IDX) mode, which makes ECAD/MCAD work smoothly; Execute modern industry standard IPC-2581,Ensure that the design data is simply and high-quality transferred to the downstream link.2.1.1 Main featuresSpeed up the design process from layout, wiring to manufacturing. Including powerful functions, such as design zoning, RF design functions and global design rules Stroke.It can improve productivity and help engineers to quickly move up to mass production* g- M4 G8 |6 }9 k7 G2.1.2 Main FunctionsProvide scalable full function PCB design solutions.Enable constraint driven design processes to reduce design iterations. Integrated DesignTrueDFM technology provides real-time DFM inspection. Provide a single, consistent context for management.Minimize design iterations and reduce overall Flex and rigid flexible designCost, and has advanced rigid and flexible design functions.Realize dynamic concurrent team design capability, shorten design cycle, and greatly reduceTime spent in routing, winding and optimization.Provide integrated RF/analog design and mixed signal design environment. Provides interactive layout and component placement.Provide design partitions for large distributed development teams. Realize real-time, interactive push editing of routing.It is allowed to use dynamic copper sheet technology to edit and update in real time.Manage netscheduling, timing, crosstalk, routing by designated layer and area Bundle.Provide proven PCB routing technology for automatic routing.Realize hierarchical route planning and accelerate the completion of design.Shorten interconnect planning and cabling time for high-speed interface intensive design.Provide a comprehensive, powerful and easy-to-use tool suite to help designersEfficient and successful manufacturing switch: DFM Checker is aimed at the company/manufacturerReview the specific rules of manufacturing partners; Used to reduce manufacturing and assembly documentsThe document editing time of the file can reach 70%; The panel editor will assemble the panel designThe intention is communicated to the manufacturing partners; Output design data in various manufacturing formats.3. y Library d and n Design a Data ManagementFor cost-effective projects that need to be delivered on time, it is easy to obtainCurrent component information and design data are critical. library and designData management is a collaborative control of the company's internal cooperation and design processAdvanced functions are provided. As the design cycle shortens and the complexity increases, youThere must be a design approach that increases predictability and accelerates design turnaround.3.1.1 Main featuresReduce time and optimize library development related resources. Improve the precision in the process of parts manufacturing. Q9 b3.1.2 Main functionsReduce time and optimize library development and validation through integrated creation and validation processes Certification related resources.A simple method to develop devices with large pin count can shorten the time from a few days to A few minutes.Powerful graphic editor supports custom shape and spreadsheet import forSchematic symbols are created to ensure the reliability and integrity of data.Supports the import of part information from general industry formats, allowing rapid creation and Update part information.Common library development environment supporting schematic tools from different suppliers, including Mentor Graphics Design Architect and Mentor Graphics Viewdraw。

allegro导入网表错误详解

此文章由资深Layout攻城狗LGW（Gavin）提供，是其的经验笔记，可转可拷。

错误种类1：#1 WARNING(SPMHNI-192): Device/Symbol check warning detected.WARNING(SPMHNI-194): Symbol 'SOD_123' for device 'SCHOTTKY_SOD_123_B5819W(DNI)' not found in PSMPATH or must be "dbdoctor"ed.此类错误和没有PCB封装有关。

错误种类2：ERROR(SPMHNI-196): Symbol 'UTH12T02' for device 'XFMR-H1102_0_UTH12T02_H12T02' has extra pin '14'.此类错误表示原理图符号的PIN脚和PCB封装PIN数量或命名不对。

错误种类3：#5 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-190): Device problem 'FERRITE BEAD_0_LC0805_100MHZ;10'. Package property error: 'VALUE'='100Mhz;100ohm±25%_3A'. Illegal character(s) present in the name or value..ERROR(SPMHNI-170): Device 'FERRITE BEAD_0_LC0805_100MHZ;10' has library errors. Unable to transfer to Allegro.这个错误是因为原理图元件的VALUE有非法字符。

ALLEGRO常见问题大全

ALLEGRO常见问题大全Q: Allegra中颜色设置好以后，应该可以导出相关设置文件，下次碰到不同设置的板子，看着难受就可以直接读入自己的文件改变设置了A:16.2版本的可以这样做：file->export->parameters,选中颜色就行了，其它的参数一样可以保存。

Q:ALLEGRO 自动布线后,为直角.如何调整成45度角走线A: ROUTE --GLOSS---PARAMETERS---CONVERT CORNET TO ARC一、群组布线;群组布线包括总线布线和一次布多外Trance.1.一次布多个Trance .鼠标左键进行选择多外PIN,或VIA. 同时可以在布线过程中用右键切换到单线模式。

群组布线只能在一个层中，不允许打过孔。

也可以在群组布线过程中，右键，“CHANGE Control Trace”Cadence CIS即原理图中，放大缩小缩小的快捷键按住CTRL键+鼠标中间滚轮）5. ALLEGRO 出光绘文件前，最好加个PHOTO_OUTLINE,确认输出光绘文件的范围Class: manufacture — Subclass: photoplot outline6. 光绘设置详解/bbs/viewthread.php?tid=28&page=1ALLEGRO 标注 1. dimension linear : 对于比较规则，简单的板子，通常采用.2.dimension datum ：对于较复杂的板子可以采用。

先确定一个基准点，接下来对每个点所标注的数据都是相对基准点的坐标值。

Manufacture------dimension/draft -----dimension linear / dimension datum2.表层铺铜时，由于铺铜和PIN 的间距问题，在PIN 和PIN 之间经常产生一些尖角。

产生这种原因的解决办法：一。

一个一个修改Boundary二。

allegro_16.0_坐标文件导出

Allegro中导出坐标文件的方法
2010-05-27 13:05:21| 分类：Allegro | 标签：|字号大中小订阅
Allegro中导出坐标文件的方法
Allegro 软件是Cadence 公司出品的面向中高端企业用户的PCB 设计软件，主要针对高速、高密度电路板设计，尤其在通讯等领域被广泛应用，目前最新版本号是16.0。

Allegro 软件导出坐标数据步骤：
1）用Allegro 软件打开PCB 设计文件。

2）设定原点和切换公制单位。

选择菜单“Setup → Drawing Size…”，弹出如图3 所示对话框，用户单位选择millimeter，MOVE ORIGIN 栏中输入新原点位置相对于当前原点的坐标数据，然后按“OK”确定。

图3 Allegro 单位切换和原点设定
3）坐标文件导出。

选择菜单“File → Export → Placement…”，弹出如图4 所示对话框，注意Placement Origin 选择Body Center，按“Export”按钮输出坐标数据。

图4 Allegro 坐标输出对话框。

allegro遇到的问题汇总

allegro遇到的问题汇总allegro 遇到的问题汇总避免忘记1、更新封装封装修改后，在allegro下palce--update symbols。

在package symbol下选择要更新的封装。

注意勾选update symbol padstacksIgnore FIXED property。

2、如何批量放置VIA？⽐⽅在TOP层铺了⼀⽚铜到地，然后想规则的放置⼀批VIA将表⾯铺铜区连接到地层，能不能⾃动完成啊？⼿动放很⿇烦也不均与，影响美观CopyFind勾選ViaOption填寫數量，間距。

别⼈整理的还不错原⽂地址/doc/c97b3ffe58fafab069dc02f0.html /BLOG_ARTICLE_3006536.HTM1. Allegro中我设置了highlight的颜⾊为⽩⾊，但选中后颜⾊是⽩蓝相间的，很不⽅便查看。

是什么地⽅需要设置，哪位⼤虾告诉哈我？答：setup/user preferences/display/display_nohilitefont 这个选项打勾就⾏了。

2. 不⼩⼼按了Highlight Sov后部分线⾼亮成⽩⾊，怎样取消？答：这个是⽤来检查跨分割的，取消的办法是：如果是4层板的话，在电源层跟地层都铺上地⽹络，然后再按Highlight Sov刷新即可。

3. 如何更改Highlight⾼亮默认颜⾊？答：可以在Display->Color/Visibility->Display->Temporary Highlight⾥修改即可，临时修改颜⾊可以点Display->Assign Color 来实现。

4. 如实现Highlight⾼亮部分⽹络，⽽背景变暗，就像Altium Designer那样？答：可以在Display->Color/Visibility->Display->Shadow Mode打开该模式，并且选中Dim active layer即可。