FPGA可编程逻辑器件芯片XC2V1000-4FG456I中文规格书
FPGA可编程逻辑器件芯片XC2V1000-6FGG456I中文规格书
Table 119: IBUFDS, IBUFDS_DIFF_OUT, IBUFDS_DIFF_OUT_INTERMDISABLE, and IBUFDS_INTERMDISABLE Ports (cont'd)PortI/O Description IBInput Input port connection. Connect directly to top-level N-side port in the design.IBUFDISABLE Input IBUFDISABLE is not supported in HD IOB.(IBUFDS_DIFF_OUT_INTERMDISABLE and IBUFDS_INTERMDISABLE only)Differential Bidirectional Buffer PrimitivesFigure 69: Differential Bidirectional Buffer PrimitivesIOBUFDSTI OIO IOB IOBUFDS_INTERMDISABLE T IOIO IOBINTERMDISABLEIBUFDISABLE X21633-092318Figure 70: Differential Bidirectional DIFF_OUT Buffer PrimitivesIOBUFDS_DIFF_OUTIO IOBIOBUFDS_DIFF_OUT_INTERMDISABLE IO IOBX21634-112818Chapter 7: HD IOB ResourcesTable 120: IOBUFDS, IOBUFDS_DIFF_OUT, IOBUFDS_DIFF_OUT_INTERMDISABLE, and IOBUFDS_INTERMDISABLE AttributesAttributeValues Description SLEWSLOW, FAST Specifies the drive strength of the output.IOSTANDARDSee HD IOB Supported Standards Assigns an I/O standard to the E_IBUFDISABLE FALSE IBUFDISABLE is not supported in HD IOB and must be set to FALSE.(IOBUFDS_INTERMDISABLE and IOBUFDS_DIFF_OUT_INTERMDISABLE only)Table 121: IOBUFDS, IOBUFDS_DIFF_OUT, IOBUFDS_DIFF_OUT_INTERMDISABLE, and IOBUFDS_INTERMDISABLE PortsPortI/O Description IO Inout Inout port connection. Connect directly to top-level P side port in the design.IOBInout Inout port connection. Connect directly to top-level N side port in the design. (IOBUFDS_DIFF_OUT, IOBUF_DIFF_OUT_INTERMDISABLE only)OOutput Output path of the buffer representing the input path to the device.OBOutput Complimentary buffer output representing the input path to the device.(IOBUFDS_DIFF_OUT, IOBUF_DIFF_OUT_INTERMDISABLE only)IInput Input port connection. Connect directly to top-level P-side port in the design.TInputTristate enable input signifying whether the buffer acts as an input or output. (IOBUFDS, IOBUFDS_INTERMDISABLE only)IBUFDISABLEInput IBUFDISABLE is not supported in HD IOB. ( IOBUFDS_INTERMDISABLE,IOBUFDS_DIFF_OUT_INTERMDISABLE only)INTERMDISABLE Input Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.(IOBUFDS_INTERMDISABLE, IOBUFDS_DIFF_OUT_INTERMDISABLE only)TM Input Tristate enable input for the P-side or master side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TS input. (IOBUFDS_DIFF_OUT,IOBUFDS_DIFF_OUT_INTERMDISABLE only)TS InputTristate enable input for the N-side or slave side signifying whether the buffer acts as an input or output. This pin must be connected to thesame signal as the TM input. (IOBUFDS_DIFF_OUT and IOBUFDS_DIFF_OUT_INTERMDISABLE only)Differential Output Buffer PrimitivesFigure 71: Differential Output Buffer PrimitivesIOOBUFTDS T OBI OOBUFDSOB X21630-092318Chapter 7: HD IOB ResourcesAppendix A: Additional Resources and Legal NoticesAppendix A Additional Resources and Legal NoticesXilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.Documentation Navigator and Design HubsXilinx®Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. T o open DocNav:•From the Vivado® IDE, select Help → Documentation and Tutorials.•On Windows, select Start → All Programs → Xilinx Design T ools → DocNav.•At the Linux command prompt, enter docnav.Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. T o access the Design Hubs:•In DocNav, click the Design Hubs View tab.•On the Xilinx website, see the Design Hubs page.Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.ReferencesThese documents provide supplemental material useful with this guide:。
FPGA可编程逻辑器件芯片XC2V1000-5FGG456C中文规格书
Table 2: Enabling Bidirectional Datapath ControlControl MechanismRelated Attributes Gating •RX datapath gating: The RX_GATING attribute enables gating of the RX datapath based on the PHY_RDEN port.While RX_GATING enables gating, the CONTINUOUS_DQS attribute lets users choose between PHY_RDEN operating based in the PLL_CLK or the strobe clock domain.•TX datapath gating: The TX_GATING attribute enables gating of the TX datapath based on the PHY_WREN port (which is serialized but not inverted when used for gating) and PHY_WREN operates in the PLL_CLK domain.NIBBESLICE[1] cannot be gated.Tristating •Tristating: The TBYTE_CTL_# attribute determines whether tristating is controlled by the T (combinatorial)port or an inverted and serialized PHY_WREN port (which is in the PLL_CLK domain).T_OUT[5:0] is the tristate control output from the XPHY. Each bit of T_OUT is associated with a NIBBLESLICE, and TBYTE_CTL_# allows each NIBBLESLICE to select its corresponding T_OUT bit to be controlled by either T or PHY_WREN. In other words for a NIBBLESLICE[x], T_OUT[x]reflects the tristate control input selected by TBYTE_CTL_x. If TBYTE_CTL_x = T, T_OUT[x](associated with NIBBLESLICE[x]) is controlled via the T[x] input. Because this is a combinatorial route, T_OUT[x] is not aligned to the data. If TBYTE_CTL_x = PHY_WREN, T_OUT[x] (associated with NIBBLESLICE[x]) is controlled through the PHY_WREN port. This input is inverted,serialized, and output synchronously (through T_OUT[x]) with the TX data when used for tristating. For more information, see Controlling Tristate Control .IMPORTANT! When using 2:1 serialization (TX_DATA_WIDTH = 2), each NIBBLESLICE tristate buffer can only be controlled through the combinatorial T input (TBYTE_CTL_<0-5> = T). Tristate control through the PHY_WREN input (TBYTE_CTL_x = PHY_WREN) is only possible for 8:1 and 4:1 serialization(TX_DATA_WIDTH = 8 and 4, respectively).PHY_RDEN is set up and used to control RX datapath gating is as follows:•PHY_RDEN controls accepting or rejecting the strobe entering on NIBBLESLICE[0] or from inter-byte or inter-nibble clocking, depending upon the settings of CONTINUOUS_DQS,RX_GATING, and RX_DATA_WIDTH. Always ensure the strobe has stabilized and BISC has completed before asserting PHY_RDEN. Refer to Controlling Built-in Self-Calibration for when BISC is considered completed.•When RX_DATA_WIDTH = don't care, RX_GATING = ENABLE, and CONTINUOUS_DQS =TRUE, then the four bits of PHY_RDEN are OR'd together and that output is used to control the gate. If the result of the OR operation is 1, the capture clock is accepted. If it is 0, then the capture clock is rejected. PHY_RDEN is synchronized to the capture clock for this attribute combination. When CONTINUOUS_DQS = TRUE, send 3 capture clock cycles before sending data.Chapter 2: XPHY Architecture•When RX_DATA_WIDTH = 4 or 8, RX_GATING = ENABLE, and CONTINUOUS_DQS = FALSE, set the following bits of PHY_RDEN to 1 to accept the strobe or 0 to reject the strobe.PHY_RDEN is synchronized to PLL_CLK for this attribute combination. Each bit of PHY_RDEN controls two UI worth of data:○If RX_DATA_WIDTH = 8: [3:0]○If RX_DATA_WIDTH = 4: [2][0]○If RX_DATA_WIDTH = 2: not supported•When RX_GATING = DISABLE the gate is always open, regardless of the value of RX_DATA_WIDTH, CONTINUOUS_DQS, or PHY_RDEN. In this scenario (RX_GATING = DISABLE), the strobe starts the deserialization in the RX datapath. Because of this, the strobe must be stable to ensure XPHY alignment.•When SERIAL_MODE = TRUE, tie all four bits of PHY_RDEN HighPHY_WREN is set up and used to control TX datapath gating as follows:•When TX_GATING = ENABLE, PHY_WREN gates the TX datapath of NIBBLESLICE[0], NIBBLESLICE[2], NIBBLESLICE[3], NIBBLESLICE[4], and NIBBLESLICE[5]. NIBBLESLICE[1] cannot be gated. Set the following bits of PHY_WREN to 0 to gate transmit data or 1 to not gate transmit data:○If TX_DATA_WIDTH = 8: [3:0]○If TX_DATA_WIDTH = 4: [2][0]○If TX_DATA_WIDTH = 2: not supported•Note that PHY_WREN can be used to control both TX datapath gating (if TX_GATING = ENABLE) and tristating (if TBYTE_CTL_# = PHY_WREN). However, only when PHY_WREN is used for tristating is it inverted and serialized prior to its use. When used for gating,PHY_WREN is serialized but is not inverted. Thus, when used for gating, PHY_WREN should be set to 1 to open the gate and 0 to close the gate. When used for tristating, PHY_WREN should be set to 0, which is then inverted to 1 to tristate the buffer. It follows that setting PHY_WREN to 1 for tristating results in the buffer not being tristated. See Controlling Tristate Control for more information on tristating.Other important points to keep in mind:•When turning the bus around, toggle the BS_RESET_CTRL.clr_gate bit then toggle the BS_RESET_CTRL.bs_reset bit. T oggling BS_RESET_CTRL.clr_gate clears the strobe path gating logic, helping to ensure proper alignment when combined with the NIBBLESLICE resetperformed through the toggling of BS_RESET_CTRL.bs_reset. Continue reading this section for the bs_reset/clr_gate sequence. See Register Interface Unit for more information onBS_RESET_CTRL. After the write to bs_reset is completed, data can be transmittedimmediately. For receivers, however, the first FIFO_EMPTY deassertion should be used to know when receiving valid data.•Before performing a bs_reset, set PHY_WREN and PHY_RDEN to 0 regardless of the TX_GATING or RX_GATING settings.•Setting CONTINUOUS_DQS = TRUE requires that three capture clock cycles be received prior to receiving data to prevent data loss.•If the TX-only interface data and clock, as well as bidirectional interface data, exist in the same nibble then TBYTE_CTL_# must be set to T for all pins in either interface, regardless of if they are part of the TX-only interface or bidirectional interface, and TX_GATING must be set to DISABLE•If the TX-only interface clock is placed in NIBBLESLICE[1], TX_GATING can be set to ENABLE because NIBBLESLICE[1] cannot be gated. In this scenario, TBYTE_CTL_# should be set to PHY_WREN for the bidirectional pins in the nibble, and TBYTE_CTL_# should be set to T for the TX-only pins in the nibble. If the TX-only interface clock is not placed on NIBBLESLICE[1], TX_GATING must be set to DISABLE, and TBYTE_CTL_# must be set to T for all pins in the interfaces, regardless of whether they are TX-only or bidirectional.•When TX_DATA_WIDTH = 2 or RX_DATA_WIDTH = 2, bidirectional support is limited to:○TX_GATING must be set to DISABLE.○RX_GATING can be set to ENABLE, but only when CONTINUOUS_DQS is also set to TRUE.is only supported through the T port (TBYTE_CTL_# = T).○TristatingT o perform a clr_gate and bs_reset sequence to turn the bus around, do the following:1.Assert BS_RESET_CTRL.clr_gate through the RIU.2.Deassert BS_RESET_CTRL.clr_gate through the RIU. The strobe path gating logic is now clear.3.If PHY_WREN and PHY_RDEN have not already been set to 0, they must be set to 0 beforecontinuing with this step. Assert BS_RESET_CTRL.bs_reset, which resets NIBBLESLICEs not masked by BS_RST_MASK.bs_reset_mask. While bs_reset is asserted, the TX IOBs ofNIBBLESLICEs not masked by BS_RST_MASK.bs_reset_mask are set to the value of their associated TX_INIT_# attribute. Keep BS_RESET_CTRL.bs_reset asserted for a minimum number of clock cycles based on the TX_DATA_WIDTH and RX_DATA_WIDTH attributes:•For data width of 8: 1 CTRL_CLK cycle + 72 PLL_CLK cycles•For data width of 4: 1 CTRL_CLK cycle + 40 PLL_CLK cycles•For data width of 2: 1 CTRL_CLK cycle + 24 PLL_CLK cycles4.Deassert BS_RESET_CTRL.bs_reset. After the write to bs_reset is completed, data can betransmitted immediately. For receivers, however, the first FIFO_EMPTY deassertion should be used to know when receiving valid data. PHY_RDEN and PHY_WREN can now bechanged from 0.IMPORTANT! If receiving a strobe (implying CONTINUOUS_DQS = FALSE) and RX_GATING = ENABLE,bitslip is not needed. For all other cases, bitslip is needed for word alignment.Related InformationControlling Tristate Control。
FPGA可编程逻辑器件芯片XC2S400-4FG456C中文规格书
550
550
MHz
FX100T devices
PLL Maximum Output Frequency for FX130T devices
500
450
N/A
MHz
FOUTMIN TEXTFDVAR RSTMINPULSE FPFDMAX FPFDMIN TFBDELAY
PLL Maximum Output Frequency for LX220T, LX330T, SX95T, SX240T, and FX200T devices PLL Minimum Output Frequency(5) External Clock Feedback Variation Minimum Reset Pulse Width Maximum Frequency at the Phase Frequency Detector Minimum Frequency at the Phase Frequency Detector Maximum Delay in the Feedback Path
Outputs Clocks (High Frequency Mode)
32.00 135.00 64.00 270.00
2.0 90.00 32.00 160.00
32.00 120.00 64.00 240.00
2.0 80.00 32.00 140.00
32.00 120.00 64.00 240.00
0.36
TAXD
AX inputs to DMUX output
0.62
TBXB
BX inputs to BMUX output
0.41
Speed Grade
-2I
FPGA可编程逻辑器件芯片XC2V250-4FG456I中文规格书
Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1TAP ControllerFigure3-2 diagrams a 16-state finite state machine. The four TAP pins control how data isscanned into the various registers. The state of the TMS pin at the rising edge of TCKdetermines the sequence of state transitions. There are two main sequences, one forshifting data into the data register and the other for shifting an instruction into theinstruction register.A transition between the states only occurs on the rising edge of TCK, and each state has adifferent name. The two vertical columns with seven states each represent the InstructionPath and the Datapath. The data registers operate in the states whose names end with"DR," and the instruction register operates in the states whose names end in "IR." The statesare otherwise identical.The operation of each state is described below.Test-Logic-Reset:All test logic is disabled in this controller state, enabling the normal operation of the IC.The TAP controller state machine is designed so that regardless of the initial state of thecontroller, the Test-Logic-Reset state can be entered by holding TMS High and pulsingTCK five times. Consequently, the Test Reset (TRST) pin is optional.Run-Test-Idle:In this controller state, the test logic in the IC is active only if certain instructions arepresent. For example, if an instruction activates the self test, then it is executed when thecontroller enters this state. The test logic in the IC is idle otherwise.Select-DR-Scan:This controller state controls whether to enter the Datapath or the Select-IR-Scan state.Select-IR-Scan:This controller state controls whether or not to enter the Instruction Path. The controllercan return to the Test-Logic-Reset state otherwise.Capture-IR:In this controller state, the shift register bank in the Instruction Register parallel loads apattern of fixed values on the rising edge of TCK. The last two significant bits must alwaysbe 01.Shift-IR:In this controller state, the instruction register gets connected between TDI and TDO, andthe captured pattern gets shifted on each rising edge of TCK. The instruction available onthe TDI pin is also shifted in to the instruction register.Exit1-IR:This controller state controls whether to enter the Pause-IR state or Update-IR state.Pause-IR:This state allows the shifting of the instruction register to be temporarily halted.Exit2-DR:This controller state controls whether to enter either the Shift-IR state or Update-IR state.Update-IR:In this controller state, the instruction in the instruction register is latched to the latch bankof the Instruction Register on every falling edge of TCK. This instruction becomes thecurrent instruction after it is latched.Configuration Flows Using JTAGFigure 3-9:IEEE 1532 Configuration FlowChapter 5:Dynamic Reconfiguration Port (DRP)Readback Command Sequences13.Write the RCRC command, and write one NOOP command.14.Write the DESYNCH command.15.Write at least 64 bits of NOOP commands to flush the packet buffer. Continue sendingCCLK pulses until DONE goes High.Table7-2 shows the readback command sequence.Table 7-2:Shutdown Readback Command Sequence (SelectMAP)Step SelectMAP Port Direction Configuration Data Explanation1Write FFFFFFFF Dummy Word 000000BB Bus Width Sync Word 11220044Bus Width Detect FFFFFFFF Dummy WordAA995566Sync Word2Write20000000Type 1 NOOP Word 03Write 30008001Type 1 Write 1 Word to CMD 0000000B SHUTDOWN Command 20000000Type 1 NOOP Word 04Write 30008001Type 1 Write 1 Word to CMD 00000007RCRC Command20000000Type 1 NOOP Word 05Write 20000000Type 1 NOOP Word 0 20000000Type 1 NOOP Word 0 20000000Type 1 NOOP Word 0 20000000Type 1 NOOP Word 0 20000000Type 1 NOOP Word 06Write 30008001Type 1 Write 1 Word to CMD 00000004RCFG Command20000000Type 1 NOOP Word 07Write 30002001Type 1 Write 1 Word to FAR 00000000FAR Address = 000000008Write 28006000Type 1 Read 0 Words from FDRO 48024090Type 2 Read 147,600 Words from FDRO9Write 20000000Type 1 NOOP Word 0 ...Type 1 31 more NOOPs Word 010Read 00000000Packet Data Read FDRO Word 0 ...00000000Packet Data Read FDRO Word 14759911Write20000000Type 1 NOOP Word 0。
FPGA可编程逻辑器件芯片XC2VP4-5FG456I中文规格书
Dedicated
Active-High signal indicating configuration is complete: 0 = FPGA not configured 1 = FPGA configured
INIT_B
Input or Output, Open-Drain
Input
Dedicated Active-Low asynchronous full-chip reset
FS[2:0] CCLK
Input
DualPurpose
SPI Variant Select pins, sampled by the INIT_B rising edge. They are multiplexed with the DATA[2:0] pins.
Dedicated
Before the Mode pins are sampled, INIT_B is an input that can be held Low to delay configuration. After the Mode pins are sampled, INIT_B is an open-drain active Low output indicating whether a CRC error occurred during configuration:
Mode
Figure 2-19: Bit Ordering
Virtex-5 FPGA Configuration Guide UG191 (v3.13) July 28, 2020
SPI Configuration Interface
When DCI match wait or DCM lock wait is enabled before the DONE release cycle during startup, the FPGA continues to clock in data until the startup wait condition is met and DONE is released. See “MultiBoot Bitstream Spacing” in Chapter 8 for considerations specific to MultiBoot Configuration.
FPGA可编程逻辑器件芯片XC2V1000-4FGG456C中文规格书
Linux Device DriverThe Linux device driver has the following character device interfaces:•User character device for access to user components.•Control character device for controlling DMA/Bridge Subsystem for PCI Express®components.•Events character device for waiting for interrupt events.•SGDMA character devices for high performance transfers.The user accessible devices are as follows:•XDMA0_control: Used to access DMA/Bridge Subsystem for PCI Express® registers.•XDMA0_user: Used to access AXI-Lite master interface.•XDMA0_bypass: Used to access DMA Bypass interface.•XDMA0_events_*: Used to recognize user interrupts.Using the DriverThe XDMA drivers can be downloaded from the Xilinx DMA IP Drivers page.Interrupt ProcessingLegacy InterruptsThere are four types of legacy interrupts: A, B, C and D. You can select any interrupts in the PCIe Misc tab under Legacy Interrupt Settings. You must program the corresponding values for both the IRQ Block Channel Vector (see IRQ Block Channel Vector Number (0xA0)) and the IRQ Block User Vector (see IRQ Block User Vector Number (0x80)). Values for each legacy interrupts are A = 0, B = 1, C = 2 and D = 3. The host recognizes interrupts only based on these values.MSI InterruptsFor MSI interrupts, you can select from 1 to 32 vectors in the PCIe Misc tab under MSICapabilities, which consists of a maximum of 16 usable DMA interrupt vectors and a maximum of16 usable user interrupt vectors. The Linux operating system (OS) supports only 1 vector. Otheroperating systems might support more vectors and you can program different vectors values in the IRQ Block Channel Vector (see IRQ Block Channel Vector Number (0xA0)) and in the IRQBlock User Vector (see IRQ Block User Vector Number (0x80)) to represent different interruptsources. The Xilinx® Linux driver supports only 1 MSI vector.MSI-X InterruptsThe DMA supports up to 32 different interrupt source for MSI-X, which consists of a maximum of 16 usable DMA interrupt vectors and a maximum of 16 usable user interrupt vectors. TheDMA has 32 MSI-X tables, one for each source (see MSI-X Vector Table and PBA (0x00–0xFE0)).For MSI-X channel interrupt processing the driver should use the Engine’s Interrupt Enable Mask for H2C and C2H (see H2C Channel Interrupt Enable Mask (0x90) or Table C2H ChannelInterrupt Enable Mask (0x90)) to disable and enable interrupts.User InterruptsThe user logic must hold usr_irq_req active-High even after receiving usr_irq_ack (acks) to keep the interrupt pending register asserted. This enables the Interrupt Service Routine (ISR) within the driver to determine the source of the interrupt. Once the driver receives userinterrupts, the driver or software can reset the user interrupts source to which hardware should respond by deasserting usr_irq_req.Example H2C FlowIn the example H2C flow,loaddriver.sh loads devices for all available channels. Thedma_to_device user program transfers data from host to Card.The example H2C flow sequence is as follows:1.Open the H2C device and initialize the DMA.2.The user program reads the data file, allocates a buffer pointer, and passes the pointer towrite function with the specific device (H2C) and data size.3.The driver creates a descriptor based on input data/size and initializes the DMA withdescriptor start address, and if there are any adjacent descriptor.4.The driver writes a control register to start the DMA transfer.Appendix A: Application Software Development5.The DMA reads descriptor from the host and starts processing each descriptor.6.The DMA fetches data from the host and sends the data to the user side. After all data istransferred based on the settings, the DMA generates an interrupt to the host.7.The ISR driver processes the interrupt to find out which engine is sending the interrupt andchecks the status to see if there are any errors. It also checks how many descriptors areprocessed.8.After the status is good, the drive returns transfer byte length to user side so it can check forthe same.Example C2H FlowIn the example C2H flow,loaddriver.sh loads the devices for all available channels. Thedma_from_device user program transfers data from Card to host.The example C2H flow sequence is as follow:1.Open device C2H and initialize the DMA.2.The user program allocates buffer pointer (based on size), passes pointer to read functionwith specific device (C2H) and data size.3.The driver creates descriptor based on size and initializes the DMA with descriptor startaddress. Also if there are any adjacent descriptor.4.The driver writes control register to start the DMA transfer.5.The DMA reads descriptor from host and starts processing each descriptor.6.The DMA fetches data from Card and sends data to host. After all data is transferred basedon the settings, the DMA generates an interrupt to host.7.The ISR driver processes the interrupt to find out which engine is sending the interrupt andchecks the status to see if there are any errors and also checks how many descriptors areprocessed.8.After the status is good, the drive returns transfer byte length to user side so it can check forthe same.。
FPGA可编程逻辑器件芯片XC2V1000-4FGG256I中文规格书
13.The test case then disables the transfer by deasserting the Run bit (bit 0) in the Controlregister for the H2C and C2H engine (0x0004 and 0x1004).When the transfer is started, one H2C and one C2H descriptor are transferred in Descriptor bypass interface and after that DMA transfers are performed as explained in above section. Descriptor is setup for 64 bytes transfer only.Simulation UpdatesFollowing is an overview of how existing root port tasks can be modified to exercise multi-channels, and multi descriptor cases.Multi-Channels Simulation, Example Channel 1 H2C and C2H1.Create an H2C Channel 1 descriptor in the Host memory address that is different than theH2C and C2H Channel 0 descriptor.2.Create a C2H Channel 1 descriptor in the Host memory address that is different than theH2C and C2H Channel 0 and H2C Channel 1 descriptor.3.Create transfer data (128 Bytes) for the H2C Channel 1 transfer in the Host memory whichdoes not overwrite any of the 4 descriptors in the Host memory (H2C and C2H Channel 0 and Channel 1 descriptors), and H2C Channel 0 data.4.Also make sure the H2C data in the Host memory does not overlap the C2H data transferspace for both C2H Channel 0 and 1.5.Write the descriptor starting address to H2C Channel 0 and 1.6.Enable multi-channel transfer by writing to control register (bit 0) of H2C Channel 0 and 1.7.Enable multi-channel transfer by writing to control register (bit 0) of C2H Channel 0 and 1.pare the data for correctness.The same procedure applies for AXI-Stream configuration. Refer to the above section for detailed explanation of the AXI-Stream transfer.Multi Descriptor Simulation1.Create a transfer of 256 bytes data (incremental or any data). Split the data into two 128bytes of data section. First, the data starts at address S1, and second, 128 bytes starts at address S2.2.Create a new descriptor (named DSC_H2C_1) in the Host memory address at DSC1.3.The DSC_H2C_1 descriptor has 128 bytes for DMA transfer, Host address S1 (source) anddestination address D1 (card).4.Create a new descriptor (named DSC_H2C_2) in the Host memory at address DSC2 that isdifferent from DSC_H2C_1 Descriptor.5.The DSC_H2C_2 descriptor has 128 bytes for DMA transfer, Host address S2 (source) anddestination address D2 (card).6.Link these two descriptors by adding next descriptor address in DSC_H2C_1. Write DSC2 innext descriptor field.7.Wire the descriptor starting address to H2C Channel 0.8.Enable DMA transfer for H2C Channel 0 by writing the Run bit in Control register 0x0004. Test TasksTable 135: Test TasksName DescriptionTSK_INIT_DATA_H2C This task generates one descriptor for H2C engine and initializes source data inhost memory.TSK_INIT_DATA_C2H This task generates one descriptor for C2H engine.TSK_XDMA_REG_READ This task reads the DMA Subsystem for PCIe register.TSK_XDMA_REG_WRITE This task writes the DMA Subsystem for PCIe register.COMPARE_DATA_H2C This task compares source data in the host memory to destination data writtento block RAM. This task is used in AXI4 Memory Mapped simulation. COMPARE_DATA_C2H This task compares the original data in the host memory to the data C2H enginewriting to host. This task is used in AXI4 Memory Mapped simulation.TSK_XDMA_FIND_BAR This task finds XDMA configuration space between different enabled BARs (BAR0to BAR6).For other PCIe-related tasks, see the “T est Bench” chapter in the 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054), Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023), UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156), or UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).Appendix A Application Software DevelopmentThis section provides details about the Linux device driver and the Windows driver lounge that is provided with the core.Device DriversFigure 33: Device DriversLinux Kernel DriverUsage model Windows Kernel DriverUsage modelX24822-111220The above figure shows the usage model of Linux and Windows XDMA software drivers. The DMA/Bridge Subsystem for PCIe example design is implemented on a Xilinx ® FPGA, which is connected to an X86 host through PCI Express.•In the first use mode, the XDMA driver in kernel space runs on Linux, whereas the testapplication runs in user space.•In the second use mode, the XDMA driver runs in kernel space on Windows, whereas the test application runs in the user space.Appendix A: Application Software Development。
FPGA可编程逻辑器件芯片XC2V1000-4FG456C中文规格书
Chapter 6: Example Design The Run Block Automation dialog box has an Automation Level option, which can be set to IPLevel or Subsystem Level.•IP Level: When you select IP level automation, the Block Automation inserts the utility buffer for the sys_clk input, connects the sys_rst_n input and pcie_mgt output interface forthe XDMA IP, as shown in the following figure.Figure 29:IP Level Block Automation Array•Subsystem Level: When you select subsystem level automation, the Block Automation inserts the necessary sub IPs on the canvas and makes the necessary connections. In addition toconnecting the sys_clk and sys_rst_n inputs it also connects the pcie_mgt outputinterface and user_lnk_up, user_clk_heartbeat and user_resetn outputs. It insertsthe AXI interconnect to connect the Block Memory with the XDMA IP through the AXI BRAMcontroller. The AXI interconnect has one master interface and multiple slave interfaces whenthe AXI4-Lite master and AXI-MM Bypass interfaces are enabled in the Run Block Automation dialog box. The block automation also inserts Block Memories and AXI BRAM Controllerswhen the AXI4-Lite master and AXI-MM Bypass interfaces are enabled.PG195 (v4.1) April 29, 2021DMA/Bridge Subsystem for PCIe v4.1Send FeedbackChapter 6: Example DesignSubsystem Level Block AutomationFigure 30:User IRQ Example DesignThe user IRQ example design enables the host to connect to the AXI4-Lite Master interfacealong with the default DMA/Bridge Subsystem for PCI Express® example design. In the example design, the User Interrupt generator module and an external block RAM is integrated on thisAXI4-Lite interface. The host can use this interface to generate the user IRQ by writing to theregister space of the User Interrupt generator module and can also read/write to the external 1K block RAM. The following figure shows the example design.The example design can be generated using the following T cl command.set_property -dict [list r_irq_exdes {true}] [get_ips <ip_name>]PG195 (v4.1) April 29, 2021DMA/Bridge Subsystem for PCIe v4.1Send FeedbackFigure 31: User IRQ Example DesignX21787-052019 The register description is found in the following table.Table 133: Example Design RegistersRegisterOffset Register Name Access Type Description0x00Scratch Pad RW Scratch Pad0x04DMA BRAM Size RO User Memory Size connected to XDMA. Memory size = (2[7:4]) ([3:0]Byte)[7:4] – denotes the size in powers of 2.0 – 11 – 22 – 4…8 – 2569 – 512[3:0] – denotes unit.0 – Byte1 – KB2 – MB3 – GBFor example, if the register value is 21, the size is 4 KB. If the register value is 91, the size is 512 KB.0x08Interrupt Control Register RW Interrupt control register (write 1 to generateinterrupt).Interrupt Status register corresponding bit must be1 (ready) to generate interrupt. Also, reset thecorresponding bit after ISR is served.0x0C Interrupt Status Register RO Interrupt Status.1: ready0: Interrupt generation in progressChapter 6: Example DesignPG195 (v4.1) April 29, 2021DMA/Bridge Subsystem for PCIe v4.1Send Feedback。
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Virtex-II Electrical CharacteristicsVirtex-II™ devices are provided in -6, -5, and -4 speed grades, with -6 having the highest performance.Virtex-II DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -4 speed grade industrial device are the same as for a -4 speed gradecommercial device). However, only selected speed grades and/or devices might be available in the industrial range.All supply voltage and junction temperature specifications are representative of worst-case conditions. The parame-ters included are common to popular designs and typical applications. Contact Xilinx for design considerations requiring more detailed information.All specifications are subject to change without notice.Virtex-II DC CharacteristicsDS031-3 (v4.0) April 7, 2014Product SpecificationTable 1: Absolute Maximum Ratings SymbolDescription(1)UnitsV CCINT Internal supply voltage relative to GND –0.5 to 1.65V V CCAUX Auxiliary supply voltage relative to GND –0.5 to 4.0V V CCO Output drivers supply voltage relative to GND –0.5 to 4.0V V BA TT Key memory battery backup supply –0.5 to 4.0V V REF Input reference voltage–0.5 to V CCO + 0.5V V IN (3)Input voltage relative to GND (user and dedicated I/Os)–0.5 to V CCO + 0.5V V TS Voltage applied to 3-state output (user and dedicated I/Os)–0.5 to 4.0V T STGStorage temperature (ambient)–65 to +150°C T SOLMaximum soldering temperature (2)All regular FF/BF flip-chip and FG/BG/CS wire-bond packages+220°C Pb-free FGG456, FGG676, BGG575, and BGG728 wire-bond packages +250°C Pb-free FGG256 and CSG144 wire-bond packages+260°C T JMaximum junction temperature (2)+125°CNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.2.For soldering guidelines and thermal considerations, see the Device Packaging and Thermal Characteristics Guide information on the Xilinxwebsite.3.Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the device is not PCIcompliant.General Power Supply RequirementsProper decoupling of all FPGA power supplies is sessential. Consult Xilinx Application Note XAPP623 for detailed infor-mation on power distribution system design.V CCAUX powers critical resources in the FPGA. Thus, V CCAUX is especially susceptible to power supply noise. Changes in V CCAUX voltage outside of 200 mV peak to peak should take place at a rate no faster than 10 mV per milli-second. Techniques to help reduce jitter and period distor-DC Input and Output LevelsValues for V IL and V IH are recommended input voltages. Values for I OL and I OH are guaranteed over the recom-mended operating conditions at the V OL and V OH test points. Only selected standards are tested. These are cho-tion are provided in Xilinx Answer Record 13756.V CCAUX can share a power plane with 3.3V V CCO, but only if V CCO does not have excessive noise. Using simultaneously switching output (SSO) limits are essential for keeping power supply noise to a minimum. Refer to XAPP689, “Man-aging Ground B ounce in Large FPGAs,” to determine the number of simultaneously switching outputs allowed per bank at the package level.sen to ensure that all standards meet their specifications. The selected standards are tested at minimum V CCO with the respective V OL and V OH voltage levels shown. Other standards are sample tested.Table 5: Minimum Power On Current Required for Virtex-II DevicesDevice (mA)XC2V40, XC2V80,XC2V250, XC2V500XC2V1000XC2V1500XC2V2000 XC2V3000XC2V4000 XC2V6000 XC2V8000 I CCINTMIN2002503504005006508001100I CCAUXMIN100100100100100100100100I CCOMIN5050100100100100100100 Notes:1.Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Gradevalues by 1.25.2.I CCOMIN values listed here apply to the entire device (all banks).Table 6: DC Input and Output LevelsInput/Output StandardV IL V IH V OL V OH I OL I OH V, Min V, Max V, Min V, Max V, Max V, Min mA mALVTTL(1)–0.50.8 2.0 3.60.4 2.424–24 LVCMOS33–0.50.8 2.0 3.60.4V CCO–0.424–24 LVCMOS25–0.50.7 1.7 2.70.4V CCO–0.424–24 LVCMOS18–0.535% V CCO65% V CCO 1.950.4 V CCO–0.416–16 LVCMOS15–0.535% V CCO65% V CCO 1.70.4 V CCO–0.416–16 PCI33_3–0.530% V CCO50% V CCO V CCO + 0.510% V CCO90% V CCO Note 2Note 2 PCI66_3–0.530% V CCO50% V CCO V CCO + 0.510% V CCO90% V CCO Note 2Note 2 PCI–X–0.5Note 2Note 2Note 2Note 2Note 2Note 2Note 2 GTLP–0.5V REF–0.1V REF + 0.1V CCO + 0.50.6n/a36n/a GTL–0.5V REF–0.05V REF + 0.05V CCO + 0.50.4n/a40n/a HSTL I–0.5V REF–0.1V REF + 0.1V CCO + 0.50.4V CCO–0.48–8 HSTL II–0.5V REF–0.1V REF + 0.1V CCO + 0.50.4V CCO–0.416–16 HSTL III–0.5V REF–0.1V REF + 0.1V CCO + 0.50.4V CCO–0.424–8 HSTL IV–0.5V REF–0.1V REF + 0.1V CCO + 0.50.4V CCO–0.448–8Extended LVDS DC Specifications(LVDSEXT_33 & LVDSEXT_25)Table 9: Extended LVDS DC SpecificationsDC Parameter Symbol Conditions Min Typ Max UnitsSupply Voltage V CCO 3.3 or 2.5VOutput High voltage for Q and Q V OH R T = 100Ω across Q and Q signals 1.785VOutput Low voltage for Q and Q V OL R T = 100Ω across Q and Q signals0.705VDifferential output voltage (Q–Q),V ODIFF R T = 100Ω across Q and Q signals440820mV Q = High (Q–Q), Q = HighOutput common-mode voltage V OCM R T = 100Ω across Q and Q signals 1.125 1.200 1.375VDifferential input voltage (Q–Q),V IDIFF Common-mode input voltage = 1.25 V100350N/A mV Q = High (Q–Q), Q = HighInput common-mode voltage V ICM Differential input voltage = ±350 mV0.2 1.25V CCO – 0.5VDescription Device Used & SpeedGradeRegister-to-RegisterPerformance UnitsBasic Functions16-bit Address Decoder XC2V1000 -5398MHz 32-bit Address Decoder XC2V1000 -5291MHz 64-bit Address Decoder XC2V1000 -5274MHz 4:1 MUX XC2V1000 -5563MHz 8:1 MUX XC2V1000 -5454MHz 16:1 MUX XC2V1000 -5414MHz 32:1 MUX XC2V1000 -5323MHz Register to LUT to Register XC2V1000 -5613MHz。