MSP430中文数据手册
MSP430G2553学习笔记(数据手册)
MSP430G2553学习笔记（数据手册）MSP430G2553性能参数(DIP-20) 工作电压范围：1.8~3.6V。
5种低功耗模式。
16位的RISC结构，62.5ns指令周期。
超低功耗：运行模式-230µA；待机模式-0.5µA；关闭模式-0.1µA；可以在不到1µs的时间里超快速地从待机模式唤醒。
基本时钟模块配置：具有四种校准频率并高达16MHz的内部频率；内部超低功耗LF振荡器；32.768KHz晶体；外部数字时钟源。
两个16 位Timer_A，分别具有三个捕获/比较寄存器。
用于模拟信号比较功能或者斜率模数(A/D)转换的片载比较器。
带内部基准、采样与保持以及自动扫描功能的10位200-ksps 模数(A/D)转换器。
16KB闪存，512B的RAM。
16个I/O口。
注意：MSP430G2553无P3口！MSP430G2553的时钟基本时钟系统的寄存器DCOCTL-DCO控制寄存器DCOxDCO频率选择控制1MODxDCO频率校正选择，通常令MODx=0注意：在MSP430G2553上电复位后，默认RSEL=7，DCO=3，通过数据手册查得DCO频率大概在0.8~1.5MHz之间。
BCSCTL1-基本时钟控制寄存器1XT2OFF不用管，因为MSP430G2553内部没有XT2提供的HF时钟XTS不用管，默认复位后的0值即可DIV Ax设置ACLK的分频数00 /101 /210 /411 /8RSELxDCO频率选择控制2BCSCTL2-基本时钟控制寄存器2SELMxMCLK的选择控制位00 DCOCLK01 DCOCLK10 LFXT1CLK或者VLOCLK11 LFXT1CLK或者VLOCLK DIVMx设置MCLK的分频数00 /101 /210 /411 /8SELSSMCLK的选择控制位0 DCOCLK1 LFXT1CLK或者VLOCLK DIVSx设置SMCLK的分频数00 /101 /210 /411 /8DCORDCO直流发生电阻选择，此位一般设00 内部电阻1 外部电阻BCSCTL3-基本时钟控制寄存器3XT2Sx不用管LFXT1Sx00 LFXT1选为32.768KHz晶振01 保留10 VLOCLK11 外部数字时钟源XCAPxLFXT1晶振谐振电容选择00 1pF01 6pF10 10pF11 12.5pFmsp430g2553.h中基本时钟系统的内容/************************************************************* Basic Clock Module************************************************************/#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */#define MOD0 (0x01) /* Modulation Bit 0 */#define MOD1 (0x02) /* Modulation Bit 1 */#define MOD2 (0x04) /* Modulation Bit 2 */#define MOD3 (0x08) /* Modulation Bit 3 */#define MOD4 (0x10) /* Modulation Bit 4 */#define DCO0 (0x20) /* DCO Select Bit 0 */#define DCO1 (0x40) /* DCO Select Bit 1 */#define DCO2 (0x80) /* DCO Select Bit 2 */#define RSEL0 (0x01) /* Range Select Bit 0 */#define RSEL1 (0x02) /* Range Select Bit 1 */#define RSEL2 (0x04) /* Range Select Bit 2 */#define RSEL3 (0x08) /* Range Select Bit 3 */#define DIVA0 (0x10) /* ACLK Divider 0 */#define DIVA1 (0x20) /* ACLK Divider 1 */#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ #define XT2OFF (0x80) /* Enable XT2CLK */#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */#define DIVS0 (0x02) /* SMCLK Divider 0 */#define DIVS1 (0x04) /* SMCLK Divider 1 */#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK /1:XT2CLK/LFXTCLK */#define DIVM0 (0x10) /* MCLK Divider 0 */#define DIVM1 (0x20) /* MCLK Divider 1 */#define SELM0 (0x40) /* MCLK Source Select 0 */#define SELM1 (0x80) /* MCLK Source Select 1 */#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */#define XT2S0 (0x40) /* Mode 0 for XT2 */#define XT2S1 (0x80) /* Mode 1 for XT2 */#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */ #define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */基本时钟系统例程(DCO)MSP430G2553在上电之后默认CPU执行程序的时钟MCLK来自于DCO时钟。
MSP430F413数据手册
D Wake-Up From Standby Mode in Less Than 6 μsD Frequency-Locked Loop (FLL+)D 16-Bit RISC Architecture, 125-ns Instruction Cycle TimeD 16-Bit Timer_A With Three or Five †Capture/Compare RegistersD Integrated LCD Driver for 96 Segments D On-Chip Comparator D Brownout DetectorDSupply Voltage Supervisor/Monitor −Programmable Level Detection on MSP430F415/417 Devices Only† Timer_A5 in ’F415 and ’F417 devices only− MSP430C412: 4KB ROM, 256B RAM − MSP430C413: 8KB ROM, 256B RAM − MSP430F412: 4KB + 256B Flash256B RAM − MSP430F413: 8KB + 256B Flash256B RAM − MSP430F415: 16KB + 256B Flash512B RAM − MSP430F417: 32KB + 256B Flash1KB RAM D Available in 64-Pin QFP (PM) and 64-Pin QFN (RTD/RGC) PackagesDFor Complete Module Descriptions,See the MSP430x4xx Family User’s Guide ,Literature Number SLAU056descriptionThe T exas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs.The MSP430x41x series are microcontroller configurations with one or two built-in 16-bit timers, a comparator,96 LCD segment drive capability, and 48 I/O pins.Typical applications include sensor systems that capture analog signals, convert them to digital values, and process the data and transmit them to a host system. The comparator and timer make the configurations ideal for industrial meters, counter applications, handheld meters, etc.This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Copyright © 2008, Texas Instruments IncorporatedPRODUCTION DATA information is current as of pub ication date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.AVAILABLE OPTIONSPACKAGED DEVICEST APLASTIC 64-PIN QFP (PM)PLASTIC 64-PIN QFN (RTD/RGC)−40°C to 85°CMSP430C412IPM MSP430C413IPM MSP430F412IPM MSP430F413IPM MSP430F415IPM MSP430F417IPMMSP430C412IRGC MSP430C413IRGC MSP430F412IRTD MSP430F413IRTD MSP430F415IRTD MSP430F417IRTDpin designation − MSP430x412, MSP430x413P1.5/TACLK/ACLK P 6.2P 6.1P 6.0R S T /N M I T C K T M S T D I /T C L K T D O /T D I P 1.0/T A 0P 1.1/T A 0/M C L K P 1.2/T A 1P 1.3/S V S O U T P 1.4P 4.4/S 5P 4.3/S 6P 4.2/S 7P 4.1/S 8P 4.0/S 9P 3.7/S 10P 3.6/S 11P 3.5/S 12P 3.4/S 13P 3.3/S 14P 3.2/S 15P 3.1/S 16P 3.0/S 17P 2.7/S 18P 2.6/C A O U T /S 19P 2.5/S 20P1.6/CA0P1.7/CA1P2.0/TA2P2.1P5.7/R33P5.6/R23P5.5/R13R03P5.4/COM3P5.3/COM2P5.2/COM1COM0P2.2/S23P2.4/S21P2.3/S22P6.3P6.4P6.5P6.6P6.7NC XIN XOUT NC NC P5.1/S0P5.0/S1P4.7/S2P4.5/S4P4.6/S3NC − No internal connection. External connection to V SS recommended.DV CC A V S SA V C CD V S Spin designation − MSP430x415, MSP430x417P1.5/TA0CLK/ACLK P 6.2P 6.1P 6.0R S T /N M I T C K T M S T D I /T C L K T D O /T D I P 1.0/T A 0.0P 1.1/T A 0.0/M C L K P 1.2/T A 0.1P 1.3/T A 1.0/S V S O U T P 1.4/T A 1.0P 4.4/S 5P 4.3/S 6P 4.2/S 7P 4.1/S 8P 4.0/S 9P 3.7/S 10P 3.6/S 11P 3.5/S 12P 3.4/S 13P 3.3/S 14P 3.2/S 15P 3.1/S 16P 3.0/S 17P 2.7/S 18P 2.6/C A O U T /S 19P 2.5/T A 1C L K /S 20P1.6/CA0P1.7/CA1P2.0/TA0.2P2.1/TA1.1P5.7/R33P5.6/R23P5.5/R13R03P5.4/COM3P5.3/COM2P5.2/COM1COM0P2.2/TA1.2/S23P2.4/TA1.4/S21P2.3/TA1.3/S22P6.3P6.4P6.5P6.6P6.7NC XIN XOUT NC P5.1/S0P5.0/S1P4.7/S2P4.5/S4P4.6/S3NC − No internal connection. External connection to V SS recommended.AV SS2DV CC A V S S 1A V C CD V S Sfunctional block diagram − MSP430x412, MSP430x413DV CC DV SS AV CC AV SSRST/NMIfunctional block diagram − MSP430x415, MSP430x417DV CC DV SS AV CC AV SSRST/NMITerminal Functions − MSP430x412, MSP430x413TERMINALNAME NO.I/O DESCRIPTIONAV CC64Positive terminal that supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive divider circuitry; must not power up prior to DV CC.AV SS62Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally connected to DV SS.DV CC1Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AV CC.DV SS63Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via AV CC/AV SS.NC7, 10, 11Not internally connected. Connection to V SS recommended.P1.0/TA053I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, compare: Out0 output/BSL transmitP1.1/TA0/MCLK52I/O General-purpose digital I/O / Timer_A, Capture: CCI0B input/MCLK output. Note: TA0 is only an input on this pin/BSL receive.P1.2/TA151I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 outputP1.3/SVSOUT50I/O General-purpose digital I/O / SVS: output of SVS comparatorP1.449I/O General-purpose digital I/OP1.5/TACLK/ ACLK48I/O General-purpose digital I/O / Input of Timer_A clock/output of ACLKP1.6/CA047I/O General-purpose digital I/O / Comparator_A inputP1.7/CA146I/O General-purpose digital I/O / Comparator_A inputP2.0/TA245I/O General-purpose digital I/O / Timer_A capture: CCI2A input, compare: Out2 outputP2.144I/O General-purpose digital I/OP2.2/S2335I/O General-purpose digital I/O / LCD segment output 23 (see Note 1)P2.3/S2234I/O General-purpose digital I/O / LCD segment output 22 (see Note 1)P2.4/S2133I/O General-purpose digital I/O / LCD segment output 21 (see Note 1)P2.5/S2032I/O General-purpose digital I/O / LCD segment output 20 (see Note 1)P2.6/CAOUT/S1931I/O General-purpose digital I/O / Comparator_A output/LCD segment output 19 (see Note 1) P2.7/S1830I/O General-purpose digital I/O / LCD segment output 18 (see Note 1)P3.0/S1729I/O General-purpose digital I/O / LCD segment output 17 (see Note 1)P3.1/S1628I/O General-purpose digital I/O / LCD segment output 16 (see Note 1)P3.2/S1527I/O General-purpose digital I/O / LCD segment output 15 (see Note 1)P3.3/S1426I/O General-purpose digital I/O / LCD segment output 14 (see Note 1)P3.4/S1325I/O General-purpose digital I/O / LCD segment output 13 (see Note 1)P3.5/S1224I/O General-purpose digital I/O / LCD segment output 12 (see Note 1)P3.6/S1123I/O General-purpose digital I/O / LCD segment output 11 (see Note 1)P3.7/S1022I/O General-purpose digital I/O / LCD segment output 10 (see Note 1)NOTE 1:LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.Terminal Functions − MSP430x412, MSP430x413 (Continued) TERMINALDESCRIPTIONI/ONAME NO.P4.0/S921I/O General-purpose digital I/O / LCD segment output 9 (see Note 1)P4.1/S820I/O General-purpose digital I/O / LCD segment output 8 (see Note 1)P4.2/S719I/O General-purpose digital I/O / LCD segment output 7 (see Note 1)P4.3/S618I/O General-purpose digital I/O / LCD segment output 6 (see Note 1)P4.4/S517I/O General-purpose digital I/O / LCD segment output 5 (see Note 1)P4.5/S416I/O General-purpose digital I/O / LCD segment output 4 (see Note 1)P4.6/S315I/O General-purpose digital I/O / LCD segment output 3 (see Note 1)P4.7/S214I/O General-purpose digital I/O / LCD segment output 2 (see Note 1)P5.0/S113I/O General-purpose digital I/O / LCD segment output 1 (see Note 1)P5.1/S012I/O General-purpose digital I/O / LCD segment output 0 (see Note 1)COM036O Common output. COM0−3 are used for LCD backplanesP5.2/COM137I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes.P5.3/COM238I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes.P5.4/COM339I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes.R0340I Input port of fourth positive (lowest) analog LCD level (V5)P5.5/R1341I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3) P5.6/R2342I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)P5.7/R3343I/O General-purpose digital I/O / Output port of most positive analog LCD level (V1)P6.059I/O General-purpose digital I/OP6.160I/O General-purpose digital I/OP6.261I/O General-purpose digital I/OP6.32I/O General-purpose digital I/OP6.43I/O General-purpose digital I/OP6.54I/O General-purpose digital I/OP6.65I/O General-purpose digital I/OP6.76I/O General-purpose digital I/ORST/NMI58I Reset input / Nonmaskable interrupt inputTCK57I Test clock. TCK is the clock input port for device programming and test.TDI/TCLK55I Test data input / Test clock input. The device protection fuse is connected to TDI.TDO/TDI54I/O Test data output port. TDO/TDI data output or programming data input terminal.TMS56I Test mode select. TMS is used as an input port for device programming and test.XIN8I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT9O Output terminal of crystal oscillator XT1.QFN Pad NA NA QFN package pad connection to V SS recommended.NOTE 2:LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.Terminal Functions − MSP430x415, MSP430x417TERMINALNAME NO.I/O DESCRIPTIONAV CC64Positive terminal that supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive divider circuitry; must not power up prior to DV CC.AV SS162Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally connected to DV SS.DV CC1Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AV CC.DV SS63Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via AV CC/AV SS.AV SS210Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally connected to DV SS.NC7, 11Not internally connected. Connection to V SS recommended.P1.0/TA0.053I/O General-purpose digital I/O / Timer0_A. Capture: CCI0A input, compare: Out0 output/BSL transmitP1.1/TA0.0/MCLK52I/O General-purpose digital I/O / Timer0_A. Capture: CCI0B input/MCLK output. Note: TA0 is only an input on this pin/BSL receiveP1.2/TA0.151I/O General-purpose digital I/O / Timer0_A, capture: CCI1A input, compare: Out1 outputP1.3/TA1.0/SVSOUT50I/O General-purpose digital I/O / Timer1_A, capture: CCI0B input/SVS: output of SVS comparator P1.4/TA1.049I/O General-purpose digital I/O / Timer1_A, capture: CCI0A input, compare: Out0 outputP1.5/TA0CLK/ACLK48I/O General-purpose digital I/O / input of Timer0_A clock/output of ACLKP1.6/CA047I/O General-purpose digital I/O / Comparator_A inputP1.7/CA146I/O General-purpose digital I/O / Comparator_A inputP2.0/TA0.245I/O General-purpose digital I/O / Timer0_A capture: CCI2A input, compare: Out2 outputP2.1/TA1.144I/O General-purpose digital I/O / Timer1_A, capture: CCI1A input, compare: Out1 outputP2.2/TA1.2/S2335I/O General-purpose digital I/O / Timer1_A, capture: CCI2A input, compare: Out2 output/LCD segment output 23 (see Note 1)P2.3/TA1.3/S2234I/O General-purpose digital I/O / Timer1_A, capture: CCI3A input, compare: Out3 output/LCD segment output 22 (see Note 1)P2.4/TA1.4/S2133I/O General-purpose digital I/O / Timer1_A, capture: CCI4A input, compare: Out4 output/LCD segment output 21 (see Note 1)P2.5/TA1CLK/S2032I/O General-purpose digital I/O / input of Timer1_A clock/LCD segment output 20 (see Note 1) P2.6/CAOUT/S1931I/O General-purpose digital I/O / Comparator_A output/LCD segment output 19 (see Note 1) P2.7/S1830I/O General-purpose digital I/O / LCD segment output 18 (see Note 1)P3.0/S1729I/O General-purpose digital I/O / LCD segment output 17 (see Note 1)P3.1/S1628I/O General-purpose digital I/O / LCD segment output 16 (see Note 1)P3.2/S1527I/O General-purpose digital I/O / LCD segment output 15 (see Note 1)P3.3/S1426I/O General-purpose digital I/O / LCD segment output 14 (see Note 1)P3.4/S1325I/O General-purpose digital I/O / LCD segment output 13 (see Note 1)P3.5/S1224I/O General-purpose digital I/O / LCD segment output 12 (see Note 1)P3.6/S1123I/O General-purpose digital I/O / LCD segment output 11 (see Note 1)P3.7/S1022I/O General-purpose digital I/O / LCD segment output 10 (see Note 1)NOTE 3:LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.Terminal Functions − MSP430x415, MSP430x417 (Continued) TERMINALDESCRIPTIONI/ONAME NO.P4.0/S921I/O General-purpose digital I/O / LCD segment output 9 (see Note 1)P4.1/S820I/O General-purpose digital I/O / LCD segment output 8 (see Note 1)P4.2/S719I/O General-purpose digital I/O / LCD segment output 7 (see Note 1)P4.3/S618I/O General-purpose digital I/O / LCD segment output 6 (see Note 1)P4.4/S517I/O General-purpose digital I/O / LCD segment output 5 (see Note 1)P4.5/S416I/O General-purpose digital I/O / LCD segment output 4 (see Note 1)P4.6/S315I/O General-purpose digital I/O / LCD segment output 3 (see Note 1)P4.7/S214I/O General-purpose digital I/O / LCD segment output 2 (see Note 1)P5.0/S113I/O General-purpose digital I/O / LCD segment output 1 (see Note 1)P5.1/S012I/O General-purpose digital I/O / LCD segment output 0 (see Note 1)COM036O Common output. COM0−3 are used for LCD backplanes.P5.2/COM137I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes.P5.3/COM238I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes.P5.4/COM339I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes.R0340I Input port of fourth positive (lowest) analog LCD level (V5)P5.5/R1341I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3) P5.6/R2342I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2)P5.7/R3343I/O General-purpose digital I/O / output port of most positive analog LCD level (V1)P6.059I/O General-purpose digital I/OP6.160I/O General-purpose digital I/OP6.261I/O General-purpose digital I/OP6.32I/O General-purpose digital I/OP6.43I/O General-purpose digital I/OP6.54I/O General-purpose digital I/OP6.65I/O General-purpose digital I/OP6.7/SVSIN6I/O General-purpose digital I/O / SVS, analog inputRST/NMI58I Reset input / Nonmaskable interrupt input portTCK57I Test clock. TCK is the clock input port for device programming and test.TDI/TCLK55I Test data input / Test clock input. The device protection fuse is connected to TDI.TDO/TDI54I/O Test data output port. TDO/TDI data output or programming data input terminal.TMS56I Test mode select. TMS is used as an input port for device programming and test.XIN8I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT9O Output terminal of crystal oscillator XT1.QFN Pad NA NA QFN package pad connection to V SS recommendedNOTE 4:LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.General-Purpose Register Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R12R13General-Purpose Register General-Purpose Register R6R7General-Purpose Register General-Purpose Register R8R9General-Purpose Register General-Purpose Register R10R11General-Purpose Register General-Purpose RegisterR14R15short-form descriptionCPUThe MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions,are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register,and constant generator, respectively. The remaining registers are general-purpose registers.Peripherals are connected to the CPU using data,address, and control buses, and can be handled with all instructions.instruction setThe instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.Table 1. Instruction Word FormatsDual operands, source-destination e.g. ADD R4,R5R4 + R5 −−−> R5Single operands, destination only e.g. CALL R8PC −−>(TOS), R8−−> PC Relative jump, un/conditionale.g. JNEJump-on-equal bit = 0Table 2. Address Mode DescriptionsADDRESS MODES DSYNTAX EXAMPLE OPERATION Register D D MOV Rs,Rd MOV R10,R11R10 −−> R11IndexedD D MOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5)−−> M(6+R6)Symbolic (PC relative)D D MOV EDE,TONI M(EDE) −−> M(TONI)Absolute D DMOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)Indirect D MOV @Rn,Y(Rm)MOV @R10,Tab(R6)M(R10) −−> M(Tab+R6)Indirect autoincrement D MOV @Rn+,Rm MOV @R10+,R11M(R10) −−> R11R10 + 2−−> R10ImmediateDMOV #X,TONIMOV #45,TONI #45 −−> M(TONI)NOTE:S = source D = destinationoperating modesThe MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.The following six operating modes can be configured by software:D Active mode (AM)−All clocks are active.D Low-power mode 0 (LPM0)−CPU is disabled.−ACLK and SMCLK remain active, MCLK is available to modules.−FLL+ loop control remains active.D Low-power mode 1 (LPM1)−CPU is disabled.−ACLK and SMCLK remain active. MCLK is available to modules.−FLL+ loop control is disabled.D Low-power mode 2 (LPM2)−CPU is disabled.−MCLK, FLL+ loop control, and DCOCLK are disabled.−DCO’s dc generator remains enabled.−ACLK remains active.D Low-power mode 3 (LPM3)−CPU is disabled.−MCLK, FLL+ loop control, and DCOCLK are disabled.−DCO’s dc generator is disabled.−ACLK remains active.D Low-power mode 4 (LPM4)−CPU is disabled.−ACLK is disabled.−MCLK, FLL+ loop control, and DCOCLK are disabled.−DCO’s dc generator is disabled.−Crystal oscillator is stopped.interrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITYPower-up External reset Watchdog Flash memoryWDTIFGKEYV(see Note 1)Reset0FFFEh15, highestNMIOscillator faultFlash memory access violationNMIIFG (see Notes 1 and 3)OFIFG (see Notes 1 and 3)ACCVIFG (see Notes 1 and 3)(Non)maskable(Non)maskable(Non)maskable0FFFCh14Timer1_A5 (see Note 4)TA1CCR0 CCIFG (see Note 2)Maskable0FFFAh13Timer1_A5 (see Note 4)TA1CCR1 to TA1CCR4CCIFGs and TA1CTL TAIFG(see Notes 1 and 2)Maskable0FFF8h12Comparator_A CMPAIFG Maskable0FFF6h11 Watchdog timer WDTIFG Maskable0FFF4h100FFF2h90FFF0h80FFEEh7 Timer_A3/Timer0_A3TACCR0/TA0CCR0 CCIFG(see Note 2)Maskable0FFECh6Timer_A3/Timer0_A3TACCR1/TA0CCR1,TACCR2/TA0CCR2 CCIFGsand TACLT/TA0CTL TAIFG(see Notes 1 and 2)Maskable0FFEAh5I/O port P1 (eight flags)P1IFG.0 to P1IFG.7(see Notes 1 and 2)Maskable0FFE8h40FFE6h30FFE4h2I/O port P2 (eight flags)P2IFG.0 to P2IFG.7(see Notes 1 and 2)Maskable0FFE2h1Basic Timer1BTIFG Maskable0FFE0h0, lowest NOTES: 1.Multiple source flags2.Interrupt flags are located in the module.3.(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.4.Implemented in MSP430x415 and MSP430x417 devices onlyspecial function registersMost interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.interrupt enable 1 and 2Address 0hAddress 1hWD TIE:Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode.OFIE:Oscillator fault interrupt enable NMIIE:Nonmaskable interrupt enable ACCVIE:Flash access violation interrupt enable BTIE:Basic Timer1 interrupt enableinterrupt flag register 1 and 2Address 02hAddress 3hWDTIFG:Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with V CC power-up,or a reset condition at the RST/NMI pin in reset mode.OFIFG:Flag set on oscillator fault NMIIFG:Set via RST/NMI pin BTIFG:Basic Timer1 interrupt flagmodule enable registers 1 and 2Address 04h/05h Legend:rw−0,1:Bit Can Be Read and Written. It Is Reset or Set by PUC.Bit Can Be Read and Written. It Is Reset or Set by POR.SFR Bit Not Present in Device.memory organizationMSP430F412MSP430F413MSP430F415MSP430F417MemoryInterrupt vector Code memorySizeFlashFlash4KB0FFFFh to 0FFE0h0FFFFh to 0F000h8KB0FFFFh to 0FFE0h0FFFFh to 0E000h16KB0FFFFh to 0FFE0h0FFFFh to 0C000h32KB0FFFFh to 0FFE0h0FFFFh to 08000hInformation memory SizeFlash256 Byte010FFh to 01000h256 Byte010FFh to 01000h256 Byte010FFh to 01000h256 Byte010FFh to 01000hBoot memory SizeROM1KB0FFFh to 0C00h1KB0FFFh to 0C00h1KB0FFFh to 0C00h1KB0FFFh to 0C00hRAM Size256 Byte02FFh to 0200h256 Byte02FFh to 0200h512 Byte03FFh to 0200h1 KB05FFh to 0200hPeripherals16-bit8-bit8-bit SFR 01FFh to 0100h0FFh to 010h0Fh to 00h01FFh to 0100h0FFh to 010h0Fh to 00h01FFh to 0100h0FFh to 010h0Fh to 00h01FFh to 0100h0FFh to 010h0Fh to 00h MSP430C412MSP430C413MemoryInterrupt vector Code memorySizeROMROM4KB0FFFFh to 0FFE0h0FFFFh to 0F000h8KB0FFFFh to 0FFE0h0FFFFh to 0E000hInformation memory Size NA NA Boot memory Size NA NARAM Size256 Byte02FFh to 0200h256 Byte02FFh to 0200hPeripherals16-bit8-bit8-bit SFR 01FFh to 0100h0FFh to 010h0Fh to 00h01FFh to 0100h0FFh to 010h0Fh to 00hbootstrap loader (BSL)The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature number SLAA089.BSL FUNCTION PM, RTD, RGC PACKAGE PINSData Transmit53 - P1.0Data Receive52 - P1.1flash memoryThe flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128bytes each. Each segment in main memory is 512 bytes in size.D Segments 0 to n may be erased in one step, or each segment may be individually erased.D Segments A and B can be erased individually, or as a group with segments 0 to n.Segments A and B are also called information memory.D New devices may have some bytes programmed in the information memory (needed for test duringmanufacturing). The user should perform an erase of the information memory prior to the first use.32KB Main MemoryInformation Memory0FFFFh0FA00h 0FE00h 0FDFFh0FC00h 0FBFFh0F9FFh08400h 083FFh 08200h 081FFh01000h010FFh08000h 01080h 0107Fh16KB0FFFFh0FA00h 0FE00h 0FDFFh 0FC00h 0FBFFh 0F9FFh0C400h 0C3FFh 0C200h 0C1FFh 01000h010FFh 0C000h 01080h 0107Fh 8KB0FFFFh 0FA00h 0FE00h 0FDFFh 0FC00h 0FBFFh 0F9FFh0E400h 0E3FFh 0E200h 0E1FFh 01000h010FFh 0E000h 01080h 0107Fh 4KB 0FFFFh0FA00h 0FE00h 0FDFFh 0FC00h 0FBFFh 0F9FFh0F400h 0F3FFh 0F200h 0F1FFh 01000h010FFh 0F000h 01080h 0107FhperipheralsPeripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number SLAU056.oscillator and system clockThe clock system in the MSP430x41x family of devices is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals:D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.D Main clock (MCLK), the system clock used by the CPU.D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.brownout, supply voltage supervisorThe brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a fixed level or user selectable level (MSP430x415 & MSP430x417 only) and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).The CPU begins code execution after the brownout circuit releases the device reset. However, V CC may not have ramped to V CC(min) at that time. The user must ensure the default FLL+ settings are not changed until V CC reaches V CC(min). If desired, the SVS circuit can be used to determine when V CC reaches V CC(min).digital I/OThere are six 8-bit I/O ports implemented—ports P1 through P6.D All individual I/O bits are independently programmable.D Any combination of input, output, and interrupt conditions is possible.D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.D Read/write access to port-control registers is supported by all instructions.Basic Timer1Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.LCD driverThe LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.。
MSP430F2618TGQWTEP;中文规格书,Datasheet资料
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MSP430F2618- EP MIXED SIGNAL MICROCONTROLLER
SLAS632 -- DECEMBER 2008
functional block diagram
SLAS632 -- DECEMBER 2008
description (continued)
The MSP430F2618 is a microcontroller configuration with two built-in 16-bit timers, a fast 12-bit A/D converter, a comparator, dual 12-bit D/A converters, four universal serial communication interface (USCI) modules, DMA, and up to 64 I/O pins. Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
Copyright 2008, Texas Instruments Incorporated
POST OFFICE BOX 655303
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MSP430F2618- EP MIXED SIGNAL MICROCONTROLLER
D Brownout Detector D Bootstrap Loader D Serial Onboard Programming,
MSP430系列MCU选型手册
MSP430系列MCU选型手册msp430芯片选型中文手册指南F1XX系列Vcc1.8V-3.6V型号MSP430F1101A参数说明1KBflash,128BRam；slopeA/D；14个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）,比较器_A；20DW、PW封装型号MSP430F1111A参数说明2KBflash,128BRam；slopeA/D；14个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）,比较器_A；20DW、PW封装型号MSP430F1121A参数说明4KBflash,256BRam；slopeA/D；14个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）,比较器_A；20DW、PW封装型号MSP430F1122参数说明4KBflash,256BRam；5通道10bitA/D；14个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）,温度传感器；20DW、PW封型号MSP430F1132参数说明8KBflash,256BRam；5通道10bitAD；14个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；温度传感器；20DW、PW封型号MSP430F122参数说明4KBflash,256BRam；slopeA/D；22个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个USART接口，比较器A；28DW、PW封装型号MSP430F123参数说明8KBflash,256BRam；slopeA/D；22个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个USART接口，比较器A；28DW、PW封装型号MSP430F1222参数说明4KBflash,256BRam；8通道10bitA/D；22个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个USART接口；温度传感器；28DW、PW封装型号MSP430F1232参数说明8KBflash,256BRam；8通道10bitA/D；22个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个USART接口；温度传感器；28DW、PW封装型号MSP430F133参数说明8KBflash,256BRam；8通道12bitA/D；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B(3个捕获/比较寄存器）；1个USART接口；比较器_A；温度传感器；64PM封装型号MSP430F135参数说明16KBflash,512BRam；8通道12bitA/D；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B(3个捕获/比较寄存器）；1个USART接口；比较器_A；温度传感器；64PM封装型号MSP430F147参数说明32KBflash,1024BRam；8通道12bitA/D；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；温度传感器；64PM封装型号MSP430F1471参数说明32KBflash,1024BRam；slopeA/D；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；64PM封装型号MSP430F148参数说明48KBflash,2048BRam；8通道12bitA/D；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；温度传感器；64PM封装型号MSP430F1481参数说明48KBflash,2048BRam；slopeA/D；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；64PM封装型号MSP430F149参数说明60KBflash,2048BRam；8通道12bitA/D；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；温度传感器；64PM封装型号MSP430F1491参数说明60kflash,2048BRam；slopeA/D；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；64PM封装型号MSP430F155参数说明16KBflash,512BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B(3个捕获/比较寄存器）；1个USART接口；I2C；比较器_A；温度传感器；64PM封装型号MSP430F156参数说明24KBflash,512BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B(3个捕获/比较寄存器）；1个USART接口；I2C；比较器_A；温度传感器；64PM封装型号MSP430F157参数说明32KBflash,1024BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B(3个捕获/比较寄存器）；1个USART接口；I2C；比较器_A；温度传感器；64PM 封装型号MSP430F167参数说明32KBflash,1024BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；I2C；MPY；比较器_A；温度传感器；64PM封装型号MSP430F168参数说明48KBflash,2048BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；I2C；MPY；比较器_A；温度传感器；64PM封装型号MSP430F169参数说明60KBflash,2048BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；I2C；MPY；比较器_A；温度传感器；64PM封装型号MSP430F1610参数说明32KBflash,5120BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；I2C；MPY；比较器_A；温度传感器；64PM封装型号MSP430F1611参数说明48KBflash,10240BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B （7个捕获/比较寄存器）；2个USART接口；I2C；MPY；比较器_A；温度传感器；64PM封装型号MSP430F1612参数说明55kBflash,5120BRam；8通道12bitA/D；双12bitD/A；DMA；48个I/O口；16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B（7个捕获/比较寄存器）；2个USART接口；I2C；MPY；比较器_A；温度传感器；64PM封装F21X1系列Vcc1.8V-3.6V型号MSP430F2101参数说明1KBflash,128BRam；slopeA/D；16个I/O口；15/16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；比较器_A；BrownoutProtection；20DW、PW、DGV封装型号MSP430F2111参数说明2KBflash,128BRam；slopeA/D；16个I/O口；15/16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；比较器_A；BrownoutProtection；20DW、PW、DGV封装型号MSP430F2121参数说明4KBflash,256BRam；slopeA/D；16个I/O口；15/16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；比较器_A；BrownoutProtection；20DW、PW、DGV封装型号MSP430F2131参数说明8KBflash,256BRam；slopeA/D；16个I/O口；15/16位WDT；1个16位Timer_A(3个捕获/比较寄存器）；比较器_A；BrownoutProtection；20DW、PW、DGV封装F4XX系列Vcc1.8V-3.6VWithLCD驱动型号MSP430F412参数说明4KBflash,256BRam；slopeA/D；48个I/O口；96段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器）；比较器_A；64PM封装型号MSP430F413参数说明8KBflash,256BRam；slopeA/D；48个I/O口；96段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器）；比较器_A；64PM封装型号MSP430F415参数说明16kBflash,512BRam；slopeA/D；48个I/O 口；96段LCD；16位WDT；8bit基本定时器；1个16位Timer_A （3或5个捕获/比较寄存器）；比较器_A；64PM 封装型号MSP430F417参数说明32kBflash,1024BRam；slopeA/D；48个I/O口；96段LCD；16位WDT；8bit基本定时器；1个16位Timer_A（3或5个捕获/比较寄存器）；比较器_A；64PM 封装型号MSP430FE423参数说明8KBflash,256BRam；SD16A/D；Emeter计量模块；14个I/O口；128段LCD；16位WDT；8bit基本定时器；1个16位Timer_A（3个捕获/比较寄存器）；1个USART 接口；温度传感器；64PM封装型号MSP430FE425参数说明16KBflash,512BRam；SD16A/D；Emeter计量模块；14个I/O口；128段LCD；16位WDT；8bit基本定时器；1个16位Timer_A（3个捕获/比较寄存器）；1个USART 接口；温度传感器；64PM封装型号MSP430FE427参数说明32KBflash,1KBRam；SD16A/D；Emeter计量模块；14个I/O口；128段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器）；1个USART 接口；比较器_A；温度传感器；64PM封装型号MSP430F4250参数说明16KBflash,256BRam；32个I/O 口；56段LCD；SD16位ADC （具有内部参考电压）；12位DAC，1个16位Timer_A(3个捕获/比较寄存器）；温度传感器模块；电源检测功能；48DL封装型号MSP430F4260参数说明24KBflash,256BRam；32个I/O 口；56段LCD；SD16位ADC （具有内部参考电压）；12位DAC，1个16位Timer_A(3个捕获/比较寄存器）；温度传感器模块；电源检测功能；48DL封装型号MSP430F4270参数说明32KBflash,256BRam；32个I/O 口；56段LCD；SD16位ADC （具有内部参考电压）；12位DAC，1个16位Timer_A(3个捕获/比较寄存器）；温度传感器模块；电源检测功能；48DL封装型号MSP430FG437参数说明32KBflash,1024BRam；12通道12bitA/D；双12bitD/A；48个I/O口；DMA；128段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器)；1个16位Timer_B(3个捕获/比较寄存器)；1个USART接口；温度传感器；80PN 封装型号MSP430FG438参数说明48KBflash,2048BRam；12通道12bitA/D；双12bitD/A；48个I/O口；DMA；128段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器)；1个16位Timer_B(3个捕获/比较寄存器)；1个USART接口；温度传感器；80PN 封装型号MSP430FG439参数说明60KBflash,2048BRam；12通道12bitA/D；双12bitD/A；48个I/O口；DMA；128段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器)；1个16位Timer_B(3个捕获/比较寄存器)；1个USART接口；温度传感器；80PN 封装型号MSP430FW423参数说明8KBflash,256BRam；slopeA/D；流量测量ScanIF模块；48个I/O口；96段LCD；16位WDT；8bit 基本定时器；1个16位Timer_A(3或5个捕获/比较寄存器)；比较器_A；64PM封装型号MSP430FW425参数说明16KBflash,512BRam；slopeA/D；流量测量ScanIF模块；48个I/O口；96段LCD；16位WDT；8bit 基本定时器；1个16位Timer_A(3或5个捕获/比较寄存器)；比较器_A；64PM封装型号MSP430FW427参数说明32KBflash,1024BRam；slopeA/D；流量测量ScanIF模块；48个I/O口；96段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3或5个捕获/比较寄存器)；比较器_A；64PM封装型号MSP430F435参数说明16KBFlash,512BRam；8通道12bitA/D；48个I/O口；128/160段LCD；16位WDT；8bit基本定时器；16位Timer_A(3个捕获/比较寄存器）_A；16位Timer_B(3个捕获/比较寄存器）_B；1个USART接口；比较器_A；温度传感器；80PN/100PZ封装型号MSP430F436参数说明24KBFlash,1024KRam；8通道12bitA/D；48个I/O口；128/160段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B(3个捕获/比较寄存器）_B；1个USART接口；比较器_A；温度传感器；80PN/100PZ封装型号MSP430F437参数说明32KBFlash,1024KRam；8通道12bitA/D；48个I/O口；128/160段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器）_A；1个16位Timer_B(3个捕获/比较寄存器）_B；1个USART接口；比较器_A；温度传感器；80PN/100PZ封装型号MSP430F447参数说明32KBFlash,1024KRam；8通道12bitA/D；48个I/O口；160段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B （7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；温度传感器；100PZ 封装型号MSP430F448参数说明48KBflash,2048BRam；8通道12bitA/D；48个I/O口；160段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B （7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；温度传感器；100PZ 封装型号MSP430F449参数说明60KBflash,2048BRam；8通道12bitA/D；48个I/O口；160段LCD；16位WDT；8bit基本定时器；1个16位Timer_A(3个捕获/比较寄存器）；1个16位Timer_B （7个捕获/比较寄存器）；2个USART接口；MPY；比较器_A；温度传感器；100PZ 封装型号TSS721AD参数说明M-BUS总线型号TRF6901PT参数说明无线射频率收发芯片。
MSP430G2553用户手册中文
时钟
LF，
1
DCO，
VLO
LF，
1
DCO，
VLO
LF，
1
DCO，
VLO
LF，
1
DCO，
VLO
LF，
1
DCO，
VLO
I/O 封装类型
24
32 引脚 QFN 封装
28 引脚 24 TSSOP 封
装
20 引脚 16 TSSOP 封
装
16
20 引脚 PDIP 封装
24
32 引脚 QFN 封装
时钟
I/O 封装类型
16
512 2x TA3
8
8
512 2x TA3
8
4
256 2x TA3
8
2
256 2x TA3
8
1
256 2x TA3
8
24
32 引脚 QFN 封装
28 引脚
24 TSSOP 封
LF，
装
-
1
DCO，Βιβλιοθήκη VLO20 引脚16 TSSOP 封
装
16
20 引脚 PDIP 封装
24
32 引脚 QFN 封装
典型应用包括低成本传感器系统，此类系统负责捕获模拟信号、将之转换为数字值、随后对数据进行处理以进行显 示或传送至主机系统。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430f552X中文手册
MSP430F552X中文手册及例程（耐心开完，必有收获）一、先写一篇开个头：这样快速闯入MSP430学习过程进入各个电子产品公司的网站，招聘里面嵌入式占据了大半工程师职位。
广义的嵌入式无非几种：传统的什么51单片机、 MSP430称做嵌入式微控制器；ARM是嵌入式微处理器；当然还有DSP；FPGA。
我们现在就不说别的，就说MSP430单片机，多数想学MSP430的童鞋，对89C51内核系列的单片机是很熟悉的，为了加深对MSP430 系列单片机的认识吗，迅速闯入MSP430学习过程，就必须彻底了解MSP430单片机，我们不妨将51单片机和MSP430两者进行一下比较。
第一点， 51内核单片机是8 位单片机。
其指令是采用的被称为“ CISC ”的复杂指令集，共具有111 条指令。
而MSP430 单片机是16 位的单片机，采用了精简指令集（ RISC ）结构，只有简洁的27 条指令，大量的指令则是模拟指令，众多的寄存器以及片内数据存储器都可参加多种运算。
这些内核指令均为单周期指令，功能强，运行的速度快。
第二点，MCU主要分为两种工作模式：待机与执行。
51内核单片机正常情况下消耗的电流为mA级，在掉电状态下，其耗电电流仍约为3mA左右；即使在掉电方式下，电源电压可以下降到2V ，但是为了保存内部RAM 中的数据，还需要提供约50uA的电流。
而430单片机功耗是在uA级的，工作电流极小，并且超低功耗，关断状态下的电流仅为0.1μA，待机电流为0.8μA，常规模式下的(250μA／1MIPS@3V)，端口漏电流不足50 nA，并可零功耗掉电复位(BOR)。
另外，该芯片属低电器件，仅需1.8～3.6V电压供电，因而可有效降低系统功耗。
MSP430将低功耗模式扩展为7种，分别对应不同应用场合及任务的低功耗方式。
以睡眠模式为例，包括深度睡眠模式RTC：只有时钟在跑而其他都不动，目前，TI宣布其MSP430在RTC模式下最低功耗仅为360nA。
MSP430F149数据手册
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PM) MSP430F133IPM MSP430F135IPM MSP430F147IPM MSP430F1471IPM MSP430F148IPM MSP430F1481IPM MSP430F149IPM MSP430F1491IPM PLASTIC 64-PIN QFP (PAG) PLASTIC 64-PIN QFN (RTD) MSP430F133IRTD MSP430F135IRTD MSP430F147IRTD MSP430F1471IRTD MSP430F148IRTD MSP430F1481IRTD MSP430F149IRTD MSP430F1491IRTD
D Serial Communication Interface (USART),
Functions as Asynchronous UART or Synchronous SPI Interface − Two USARTs (USART0, USART1) — MSP430x14x(1) Devices − One USART (USART0) — MSP430x13x Devices Family Members Include: − MSP430F133: 8KB+256B Flash Memory, 256B RAM − MSP430F135: 16KB+256B Flash Memory, 512B RAM − MSP430F147, MSP430F1471†: 32KB+256B Flash Memory, 1KB RAM − MSP430F148, MSP430F1481†: 48KB+256B Flash Memory, 2KB RAM − MSP430F149, MSP430F1491†: 60KB+256B Flash Memory, 2KB RAM Available in 64-Pin Quad Flat Pack (QFP) and 64-pin QFN For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide, Literature Number SLAU049
MSP430F5系列中文手册 RTC 实时时钟A
MSP430F5系列16位超低功耗单片机模块原理第14章RTC 实时时钟A版本: 1.0日期: 2008.9.原文: TI slau208.pdf (5xxfamily User's Guide)翻译: 周欣南京信息工程大学编辑: DC 微控技术论坛版主注：以下文章是翻译TI slau208.pdf 文件中的部分内容。
由于我们翻译水平有限，有整理过程中难免有所不足或错误；所以以下内容只供参考.一切以原文为准。
文章更新详情请密切留意微控技术论坛。
Page 1 of 14第14章实时时钟A实时时钟模块提供了具有日历模式、灵活可编程闹钟和校准的时钟计数器。
这一章节介绍了实时时钟A模块。
实时时钟模块A执行于MSP430X5XX器件中。
14.1 实时时钟介绍实时时钟模块提供了一个具有可以配置成一般目的计数器的日历时钟。
实时时钟特点有：l可配置成实时时钟模式或者一般目的的计数器l在日历模式中提供了秒钟，分钟，小时，星期，日期，月份和年份l具有中断能力l实时时钟模式里可选择BCD码或者二进制格式l实时时钟模式里具有可编程闹钟l实时时钟模式里具有时间偏差的逻辑校正实时时钟框图见图14-1。
注意：实时时钟初始化实时时钟模块的大多数寄存器没有初始条件。
在使用这个模块之前，用户必须通过软件对寄存器进行配置。
Page 2 of 14Page 3 of 14图14-1 实时时钟14.2 实时时钟操作实时时钟模块可以被配置成具有日历作用的实时时钟或者是一个具有RTCMODE 比特一般目的的32位计数器。
14.2.1 计数器模式当RTCMODE 被重置时，计数器模式被选择。
在这个模式中，通过软件可以得到一个32位的计数器。
从日历模式切换到计数器模式是通过重置计数值（RCTNT1，RCTNT2，RCTNT3，RCTNT4），和预换算计数器（RT0PS，RT1PS）。
时钟的增量计数器可源于ACLK、SMCLK或者是分频之后的ACLK或SMCLK。
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MSP430混合信号微控制器数据手册产品特性●低电压范围：2.5V～5.5V●超低功耗——活动模式：330μA at 1MHz, 3V——待机模式：0.8μA——掉电模式（RAM数据保持）：0.1μA●从待机模式唤醒响应时间不超过6μs●16位精简指令系统，指令周期200ns●基本时钟模块配置——多种内部电阻——单个外部电阻——32kHz晶振——高频晶体——谐振器——外部时钟源●带有三个捕获/比较寄存器的16位定时器（Timer_A）●串行在线可编程●采用保险熔丝的程序代码保护措施●该系列产品包括——MSP430C111：2K字节ROM，128字节RAM——MSP430C112：4K字节ROM，256字节RAM——MSP430P112：4K字节OTP，256字节RAM●EPROM原型——PMS430E112：4KB EPROM, 256B RAM●20引脚塑料小外形宽体（SOWB）封装，20引脚陶瓷双列直插式（CDIP）封装（仅EPROM）●如需完整的模块说明，请查阅MSP430x1xx系列用户指南（文献编号：SLAU049产品说明TI公司的MSP43O系列超低功耗微控制器由一些基本功能模块按照不同的应用目标组合而成。
在便携式测量应用中，这种优化的体系结构结合五种低功耗模式可以达到延长电池寿命的目的。
MSP430系列的CPU采用16位精简指令系统，集成有16位寄存器和常数发生器，发挥了最高的代码效率。
它采用数字控制振荡器（DCO），使得从低功耗模式到唤醒模式的转换时间小于6μs.MSP430x11x系列是一种超低功耗的混合信号微控制器，它拥有一个内置的16位计数器和14个I/0引脚。
典型应用：捕获传感器的模拟信号转换为数据，加以处理后输出或者发送到主机。
作为独立RF传感器的前端是其另一个应用领域。
DW封装（顶视图）可用选型功能模块图管脚功能简介：1.CPUMSP430的CPU采用16位RISC架构，具有高度的应用开发透明性。
除了流程控制指令，所有的操作都以寄存器操作的形式进行，其中源操作数有七种寻址方式，目的操作数有四种寻址方式。
该CPU集成了16个寄存器，用于缩短指令执行时间可以在一个时钟周期内完成寄存器间操作。
其中R0-R3这四个寄存器被用作特殊功能寄存器，分别作为程序计数器、堆栈指针、状态寄存器、常数发生器，其余寄存器用作通用寄存器。
外围设备通过数据、抵制、控制总线与CPU相连，通过所有指令可以很容易的对它们进行控制。
2.指令集整个指令集由51条指令构成，具有三种格式和七种寻址方式。
每一条指令都既可以做字操作，又可做字节操作。
表1总结了三种指令格式并举例，寻址方式见表2表1 指令字格式表2 寻址方式说明3.工作模式MSP430有一个活动模式和五个软件可选的低功耗工作模式。
一个中断事件可以把系统从各种低功耗模式唤醒，响应中断请求并且从中断程序中返回原来的低功耗模式。
以下六种工作模式可以通过软件进行配置：1.活动模式（AM）：所有时钟均被激活。
2.低功耗模式0（LPM0）：CPU停止工作，外围模块继续工作，ACLK 和SMCLK有效，MCLK的环路控制无效。
3.低功耗模式1（LPM1）：CPU停止工作，外围模块继续工作，ACLK 和SMCLK有效，MCLK的环路控制无效，如果数字控制振荡器（DCO）没有被用于活动模式，其DC发生器被关闭。
4. 低功耗模式2（LPM2）：CPU停止工作，外围模块继续工作，ACLK 有效，SMCLK和MCLK环路控制无效，DCO的DC发生器关闭。
5. 低功耗模式3（LPM3）：CPU停止工作，外围模块继续工作，ACLK 有效，SMCLK和MCLK环路控制无效，DCO的DC发生器关闭。
6. 低功耗模式4（LPM4）：CPU停止工作，外围模块继续工作，晶体振荡器停止工作，SMCLK和MCLK环路控制无效，并且数字控制振荡器（DCO）的DC发生器被关闭。
4.中断向量地址中断向量和上电起始地址位于ROM中的0FFFFh-0FFE0H范围内，向量中包含各种中断处理程序的16位入口地址。
注释1：多源标志注释2：中断标志位于模块内部注释3：共有8个P2中断标志，但是在’11x系列中仅应用了6个P2的I/O引脚。
特殊功能寄存器（SFR）多数中断和模块的允许位集中在低地址空间，未分配功能的那些特殊功能寄存器位在器件中实际上并未提供，这样安排可以简化软件存取。
1.中断使能寄存器1WDTIE: 看门狗定时器中断使能位。
当看门狗定时器被配置在间隔定时器模式时激活，当选中看门狗模式时不激活。
OFIE：振荡器错误中断使能位。
NMIE: 非可屏蔽中断使能位。
2.中断标志寄存器1WDTIFG: 看门狗定时器溢出（看门狗模式下）或者保密密钥非法时置位，VCC上电或者复位模式下RST/NMI引脚引起复位时复位.OFIFG: 振荡器错误时置位.NMIFG: 通过RST/NMI引脚置位存储器组织外围设备外设通过数据、地址、控制总线与CPU相连，可以通过所有操作指令进行控制。
完整的模块说明请参阅MSP43Ox11xx系列用户手册（文献号：SLAU049）。
振荡器和系统时钟时钟系统由基本时钟模块支持，基本时钟模块包括一个内部数字控制振荡器、一个高频晶振和对一个32768Hz外部晶振的支持。
基本时钟模块的这种设计既满足了低系统开销的要求，又满足了低功耗的要求。
内部数字控制振荡器（DCO）提供了一个高速开启的时钟源，它尅在6μs内达到稳定。
基本时钟模块提供了一下几种时钟信号：1.辅助时钟（ACLK），由32768Hz外部晶体或者一个高频晶体产生2.主时钟（MCLK），供CPU使用的系统时钟3.子系统时钟（SMCLK），供外围模块使用的子系统时钟数字I/O共有两个8位的I/O接口---P1和P2（在外部引脚上只有6个P2I/O信号可用）：1.所有的单个I/O位均是独立可编程的2.允许任意组合输入、输出和中断条件3.P1口的所有8位和P2口的6位都可以用于处理外部中断处理4.可以使用所有指令读写端口控制的寄存器注释：外部引脚上只有P2口的6位，P2.0—P2.5，但为P2口分配了所有的控制位和数据位。
看门狗定时器看门狗定时器（WDT）模块的基本功能是当软件执行出现混乱时可以控制系统自动复位。
如果设定的溢出时间到了，系统将产生复位。
如果应用程序不需要看门狗功能，这个模块可以作为一个间隔定时器使用，当选择的定时时间到了以后，它可以产生一个定时中断。
定时器 A3定时器A3是一个带有3个捕获/比较寄存器的16位定时器/计数器。
定时器A3可以支持多重的捕获/比较、PWM输出、间隔计时。
定时器A3还具有很多中断能力。
中断可能产生自计数器溢出和每一个捕获/比较寄存器。
外围模块表绝对最大额定参数VCC—VSS电压…………………………………………………………-0.3V-----6V 任意引脚上的电压（见注释）……………………………………-0.3V---VCC+0.3V 任意端点二极管电流……………………………………………………………±2mA 存储温度（未编程芯片）……………………………………………-55℃---150℃存储温度（已编程芯片）……………………………………………-40℃----85℃注释：所有电压以VSS为参照。
JTAG熔断电压(VFB)允许超过绝对最大额定值。
熔断JTAG熔丝时电压加在TEST引脚上。
推荐工作环境图1：C版本频率与供电电压间的关系注释：最小处理器频率由系统时钟决定图2：P/E版本频率与供电电压关系注释：最小处理器频率由系统时钟决定在推荐供电电压范围和推荐工作温度下的电气性能（除非另外说明）供电电流（进入VCC）不包括外部电流注释：所有输入连接到VSS或VCC，输出悬空。
与系统频率相对应的活动模式下的电流消耗：与供电电压相对应的活动模式下的电流消耗：施密特触发式输入_P1和P2口标准输入RST/NMI，TCK，TMS，TDI输入Px.x,Tax注释：1.外部信号每次将中断标志置位，t int 周期和时间参数必须满足条件。
即使触发信号比t int短，也可能会使标志位置位。
为了确保标志可靠置位，信号周期和时间都应满足条件。
2.当满足最小的t cap时间和参数时，外部信号将触发捕获事件。
即便捕获信号小于t cap 也可能触发捕获事件。
为了确保获得16位定时器值和使标志位置位，周期和时间必须满足这些规范。
内部信号Tax,SMCLK at Timer_A泄露电流（参阅注释1）注释：1.除非另外说明，测量时对应引脚所加的电平为VSS或VCC2.数字端口引脚的泄露电流要单个测量。
端口引脚必须选择为输入并且没有选择上拉或下拉电阻。
输出 P2x,Tax输出P1口和P2口注释：1.对于所有输出组合，最大总电流I OH（max）和I OL（max）不能超过±12mA，以便输出电压满足输出电压下降标准。
2.对于所有输出组合，最大总电流I OH（max）和I OL（max）不能超过±36mA，以便输出电压满足输出电压下降标准。
可选电阻，独立可编程（参阅注释1）注释1：在标准OTP或者EPROM设备MSP430P112或MSP430E112中，用于上拉或下拉的可选电阻R optx 是不可编程的。
从低电压模式唤醒响应时间（LPMx）这个电压下，程序不能执行。
注释1：这些参数未进行实际产品测试注释1：这些参数未进行实际产品测试主要的DCO特性●个别设备有最小和最大工作频率。
f(DCOx0)到f(DCOx7)的特定参数对所有设备均是有效的。
● Rsel(n)选择的所有范围和Rsel(n+1)的重合。
● DCO控制位DCO0，DCO1，DCO2有一个由参数S DCO 定义的步长。
●调节控制位MOD0到MOD4选择在32个DCO时钟周期的周期里f(DCO+1)被使用多少次，在剩余的时钟周期里使用频率f(DCO).这个频率是一个如下所示的平均值：晶振，XIN，XOUT注释：1.晶体两端都需要连接电容，电容值由晶体制造商规定。
2.仅当使用一个外部逻辑水平时钟源时适用，使用晶体或谐振器时不适用。
应用信息输入输出电路带有施密特触发器的输入输出口P1，P1.0到P1.5注释：x为P1的位标识符，从0到3注释：1.ROM版本有可供选择的上拉或下拉电阻。
2.可选上拉或下拉电阻的熔丝只能在工厂编程。
输入输出电路（续）带有施密特触发器的输入输出口P1，P1.4到P1.7，及在线存取特性带有施密特触发器的输入输出口P2，P2.0到P2.4注释：x为P2口的位标示符，从0到4注释：1.ROM版本有可供选择的上拉或下拉电阻2.可选上拉或下拉电阻的熔丝只能在工厂编程带有施密特触发器的输入输出口P2，P2.5，供基本时钟模块使用的Rosc功能P2口，未连接的位P2.6和P2.7注释:x为P2口的位标识符6到7，在元件上没有与这两位对应的外部引脚注释：将P2口未连接的两位6和7用作中断标志是一种良好的应用方法，除了软件其他信号不会影响到这两个中断标志，从而它们被用作软件中断。