5大规模数字集成电路习题解答
集成电路制造技术习题解答(第5单元)
复习题1. ULSI 对多层互连系统的要求？答：可从金属导电层和绝缘介质层的材料特性，工艺特性，以及互连延迟时间等多个方面来分析ULSI 对多层互连系统的要求：1、缩短互连线延迟时间，通常用电阻电容（RC ）常数表征互连线延迟时间，有：ox m ox m t t l t wl wt l RC 2ρεερ=⋅= 其中，ρ为金属连线的电阻率；l 、w 、t m 分别为金属连线层的长度、宽度和厚度；为ε、t ox 分别为介质层的介电常数和厚度。
由公式式可知，金属导电层的电阻率越低，绝缘层的介电常数越小，互连线越短，互连线延迟时间也就短，电路速度也就越快。
2、金属导电材料的选取除了要求低电阻率之外，还应抗电迁移能力强，理化稳定性能、机械性能和电学性能在经过后续工艺及长时间工作之后保持不变，最好薄膜淀积和图形转移等加工工艺简单、且经济，制备的互连线台阶覆盖特性好、缺陷浓度低、薄膜应力小。
实际上完全满足上述要求的金属或金属性材料没有。
早期的ULSI 是采用铝及铝合金作为导电材料。
近年来随着工艺技术的发展，铜已成为金属导电材料的首选，在集成度更高的ULSI 中有取代铝及铝合金的趋势。
3、绝缘介质材料的选取除了要求介电常数低之外，还应击穿场强高、漏电流低、体电阻率和表面电阻率大（一般均应大于1015Ω·cm ），即电学性能好；不吸潮、对温度的承受能力在500℃以上、无挥发性残余物存在，即理化性能好；薄膜材料的应力低、与导电层的附着性好，即兼容性好；薄膜易制备、且缺陷密度低、易刻蚀、台阶覆盖特性好，即易于加工成型。
2. 简述多层互连工艺流程。
答：在互连工艺中，首先淀积介质层，通常是CVD-PSG ；接下来平坦化，即PSG 的热处理回流，以消除衬底表面因前面光刻等工艺造成的台阶；然后通过光刻形成接触孔和通孔；再进行金属化，如PVD-Al 填充接触孔和通孔，形成互连线；如果不是最后一层金属，继续进行下一层金属化的工艺流程，如果是最后一层金属，则积淀钝化层，通常是PECVD-Si 3N 4，互连工艺完成。
计算机教材课后习题参考答案
《大学计算机基础与计算思维》课后习题参考答案目录第1章计算、计算机与计算思维 (1)第2章数据的计算基础 (3)第3章计算机硬件系统 (5)第4章操作系统基础 (9)第5章算法与数据结构 (11)第6章程序设计及软件工程基础 (14)第7章数据库技术 (16)第8章计算机网络 (19)第9章信息安全与职业道德 (21)第10章计算软件 (24)第11章办公软件Office 2010 (25)算机科学与技术学院计算机基础教学部2015年9月第1章计算、计算机与计算思维1.1 举例说明可计算性和计算复杂性的概念。
答：对于给定的一个输入，如果计算机器能在有限的步骤内给出答案，这个问题就是可计算的。
数值计算、能够转化为数值计算的非数值问题（如语音、图形、图像等）都是可计算的。
计算复杂性从数学上提出计算问题难度大小的模型，判断哪些问题的计算是简单的，哪些是困难的，研究计算过程中时间和空间等资源的耗费情况，从而寻求更为优越的求解复杂问题的有效规则，例如著名的汉诺塔问题。
1.2 列举3种电子计算机出现之前的计算工具，并简述其主要特点。
答：（1）算盘通过算法口诀化，加快了计算速度。
（2）帕斯卡加法器通过齿轮旋转解决了自动进位的问题。
（3）机电式计算机Z-1，全部采用继电器，第一次实现了浮点记数法、二进制运算、带存储地址的指令等设计思想。
1.3 简述电子计算机的发展历程及各时代的主要特征。
答：第一代——电子管计算机（1946—1954年）。
这个时期的计算机主要采用电子管作为运算和逻辑元件。
主存储器采用汞延迟线、磁鼓、磁芯，外存储器采用磁带。
在软件方面，用机器语言和汇编语言编写程序。
程序的编写与修改都非常繁琐。
计算机主要用于科学和工程计算。
第二代——晶体管计算机（1954—1964年）。
计算机逻辑元件逐步由电子管改为晶体管，体积与功耗都有所降低。
主存储器采用铁淦氧磁芯器，外存储器采用先进的磁盘，计算机的速度和可靠性有所提高。
《超大规模集成电路设计》习题（含答案）
《超大规模集成电路设计》习题1．集成电路的发展过程经历了哪些发展阶段？划分集成电路的标准是什么？集成电路的发展过程:•小规模集成电路(Small Scale IC ，SSI)•中规模集成电路(Medium Scale IC ，MSI)•大规模集成电路(Large Scale IC ，LSI) •超大规模集成电路(Very Large Scale IC ，VLSI)•特大规模集成电路(Ultra Large Scale IC ，ULSI)•巨大规模集成电路(Gigantic Scale IC ，GSI ）2．超大规模集成电路有哪些优点？1. 降低生产成本VLSI 减少了体积和重量等,可靠性成万倍提高,功耗成万倍减少.2.提高工作速度VLSI 内部连线很短,缩短了延迟时间.加工的技术越来越精细.电路工作速度的提高,主要是依靠减少尺寸获得. 3. 降低功耗芯片内部电路尺寸小,连线短,分布电容小,驱动电路所需的功率下降.4. 简化逻辑电路芯片内部电路受干扰小,电路可简化.5.优越的可靠性采用VLSI 后，元件数目和外部的接触点都大为减少，可靠性得到很大提高。
6.体积小重量轻7.缩短电子产品的设计和组装周期一片VLSI 组件可以代替大量的元器件,组装工作极大的节省,生产线被压缩,加快了生产速度.3．简述双阱CMOS 工艺制作CMOS 反相器的工艺流程过程。
4．在VLSI 设计中，对互连线的要求和可能的互连线材料是什么？5．在进行版图设计时为什么要制定版图设计规则？划分集成电路规模的标准数字集成电路类别MOS IC 双极IC 模拟集成电路SSI ＜102＜100 ＜30 MSI 102～103100～500 30～100 LSI 103～105500～2000 100～300 VLSI 105～107＞2000 ＞300 ULSI 107～109GSI ＞109在芯片尺寸尽可能小的前提下，使得即使存在工艺偏差也可以正确的制造出IC，尽可能地提高电路制备的成品率6．版图验证和检查主要包括哪些方面？u DRC(Design Rule Check)：几何设计规则检查；对IC的版图做几何空间检查，保证能在特定的工艺条件下实现所设计的电路，并保证一定的成品率；u ERC(Electrical Rule Check)：电学规则检查；检查电源(power)/地(ground)的短路，浮空的器件和浮空的连线等指定的电气特性；u LVS(Loyout versus Schematic)：网表一致性检查；将版图提出的网表和原理图的网表进行比较，检查电路连接关系是否正确，MOS晶体管的长/宽尺寸是否匹配，电阻/电容值是否正确等；u LPE(Layout Parameter Extraction)：版图寄生参数提取；从版图中提取晶体管的尺寸、结点的寄生电容、连线的寄生电阻等参数，并产生SPICE 格式的网表，用于后仿真验证；u POSTSIM：后仿真，检查版图寄生参数对设计的影响；提取实际版图参数、电阻、电容，生成带寄生量的器件级网表，进行开关级逻辑模拟或电路模拟，以验证设计出的电路功能的正确性和时序性能等，并产生测试向量。
集成电路制造技术习题解答(第4单元)
复习题1.ULSI中对光刻技术的基本要求？答：一般来说，在ULSI中对光刻技术的基本要求包括五方面：①高分辨率。
随着集成电路集成度的不断提高，加工的线条越来越精细，要求光刻的图形具有高分辨率。
在集成电路工艺中，通常把线宽作为光刻水平的标志，一般也可以用加工图形线宽的能力来代表集成电路的工艺水平。
②高灵敏度的光刻胶。
光刻胶的灵敏度通常是指光刻胶的感光速度。
在集成电路工艺中为了提高产品的产量，希望曝光时间愈短愈好。
为了减小曝光所需的时间，需要使用高灵敏度的光刻胶。
光刻胶的灵敏度与光刻胶的成份以及光刻工艺条件都有关系，而且伴随着灵敏度的提高往往会使光刻胶的其它属性变差。
因此，在确保光刻胶各项属性均为优异的前提下，提高光刻胶的灵敏度已经成为了重要的研究课题。
③低缺陷。
在集成电路芯片的加工过程中，如果在器件上产生一个缺陷，即使缺陷的尺寸小于图形的线宽，也可能会使整个芯片失效。
通常芯片的制作过程需要经过几十步甚至上百步的工序，在整个工艺流程中一般需要经过10~20次左右的光刻，而每次光刻工艺中都有可能引入缺陷。
在光刻中引入缺陷所造成的影响比其他工艺更为严重。
由于缺陷直接关系到成品率，所以对缺陷的产生原因和对缺陷的控制就成为重要的研究课题。
④精密的套刻对准。
集成电路芯片的制造需要经过多次光刻，在各次曝光图形之间要相互套准。
ULSI中的图形线宽在1μm以下，因此对套刻的要求也就非常高。
一般器件结构允许的套刻精度为线宽的±10%左右。
这种要求单纯依靠高精度机械加工和人工手动操作已很难实现，通常要采用自动套刻对准技术。
⑤对大尺寸硅片的加工。
集成电路芯片的面积很小，即便对于ULSI的芯片尺寸也只有1~2cm2左右。
为了提高经济效益和硅片利用率，一般采用大尺寸的硅片，也就是在一个硅片上一次同时制作很多完全相同的芯片。
采用大尺寸的硅片带来了一系列的技术问题。
对于光刻而言，在大尺寸硅片上满足前述的要求难度更大。
而且环境温度的变化也会引起硅片的形变（膨胀或收缩），这对于光刻也是一个难题。
(完整版)集成电路设计复习题及解答
集成电路设计复习题绪论1．画出集成电路设计与制造的主要流程框架。
2．集成电路分类情况如何？集成电路设计1．层次化、结构化设计概念，集成电路设计域和设计层次2．什么是集成电路设计？集成电路设计流程。
（三个设计步骤：系统功能设计逻辑和电路设计版图设计）3．模拟电路和数字电路设计各自的特点和流程4．版图验证和检查包括哪些内容？如何实现？5．版图设计规则的概念，主要内容以及表示方法。
为什么需要指定版图设计规则？6．集成电路设计方法分类？（全定制、半定制、PLD）7．标准单元/门阵列的概念，优点/缺点，设计流程8．PLD设计方法的特点，FPGA/CPLD的概念9．试述门阵列和标准单元设计方法的概念和它们之间的异同点。
10．标准单元库中的单元的主要描述形式有哪些？分别在IC设计的什么阶段应用？11．集成电路的可测性设计是指什么？Soc设计复习题1.什么是SoC？2.SoC设计的发展趋势及面临的挑战？3.SoC设计的特点?4.SoC设计与传统的ASIC设计最大的不同是什么？5.什么是软硬件协同设计？6.常用的可测性设计方法有哪些？7. IP的基本概念和IP分类8.什么是可综合RTL代码?9.么是同步电路，什么是异步电路，各有什么特点？10.逻辑综合的概念。
11.什么是触发器的建立时间（Setup Time），试画图进行说明。
12.什么是触发器的保持时间（Hold Time），试画图进行说明。
13. 什么是验证，什么是测试，两者有何区别？14.试画图简要说明扫描测试原理。
绪论1、 画出集成电路设计与制造的主要流程框架。
2、集成电路分类情况如何？集成电路设计1． 层次化、结构化设计概念，集成电路设计域和设计层次分层分级设计和模块化设计．将一个复杂的集成电路系统的设计问题分解为复杂性较低的设计级别，⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨⎧⎪⎪⎪⎪⎩⎪⎪⎪⎪⎨⎧⎩⎨⎧⎩⎨⎧⎪⎪⎪⎪⎩⎪⎪⎪⎪⎨⎧⎪⎪⎪⎪⎪⎪⎩⎪⎪⎪⎪⎪⎪⎨⎧⎩⎨⎧⎪⎪⎪⎪⎩⎪⎪⎪⎪⎨⎧⎩⎨⎧⎪⎩⎪⎨⎧按应用领域分类数字模拟混合电路非线性电路线性电路模拟电路时序逻辑电路组合逻辑电路数字电路按功能分类GSI ULSI VLSI LSI MSI SSI 按规模分类薄膜混合集成电路厚膜混合集成电路混合集成电路B iCMOS B iMOS 型B iMOS CMOS NMOS PMOS 型MOS双极型单片集成电路按结构分类集成电路这个级别可以再分解到复杂性更低的设计级别；这样的分解一直继续到使最终的设计级别的复杂性足够低，也就是说，能相当容易地由这一级设计出的单元逐级组织起复杂的系统。
数字集成电路课后习题1-4章作业解析
VOH = VGG − VT = VDD − VT 0 + γ
(
(V
SB
+ 2 φf − 2 φf
))
= VGG − VT 0 − γ VOH + 2 φ f + γ 2 φ f = 1.6 − 0.4 − 0.2 VOH + 0.88 + 0.2 0.88 = 1.388 − 0.2 VOH + 0.88
QOX 6 ×1011 ×1.6 ×10−19 0.06 V = = COX 1.6 ×10−6 VT0 =−0.99 − (−0.88) − (−0.188) − 0.060 =+0.018 V
计算 PMOS 器件的阈值电压： kT N D 3 ×1017 = φFn = ln 0.026 ln = 0.44 V q ni 1.4 ×1010
VOL 2 (0.1×10−4 )(8 ×106 )(1.6 − VOL − 0.4) 2 1 270 1.2 0.4 V − − ( ) OL = 0.1 VOL 2 (1.6 − VOL − 0.4) + 0.6 1 + 0.6
+0.99 V φGC = φFn − φG ( gate ) = 0.44 + 0.55 = QB 0 3 ×10−7 = = +0.188 V QB 0 = 3 ×10−7 C / cm 2 COX 1.6 ×10−6 QOX 6 ×1011 ×1.6 ×10−19 = = 0.06 V COX 1.6 ×10−6 VT0 =0.99 − (+0.88) − (+0.188) − 0.060 =−0.138 V
VOH = 1.11V 由此可知，VGG 实际要大于 1.6 V，接近 1.7 V，才能使 VOH 达到 1.2 V。 计算 VOL 时忽略体效应， ∴
习题数电参考答案（终）
习题数电参考答案（终）第⼀章数字逻辑概论1.1 数字电路与数制信号1.1.1 试以表1.1.1所列的数字集成电路的分类为依据，指出下列IC器件属于何种集成度器件：（1）微处理器；（2）计数器；（3）加法器；（4）逻辑门；（5）4兆位存储器。
解：依照表1.1.1所⽰的分类，所列的五种器件：（1）、（5）属于⼤规模；（2）、（3）属于中规模；（4）属于⼩规模。
1.1.2⼀数字信号波形如图题1.1.2所⽰，试问该波形所代表的⼆进制数是什么？解：图题1.1.2所⽰的数字信号波形的左边为最⾼位（MSB），右边为最低位（LSB），低电平表⽰0，⾼电平表⽰1。
该波形所代表的⼆进制数为010110100。
1.1.3 试绘出下列⼆进制数的数字波形，设逻辑1的电压为5V，逻辑0的电压为0V。
（1）001100110011（2）0111010 （3）1111011101解：⽤低电平表⽰0，⾼电平表⽰1，左边为最⾼位，右边为最低位，题中所给的3个⼆进制数字的波形分别如图题1.1.3（a）、（b）、（c）所⽰，其中低电平为0V，⾼电平为5V。
1.1.4⼀周期性数字波形如图1.1.4所⽰，试计算：（1）周期；（2）频率；（3）占空⽐。
解：因为图题1.1.4所⽰为周期性数字波，所以两个相邻的上升沿之间持续的时间为周期，T=10ms。
频率为周期的倒数，f=1/T=1/0.01s=100Hz。
占空⽐为⾼电平脉冲宽度与周期的百分⽐，q=1ms/10ms×100%=10%。
1.2 数制1.2.1 ⼀数字波形如图1.2.1所⽰，时钟频率为4kHz，试确定：（1）它所表⽰的⼆进制数；（2）串⾏⽅式传送8位数据所需要的时间；（3）以8位并⾏⽅式传送的数据时需要的时间。
解：该波形所代表的⼆进制数为00101100。
时钟周期T=1/f=1/4kHz=0.25ms。
串⾏⽅式传送数据时，每个时钟周期传送1位数据，因此，传送8位数据所需要的时间t=0.25ms×8=2ms。
数字集成电路设计与系统分析答案
懂得1、Please illustrate the meaning of its voltage transfer characteristic to a logic gate, and describe the static behaviors showed in the voltage transfer characteristic curves.The electrical function of a gate is best expressed by its voltage transfer characteristic (VTC),which plots the output voltage as a function of the input voltage Vout=f(Vin).The high and low nominal voltage Voh and Vol;The gate or switching threshold voltage Vm,that is define as Vm=f(Vm)(The gate threshold voltage presents the midpoint of the switching characteristics,which is obtained when the output of a gate is short circuited to the input);The high and low input voltage Vih and Vil are defined by the point where the gain (=dVout/dVin)of the VTC equals -12、Please draw the voltage transfer characteristic curve of the inverter and label the static operation points in the VTC.3、Please describe the definition of noise margin and its physical significance(物理意义), then draw the figure of definition of noise margins.The noise margins represent the levels of noise that can be sustained(所允许的) when gates are cascaded. A measure of the sensitivity of a gate to noise is given by the noise margins NML(noise margin low) and NMH(noise margin high), which quantize the size of the legal “0” and “1”, respectively, and set a fixed maximum threshold on the noise value4、Please describe the meaning of the regenerative property and the conditions of a gate with regenerative property.A gate with regenerative property ensures that a disturbed signal converges back to a nominal voltage level after passing through a number of logical stages. The VTC should have a transient region (or undefined region) with a gain greater than 1 in absolute value, bordered by the two legal zones, where the gain should be less than 1 in absolute value5、What are the definitions of the fan-out and fan-in properties?The number that can be driven is termed the fan-out of circuit, that denotes the number of load gates N that are connected to the output of the driving gate. The fan-in of a gate is defined as the number of independent input nodes to the gate.6、How to describe the performance of a digital IC? Please illustrate the parameters used to characterize the transient performance of a logic family, and draw the associated figure of the definition of these parP ropagation delay time and rise/fall time can be used to characterize the transient performance of a logic family .Propagation delay time of a gate expresses the delay experienced by a signal when passing through a gate,which represent how quickly the gate responds to the changes at its inputs.Rise/fall time express how fast a signal transits between the different levels. Propagation delay time is defined as the period between the 50%transition points of the input and output signals.Rise/fall time is defined as the period between the 10% and 90% points of the total voltage transition at the output waveforms.1、Illustrate the basic structure and simple operation principle of MOS transistor.Four terminals:source, drain, gate, body; Vertical Structure: gate electrode, insulator, semiconductor substrate; Horizontal Structure: source region, channel region, drain region2、Illustrate the basic function of each terminal of MOS device, and describe the general terminal connections of NMOS and PMOS transistor, respectively.The source and the drain are the electrodes conducting the current. The gate electrode is thecontrolling terminal. The function of the body is secondaryIn NMOS devices, the source is defined as the n+ region which has a lower potential(电势) than the other n+ region, the drain. The source is the terminal with the higher potential in PMOS devices, The body is generally connected to a DC supply that is identical for all devices of the same type (GND for NMOS, VDD for PMOS).3、What does the transition (or input) characteristic of MOS transistor mean? And what conclusions we can find from the characteristic curve?It describes the relationship between the gate-source voltage and the drain-source current with the certain drain-source voltage .When the gate-source voltage is less than the threshold voltage, the conducting current is zero, that is, the NMOS transistor is in cutoff operation. When is larger than, the NMOS transistor is on.4、What does the current-voltage (or output) characteristic of MOS transistor mean? And what conclusions we can find from the I-V characteristic curve?.It describes the relationship between the drain-source voltage and the drain-source current with a certain gate-source voltageVgs > Vt , 0<VDS <VGS -VT : Linear modeThe inversion layer forms a continuous current path between the source and the drain.A drain current proportional to Vds will flow from the drain to the source through the conducting channel. The channel region acts as a voltage-controlled linear resister.5、Describe the operation modes of NMOS and PMOS transistors respectively, and define the corresponding ideal current equations.1、Explain the channel-length modulation, sub-threshold conduction, short-channel effect and narrow-channel effect. And illustrate their corresponding chief impacts on the device.This simple current equation prescribes a linear drain-bias dependence for the current in MOS transistors, determined by the empirical model parameter λ, called the channel-length modulation coefficientOne typical condition, which is due to the two-dimensional nature of channel current flow, is the sub-threshold conduction in small-geometry MOS transistors.As a working definition, a MOS transistor is called a short-channel device if its channel length is on the same order of magnitude as the depletion region thicknesses of the source and drain junctions.The short-channel effects that arise in this case are attributed to two physical phenomena: the limitations imposed on electron drift characteristics in the channel; the modification of the threshold voltage due to the shortening channel lengthMOS transistor that have channel widths on the same order of magnitude as the maxium depletion region thickness are defined as narrow channel devices.For MOSFET with small channel widths,the actual threshold voltage increases as a result of this extra depletion charge of the fringe depletion region.This fact is called narrow channel effect.2、Describe the three main components of the load capacitanceCL, when a logic gate is driving other fan-out gates. And sketch the capacitance model of NMOS transistor.Gate capacitances (of other inputs connected to out)Diffusion(or junction) capacitances (of drain/source regions)Routing capacitances (output to other inputs)1,Describe the basic structure and operation of a static CMOS inverter. Then draw theassociated transistor schematicThis structure consists of an enhancement-type NMOS transistor and an enhancement-type PMOS transistor, operating in complementary mode. So this configuration is called Complementary MOS (CMOS). The gate terminals of the PMOS and NMOS transistors are connected to form the inverter input. The drain terminals of the PMOS and NMOS transistors are connected to form the inverter output. The source and the substrate of the NMOS transistor are connected to the ground, while the source and body of PMOS transistor are connected to VDD The circuit topology is complementary push-pull in the sense that: For high input the NMOS transistor drives (pulls down) the output node while the PMOS transistor acts as the load, and for low input the PMOS transistor drives (pulls up) the output node while the NMOS transistor acts as the load.When the input is at VDD: The NMOS is on (conducting) while the PMOS is off (cut-off). A direct path exists between Vout and the ground node, resulting in a steady-state value of 0V at the output. When the input is at ground:The NMOS is off while the PMOS is on. A direct path exists between VDD and Vout, yielding a high output voltage (equal to VDD).Static CMOS logic:structure:The static CMOS style is really an extension of the static CMOS inverter to multiple inputs. A logic function in static CMOS must be implemented in both NMOS and PMOS transistors. It is the combination of the pull-up network(PUN) and the pull-down network(PDN). Each input always connects to PUN and PDN simultaneously. The function of the PUN is to provide a connection between the output and VDD anytime the output of the logic gate is meant to be 1 (based on the inputs). The function of the PDN is to connect the output to VSS when the output of the logic gate is meant to be 0.Opreation: The pull-down net should be “on” when the pull-up net is “off” and vice versa. For any given input combination, the output is connected either to VDD or to ground via a low-resistance path. A DC current path between the VDD and ground is not established for any of the input combinations. With the complementary nature of NMOS and PMOS, the pull-up or the pull-down is “on” alternately to implement the logic operation.Discuss the main problems for high fan-in static CMOS gates and the associated techniques for fast complex gates.tpHL = 0.69 Reqn(C1+2C2+3C3+4CL); Propagation delay deteriorates(恶化) rapidly as a function of fan-in quadratically in the worst case, Gates with a fan-in greater than 4 become excessively slow and must be avoided.tPLH increases linearly due to the linearly increasing value of the diffusion capacitance;tPHL increase quadratically due to the simultaneous increase the resistance and internal capacitance in serial part.Transistor sizing: as long as fan-out capacitance dominatesProgressive transistor sizing: This approach reduces the dominant resistance, while keeping the increase in capacitance within boundsTransfer gate:Configuration:The source and drain nodes serve as inputs and outputs, while the gate node serves as the control input, the body node is connected to the power/ground Operation: For NMOS transfer gate,it turns on while the gate control terminal goes high, and the input signal will be delivered to the output node; it turns off while the gate control terminal goes low, and the output node will be impedance.CMOS transmission gate:Configuration: The CMOS transmission gate consists of one NMOS and one PMOS transistor, with the source and drain connected in parallel; The gate voltages appliedto these two transistors are also set to be complementary signals. The substrate terminal of the NMOS transistor is connected to ground and the substrate terminal of the PMOS transistor is connected to Vdd.Operation: If the control signal C is logic-high (equal to Vdd), then both transistors are turned on and provide a low-resistance current path between the input and output nodes. If the control signal C is logic-low, then both transistors will be off, and the path between the input and output nodes will be in the high-impedance state. The weakness of one device is overcome by the strength of the other device, whether the output is transmitting a high or low value. This is a clear advantage of the CMOS transfer gate over the single transistor counterpart.DCVLS:Operation: Assume now that, for a given set of inputs, PDN1 conducts while PDN2 does not, and that Out and out are initially high and low, respectively. Turning on PDN1: Causes Out to be pulled down (below VDD−|VTP |); Out is in a high impedance state, as M2 and PDN2 are both turned off. At the point M2 turns on and starts charging out非to VDD — eventually turning off M1; This in turn enables Out to discharge all the way to GND.XOR/XNOR: When the signals A and B have the same values, there is one conducting path either AB or A非B非; Then the output F is pulled down;At the same time, the other pull-down paths connected to the F非are both turned off. When F is pulled down below VDD−|VTP |, M2 t urns on and starts charging F非to VDD —eventually turning off M1 and pulling down F to Gnd. When the signals A and B have the different values, there is one conducting path either AB非or A非B; Then the output F非is pulled down; At the same time, the other pull-down paths connected to the F are both turned off. When F非is pulled down below VDD−|VTP |, M1 turns on and starts charging F to VDD —eventually turning off M2 and pulling down F非to Gnd.Precharge-Evaluate dynamic CMOS:Operation: Precharge (when the clock signal Φ= 0)：The PMOS precharge transistor MP is conducting while the complementary NMOS transistor MN is off. The output load capacitance is precharged to VDD by MP, then VOH=VDD；The input voltages have no influence yet upon the output level since the complementary NMOS transistor MN is off. Evaluate (when the clock signal Φ=1)：The precharge transistor MP turns off while the NMOS evaluate transistor MN turns on. The output node voltage may now remain at the logic-high level or drop to a logic low, depending on the input voltage levels: If the input signals create a conducting path between the output node and the ground, PDN is on, and the output capacitance will discharge toward VOL=0;Otherwise, when PDN is off, the output voltage remains at VOH= VDD.Domino dynamic CMOS logic:When Φ=0, during precharge: The output of the n-type dynamic gate is charged up to VDD, and the output of the inverter is set to 0. When Φ=1, during evaluation: The dynamic gate conditionally discharges, and there are two possibilities: The output node of the dynamic CMOS stage is either discharged to a low level through the NMOS circuitry (1 to 0 transition), or it remains high. Consequently, the inverter output voltage can also make at most one transition during the evaluation phase, from 0 to 1.TSPC dynamic CMOS logic:Configuration:If one constrains a NORA stage to have only n-precharge gates, and not static gates, then a p-channel transistor can be eliminated from the clocked latch; The dynamic circuit technique to be presented in that it uses only one-phase clock signal, so no clock skew problem exists. The NORA design style can be simplified so that a single clock is sufficient. For the doubled n-C2MOS latch, when φ= 1, the latch is in the transparent evaluate mode and corresponds to 2 cascaded inverters (non-inverting); For the doubled n-C2MOS latch, when φ= 0, both inverters are disabled (hold mode) -- only the pull-up network is still active.Pipelined NORA dynamic CMOS system:Configuration: Consists of an np-CMOS logic sequence and a clocked CMOS output buffer; A pipelined system can be constructed by simply cascading alternating φ-section and φ -section, meaning that evaluation occurs during active φ and φ respectively;Operation:φ=0, during hold mode :N block performs the precharge operation and pulls node Out1 up to VDD through the p-type device Mp1, while p block performs the discharge operation and pulls the node Out2 down to zero through the n-type device Mn2; The clocked CMOS latch will not be in operation and the previous output voltage will be stored on the output load capacitor CL. φ=1, during evaluate mode:All cascaded NMOS and PMOS blocks evaluate output levels one after the other, and then the signal Out2 will be inversed to the output node by the clocked CMOS latch in operation;Operation Mode: Evaluate―Hold: All logic stages perform the precharge-discharge operation when the clock is high, and all stages evaluate output levels when the clock is low. Therefore, wewill call this circuit a section, meaning that evaluation occurs during active .Clocked CMOS dynamic circuit:Basic Structure:A pair of PMOS and NMOS transistors controlled by the complementary clock signals are cascaded in the pullup and pulldown paths of the static CMOS gate, respectively, then a CMOS logic gate can be synchronized with a clock. Operation: φ=1, during evaluation mode：The transistors Mp1 and Mp2 are both turned on, then this gate can evaluate normally as a CMOS inverter to generate the logic output In非; φ=0 , during hold mode: Both transistors Mp1 and Mp2 are off, decoupling the output from the input. The CMOS circuit cannot conduct and evaluate, then the output Q retains its previous value stored on the output capacitor CL.Sequential logic:Virtually all useful systems require storage of state information, leading to another class of circuits called sequential logic circuits. In these circuits, the output not only depends upon the current values of the inputs, but also upon preceding output values. In other words, a sequential circuit remembers some of the past history of the system; A sequential circuit consists of a combinational circuit and a memory block in the feedback loop.Combination logic:In all logic circuits described so far, the output is directly related to the input. Typically, there are no feedback loops between the output and the input in these circuits (also classified as non-regenerative circuits), so the outputs are always a logical combination of the inputs. As a class, these circuits are known as combinational logic circuits. Combinational logic circuits, described earlier, have the property that the output of a logic block is only a function of the current input values, assuming that enough time has elapsed for the logic gates to settle. Static storage:preserve state as long as the power is on;are built using positive feedback or regeneration with an intentional connection between the output and the input;useful when updates are infrequent (clock gating)Dynamic storage:store state on parasitic capacitors;only hold state for short periods of time (milliseconds);require periodic refresh to annihilate charge leakage;usually simpler, so higher speed and lower power;useful in datapath circuits that require high performance levels and are periodically clockedLatch: level sensitive circuit that passes inputs to Q when the clock is high (or low);input sampledon the falling edge of the clock is held stable when clock is low (or high)Register or Flip-flops (edge-triggered): edge sensitive circuits that only sample the inputs on a clock transitionpositive edge-triggered: 0- 1negative edge-triggered: 1 -0built using latches (e.g., master-slave flip-flops)。
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自我检测题
1．在存储器结构中，什么是“字”什么是“字长”，如何表示存储器的容量
解：采用同一个地址存放的一组二进制数，称为字。
字的位数称为字长。
习惯上用总的位数来表示存储器的容量，一个具有n字、每字m位的存储器，其容量一般可表示为n ×m位。
2．试述RAM和ROM的区别。
解：RAM称为随机存储器，在工作中既允许随时从指定单元内读出信息，也可以随时将信息写入指定单元，最大的优点是读写方便。
但是掉电后数据丢失。
ROM在正常工作状态下只能从中读取数据，不能快速、随时地修改或重新写入数据，内部信息通常在制造过程或使用前写入，
3．试述SRAM和DRAM的区别。
解：SRAM通常采用锁存器构成存储单元，利用锁存器的双稳态结构，数据一旦被写入就能够稳定地保持下去。
动态存储器则是以电容为存储单元，利用对电容器的充放电来存储信息，例如电容器含有电荷表示状态1，无电荷表示状态0。
根据DRAM的机理，电容内部的电荷需要维持在一定的水平才能保证内部信息的正确性。
因此，DRAM在使用时需要定时地进行信息刷新，不允许由于电容漏电导致数据信息逐渐减弱或消失。
4．与SRAM相比，闪烁存储器有何主要优点
解：容量大，掉电后数据不会丢失。
5．用ROM实现两个4位二进制数相乘，试问：该ROM需要有多少根地址线多少根数据线其存储容量为多少
解：8根地址线，8根数据线。
其容量为256×8。
6．简答以下问题：
（1）CPLD和FPGA有什么不同
FPGA可以达到比 CPLD更高的集成度，同时也具有更复杂的布线结构和逻辑实现。
FPGA 更适合于触发器丰富的结构，而 CPLD更适合于触发器有限而积项丰富的结构。
在编程上 FPGA比 CPLD具有更大的灵活性；CPLD功耗要比 FPGA大；且集成度越高越明显；CPLD比 FPGA有较高的速度和较大的时间可预测性，产品可以给出引脚到引脚的最大延迟时间。
CPLD的编程工艺采用 E2 CPLD的编程工艺，无需外部存储器芯片，使用简单，保密性好。
而基于 SRAM编程的FPGA,其编程信息需存放在外部存储器上，需外部存储器芯片 ,且使用方法复杂，保密性差。
（2）写出三家CPLD/FPGA生产商名字。
Altera，lattice，xilinx，actel
7．真值表如表所示，如从存储器的角度去理解，AB应看为地址，F0F1F2F3应看为数据。
表
8．一个ROM 共有10根地址线，8根位线（数据输出线），则其存储容量为。
A．10×8 B．102×8 C．10×82 D．210×8
9．为了构成4096×8的RAM，需要片1024×2的RAM。
A．8片 B．16片 C．2片 D．4片
10．哪种器件中存储的信息在掉电以后即丢失
A．SRAM B．UVEPROM C．E2PROM D．PAL
11．关于半导体存储器的描述，下列哪种说法是错误的。
A．RAM读写方便，但一旦掉电，所存储的内容就会全部丢失
B．ROM掉电以后数据不会丢失
C．RAM可分为静态RAM和动态RAM
D．动态RAM不必定时刷新
12．有一存储系统，容量为256K×32。
设存储器的起始地址全为0，则最高地址的十六进制地址码为 3FFFFH 。
13．PAL是一种的可编程逻辑器件。
A．与阵列可编程、或阵列固定的 B．与阵列固定、或阵列可编程的
C．与、或阵列固定的 D．与、或阵列都可编程的
习题
1．现有如图所示的4×4位RAM若干片，现要把它们扩展成8×8位RAM。
（1）试问需要几片4×4位RAM
（2）画出扩展后电路图（可用少量门电路）。
图
解：（1）用4×4位RAM扩展成8×8位RAM时，需进行字数和位数扩展，故需要4片4×4的RAM
（2）扩展后电路如图：
D D 6D D 4A 0A 1D D 2D D 0
A 2
2．在微机中，CPU 要对存储器进行读写操作，首先要由地址总线给出地址信息，然后发出相应读或写的控制信号，最后才能在数据总线上进行信息交流。
现有256×4位的RAM 二片，组成一个页面，现需4个页面的存储容量，画出用256×4位组成1K ×8位的RAM 框图，并指出各个页面的地址分配。
解：电路连接图如图所示。
从左到右四个页面的地址为： 000H~0FFH ，100H~1FFH ，200H~2FFH ，300H~3FFH 。
D 7D 6D 5D 4D 3D 2D 1
D 0
A 8A 9
A 0~A 3．试用4×2位容量的ROM 实现半加器的逻辑功能，并直接在图中画出用ROM 点阵图实现的半加法器电路。
A
B
S
i
C
i
图
A
B
i
S
i
C
A
B
i
S
i
C 解：由于半加器的输出B
A
B
A
S
i
+
=
AB
C i=
所以ROM点阵图如图所示。
4．用EPROM实现二进制码与格雷码的相互转换电路，待转换的代码由I3I2I1I0输入，转换后的代码由O3O2O1O0输出。
X为转换方向控制位，当X=0时，实现二进制码到格雷码的转换；当X=1时，实现格雷码到二进制码的转换。
试求：
（1）列出EPROM的地址与内容对应关系真值表；
（2）确定输入变量和输出变量与ROM地址线和数据线对应关系。
解：真值表为：
输入变量和输出变量与ROM 地址线和数据线对应关系如图所示：
32×4 RAM D 3D 2D 1D 0
A 0
A 1A 3A 2X A 4I 3I 2I 1I 0
O 3O 2O 1O 0
5．试分析如图所示PLA 构成电路。
写出F 1、F 2的逻辑表达式。
1
2
图
解：C
A
F+
+
C
=
AB
A
B
C
1
A
=
F+
BC
C
B
A
2
6．试分析如图所示电路。
（1）列出时序PLA的状态表和状态图
（2）简述该时序PLA的逻辑功能。
图
解：（1）根据电路图写出各触发器驱动方程 n n Q Q J 120+=，10=K
n Q J 01=，n n Q Q K 021+= n n Q Q J 012=，n Q K 12=
（2）写出各触发器状态方程 n n n n n n n Q Q Q Q Q K Q J Q 010200000+=+= n n n n n n n n Q Q Q Q Q Q K Q J Q 0120111111+=+=
n n n n n n n n Q Q Q Q Q Q K Q J Q 1201222222+=+=
（3）列出状态表
（4）状态转换图
（5）功能：同步七进制加法计数器。
7．试分析如图所示由PLA 实现的时序电路，列出状态转换表，简述该时序电路的逻辑功能。
Q 0
Q 1
Q 2
X
图
解 （1）根据电路图写出各触发器状态方程：
n n n n n Q Q X Q Q Q 020112+=+
n n n n n n Q Q Q Q Q Q 0120111+=+
n n n n Q X Q Q Q 00210+=+
（2）根据特性方程列出状态真值表，如表所示。
（3）状态转换图
由状态真值表可得电路在X = 0与X = 1时的状态转换图，如图所示。
12Q Q Q X =0
X =1
（4）逻辑功能
当X =0时，该时序电路为6进制加法计数器；当X =1时，该时序电路为5进制加法计数器。
8．观察如图的可编程I/O 模块，要求把此I/O 模块配置成输入管脚，请标出数据输入通道，给出具体的5个配置比特，并给出T 的值。
I/O 引脚
输出信号
输入信号
时钟
使能使能全局请零
时钟三态控制输出反相
三态反相
锁存输出弱上拉
转换
速率
图
解：要将I/O 引脚作为输入引脚，
要将输出三态缓冲器输出置成高阻态，弱上拉禁止。
因此可将三态控制T 置1，三态反相置0，弱上拉置0，其余编程位无关。