TRACE32-使用
TRACE32 iAMP 双核调试应用说明书
Application Note for iAMP Debugging Release 09.2023TRACE32 Online HelpTRACE32 DirectoryTRACE32 IndexTRACE32 Documents ...................................................................................................................... Multicore Debugging ..................................................................................................................... Application Note for iAMP Debugging . (1)SMP, iAMP or AMP? (3)iAMP Setup (7)Example iAMP Setup10Version 09-Oct-2023 11-Nov-2021New manual.SMP, iAMP or AMP?TRACE32 offers various configuration possibilities for debugging multi-core target systems. This chapter explains the basic differences between:•SMP (Symmetrical MultiProcessig)•iAMP (integrated Asymmetrical MultiProcessing)•AMP (Asymmetrical MultiProcessig)This application note focuses on iAMP. It gives you a basic overview of the iAMP concept and helps you to choose the right configuration for your setup. For further details about iAMP and the commands used here, you can also see the “General Reference Guide” (general_ref_<x>.pdf) or contact**********************.If you want to create a new TRACE32 setup for any multicore system, one of the very first decisions you have to make is “AMP or SMP or iAMP?”. In some cases, only one of the possibilities is supported by TRACE32, for example: if you have several cores of different architectures (like one Arm core, one Xtensa core and one RISC-V core), then AMP is the only possible option. But in many cases, you have a choice.Let’s first take a look at the key properties of the three concepts:•All cores have the same instruction set.•All cores use the same instance of an OS (when not bare-metal and unless you are using a hypervisor (“Hypervisor Debugging User Guide” (hypervisor_user.pdf)).•All cores use the same memory model and same address translations (unless you are using a hypervisor).•All cores share the same physical and logical address space.•All cores share the same debug symbols (typically the same elf file).•All cores are debugged from a single TRACE32 PowerView instance. Y ou can have up to 1024cores.•TRACE32 starts and stops all cores simultaneously (even though you can temporarily single out one core for independent start/stop).iAMP (integrated asymmetrical multiprocessing):•All cores have the same instruction set.•There are typically multiple OS instances (if not bare metal).•There is just one global physical address space but each OS maintains its own set of virtual address spaces.•All cores are debugged from a single TRACE32 PowerView GUI. The number of cores is limited just by the core architecture used and can be very high.•TRACE32 allows to group cores logically into machines; this grouping depends on the logical structure of the system under debug - each machine consists of one or more cores. Up to30machines are possible.•Each machine has its own OS instance (if not bare metal).•Each machine has its own memory model, address translations and debug symbols.•TRACE32 starts and stops all cores simultaneously (even though you can temporarily single out one core for independent start/stop).•AMP can bundle single cores, as well as SMP and iAMP subsystems.•Mixing of different core architectures with different instruction sets is possible.•Each core/subsystem has its own TRACE32 PowerView GUI.•Each core/subsystem has its own (different) memory models, address translations, elf files and debug symbols.•Each core/subsystem can have its own physical address space.•Each core/subsystem has its own logical address spaces.•Each core/subsystem starts and stops independently but can also be synchronized.•AMP is limited to 16 TRACE32 PowerView GUIs.An example of an AMP system that bundles single cores, an SMP and an iAMP subsystem can be found on page10.The most important questions for the decision are:•Do all my cores use the same instruction set?If not, it is definitely AMP.•Do all my cores of the same instruction set run a single instance of OS?If yes, these cores form an SMP (sub)system.•Are there SMP subsystems and single cores of the same instruction set? Does it make sense to configure them as an iAMP system and debug them from a single TRACE32PowerView instance?Y es, if they are all using a global physical address space.Y es, if they logically belong together; that means they work together or in parallel on the same tasks.Y es, if you want or need to reduce the number of TRACE32 PowerView instances.The following table provides a systematic overview:SMP AMP iAMP Homogeneous cores (cores of the same instruction set)✓✓✓Heterogeneous cores✓Single TRACE32 instance/GUI✓✓Multiple TRACE32 instances/GUIs 16Hypervisor with statically assigned guests (core identity)✓✓✓Hypervisor with dynamic core assignment (core sharing)✓SMP OS (a single OS managing multiple cores)✓Multiple OSes without hypervisor✓Synchronous run✓✓✓Asynchronous run✓iAMP is available for selected core architectures like Arm, Hexagon and T riCore. If you need iAMP and your platform does not support it yet, please contact your local Lauterbach representative or**********************.Some of the decision criteria are easy to evaluate (like more than 16 CPUs) but some of them are quite fuzzy - talking to Lauterbach representative or Lauterbach support might help you with the decision.iAMP SetupThe basis for an iAMP system is that cores are grouped into machines.The SYStem.Option.MACHINESPACES ON command creates the basis for this.All cores that use the same instance of an OS (when not bare-metal) can be grouped and assigned to a machine by the TASK.Create.MACHINE command.Example :This will create two machines, each of them with two cores. Their setup can be then displayed using the commandTASK.List.MACHINES :The columns name and cores in the screenshot are self-explaining, ‘mid’ displays the machine ID, other columns are not relevant for our example.It may be necessary to use the CORE.ASSIGN command beforehand to assign the physical cores to the logical cores of the iAMP system.Use the command CORE.select <logical_core> to switch to the core of interest and the TRACE32PowerView GUI will display the system information from the perspective of the selected core. T o understand how this works, think that “the machine is never selected directly but always follows selected core”.By default, all cores are started and stopped simultaneously , but you can single out a single core for independent start/stop by using the CORE.SINGLE <logical_core> command.The CORE.select command without an argument can be used to reverse this selection after the core is stopped.It is imperative to ensure that the symbols loaded by any of the Data.LOAD.* commands will be added to the right machine space. When loading executables and symbol information, the safest way is to explicitly select the core to which the executable belongs – it then explicitly defines both the core and machine. One of the reasons is that registers like PC might be pre-initialized during Data.LOAD so by selecting the correct core it becomes clear where the register(s) are to be set:TASK.Create.MACHINE , 0. "main0" /CORE 0. 1.TASK.Create.MACHINE , 1. "main1" /CORE 2. 3.CORE.select 0.Data.LOAD.Elf application_subsystem0.elf CORE.select 2.Data.LOAD.Elf application_subsystem1.elf /NoClearOn the other hand, when you load only symbol information and no register content, it is sufficient to specify only the machine; knowledge of the specific core is not required. T o specify only the machine, use theloading offset parameter to Data.LOAD.* where this offset contains the machine number. In most cases you use zero as offset (unless you need to shift the data to another base address).Loading symbols using the machine ID makes them machine aware as can be seen in the image below.The machine name can be explicitly specified in a symbol name using triple-backslash (“\\\”) syntax.Example :This command will show the source of the symbol start from the module Global on the machine named main1.The general format for symbol names becomes:[\\\<machine_name>]\\[<program_name>]\[<module_name>]\<symbol_name>Both <program_name> and <module_name> may be omitted if there is no ambiguity with another symbol but the appropriate backslashes must remain to indicate where they were, for example:\\\<machine_name>\\\<symbol_name>So, our example of \\\main1\\Global\start now becomes \\\main1\\\\startWhen you activate the iAMP mode, the behavior of many commands changes. The commands now also consider the correct machine scope, for example:Data.LOAD.Elf application_subsystem0.elf 0x0:::0 /NoCODE /NoRegData.LOAD.Elf application_subsystem1.elf 0x1:::0 /NoClear /NoCODE /NoRegNOTE:This concept is extended to allow you to access a logical address on any machine and works like this:[<access_class>:][<machine_id>:::]<address_offset> Example:P:1:::0x1234000 means program address P:0x1234000 on machine 1.R:0:::0x81021864 means AArch32 Arm code at address R:0x81021864 on machine 0.List.Asm \\\main1\\\Global\startNormally, MMU.DUMP.TLB shows the only TLB in the system (where available). With iAMP, the contents displayed by MMU.DUMP.TLB will update after every change of machine and always show the TLB of the currently selected machine.The program counter is now shown everywhere with the machine number included - like in this CORE.List window:The machine number is also included in many other outputs and windows, almost everywhere where you see an address. The screenshot below shows the sYmbol.List.SECtion window. It can be seen that sections from all machines and all addresses include the machine number.Example iAMP SetupAssume the following system, based on a TDA4VM chip from T exas Instruments:•Four Cortex-R5 cores, grouped in two core pairs, called “main0” and “main1”. These four cores form our example iAMP system.Each core pair has its own symbols and ELF file (app_ddr.elf and app_sram.elf ).Both core pairs use logical memory but have their own translations.•In addition to that, there is also a Cortex-M3 core (“master”), Cortex-R5 (“mcu”) based SMP subsystem and a TI C71x (“dsp”) on the chip, which all need to be debugged as well.Four TRACE32 PowerView GUIs are needed to debug this AMP system:1.GUI to control the Cortex-R5 based iAMP subsystem 2.GUI to control a single Cortex-M33.GUI to control the Cortex-R5 based SMP subsystem4.GUI to control a single C71x DSPTRACE32 PowerDebugDebug Port®iAMP main0 + main1Cortex-M3masterSMP 2x Cortex-R5mcuC71x dspApplication Note for iAMP Debugging | 11©1989-2023 L auterbach So, let's focus on the iAMP subsystem - we want to preload all elf files, execute all startups immediately after loading, and then start the execution of all cores/machines from the symbol main simultaneously. For this setup, the following script can be used:The other subsystems of SoC are initialized as usual with their own scripts.The structure of the whole system can be then displayed via the command TargetSystem ALL .sYmbol.RESetSYStem.Option.MACHINESPACES ONTASK.CREATE.MACHINE , 0. "main0" /CORE 0. 1.TASK.CREATE.MACHINE , 1. "main1" /CORE 2. 3.CORE.select 0.Data.LOAD.Elf app_ddr.elfCORE.select 2.Data.LOAD.Elf app_ram.elf /NoClearCORE.SINGLE 0. ; enter single core execution mode Go mainWAIT !STATE.RUN()CORE.SINGLE 2. ; enter single core execution mode Go mainWAIT !STATE.RUN()CORE.select 0. ; leaving single core execution mode PRINT "Now we are ready to debug from main"。
TRACE32使用精品PPT课件
3，安装TRACE32工具软件
• 2.1）TRACE32在FTP服务器目的位置： \\192.167.100.185\simcom\TD\Tools\trace32 • 2.2）安装注意事项： • step4，Product type选择—ICD In-circuit-
• 4.3） 为使TRACE32调试跟踪某应用程序，需要在 js_it_debug.cmm脚本中，添加该应用程序的路径。 方法是打开js_it_debug.cmm脚本，添加应用程序路 径，如添加phonebook模块，只要在脚本中添加 Symbol.Spath z:\app2\applications\phonebook
演讲人：XXXXXX 时 间：XX年XX月XX日
Debugger; • Step5，IDC Interface Type—USB
interface ;
• step6，选择license key not necessary; • step8，CPU selection—IDC ARM7 ARM9
ARM10 ARM 11 • 其它安装步骤默认处理
4，编译，烧录代码
连接方法：
TRACE32，手机，开发板连接图：
• 1.2）下图适用于TH100接开发板跳线方法。 • J14和J13两个跳线帽放到左边 ，J7在右边
•Байду номын сангаас1.3）TH100连接Trace32注意事项：
• 图中的开发板的版本是 “TG100_TESTBOARD_V2.10_PCB(07 0619)”，请尽量使用此版本的Test Board。
trace32使用手册
打开后的程序列表窗口可以有下面几种形式。 Pic24. 找不到源文件的程序列表窗口
对于上图所示的情形，需要用 Y.SPATH 命令指定源程序路径。如下图所示。 Pic25. 指定源程序路径（其一） Pic26. 带源程序的混合显示程序列表窗口（其二）
通过点击程序列表窗口上的“Mode”按钮可以切换混合和源码显示方式。 Pic27. 带源程序的源码程序列表窗口（其三）
这些设置主要包括： 1、 选择要调试的处理器型号。 2、 是否有多个器件串联在同一个 JTAG 链路里，连接顺序如何，每个器件的 JTAG IR
寄存器的宽度是多少。 （情况一） 3、 JTAG 时钟使用 TCK 还是 RTCK。TCK 由 TRACE-ICP 提供，一般情况下选用
10MHz。RTCK 是 TRACE-ICP 的 TCK 进入目标 JTAG 链路之后，从目标 JTAG 链路返回的时钟，它与目标处理器的时钟同步。一般情况下，具有睡眠模式的处理 器多选用 RTCK 作 JTAG 时钟， 如 ARM926EJ-S。 （情况二） 4、 通过 JTAG 与目标连接时，是否要先复位目标板。JTAG 口上的 SRST 信号产生复 位信号。 （情况三） 5、 通过 JTAG 与目标连接时，是否要停止目标处理器运行。 （情况四） 从主菜单“CPU”中选择“System Settings…” ，打开如下图所示对话框。从“CPU” 下拉菜单里选择要调试的处理器。 Pic2. System Settings 对话框
Pic29 中红框内的单选钮 IMASKASM 和 IMASKHLL 选择之后，单步时就会屏蔽中断。 用户也可以通过命令 sys.o imaskasm on 和 sys.o imaskhll on 来设置这两个选项。
十、 设置软件断点 设置软件断点可以在命令行输入命令 break.set <address> /soft 来实现，在命令中的 <address>代表程序地址，可以是程序中的函数名等符号。如下图所示。 Pic30. 用命令设置软件断点
TRACE32调试技巧
TRACE32调试技巧TRACE32是一款功能强大的软件调试工具，广泛应用于嵌入式系统的调试和测试。
它提供了丰富的调试功能和强大的分析能力，可以帮助开发人员快速定位故障和优化系统性能。
下面将介绍一些TRACE32的调试技巧，帮助开发人员更好地使用这个工具。
1.使用实时跟踪功能：TRACE32支持实时跟踪功能，可以实时收集目标系统的执行信息。
通过实时跟踪，开发人员可以查看程序的执行路径、函数调用关系、指令执行时间等信息，帮助快速定位程序错误和优化系统性能。
2.设置断点和触发条件：TRACE32支持设置断点和触发条件，可以在软件运行过程中暂停程序执行。
开发人员可以根据需要设置断点，然后在断点处查看当前程序状态和变量值，帮助分析程序执行流程和调试错误。
3.使用慢速模式：TRACE32支持慢速模式，在这种模式下，可以减慢目标系统的执行速度，帮助开发人员更好地观察和分析程序的执行情况。
慢速模式可以有效地帮助调试时间较短的代码片段，并且可以避免程序执行过快导致的观察困难。
4.使用非侵入式调试功能：TRACE32支持非侵入式调试功能，可以在不停止目标系统的情况下进行调试。
这对于那些不能中断执行的实时系统非常有用，可以帮助开发人员在不中断系统运行的情况下进行调试和分析。
5.使用时间相关分析功能：TRACE32还提供了强大的时间相关分析功能，可以帮助开发人员分析程序的响应时间、任务调度时间等性能指标。
通过时间相关分析，开发人员可以发现程序中的时间瓶颈，并做出相应的优化措施。
6.使用多核调试功能：TRACE32支持多核调试功能，可以帮助开发人员调试多核处理器上的并行程序。
通过多核调试，开发人员可以查看每个核心上的程序执行情况，帮助分析并行程序的运行状态和调试错误。
7.使用快速调试功能：TRACE32拥有快速调试功能，可以加快调试过程。
通过快速调试，开发人员可以在源代码级别进行调试，而无需重新编译和烧写目标系统。
8.使用数据跟踪功能：TRACE32支持数据跟踪功能，可以帮助开发人员收集指定变量的值和修改历史。
Lauterbach黑芯调试器TRACE32在线帮助说明书
Blackfin Debugger Release 09.2023Blackfin DebuggerTRACE32 Online HelpTRACE32 DirectoryTRACE32 IndexTRACE32 Documents ......................................................................................................................ICD In-Circuit Debugger ................................................................................................................Processor Architecture Manuals ..............................................................................................Blackfin ....................................................................................................................................Blackfin Debugger (1)Introduction (4)Brief Overview of Documents for New Users4 Demo and Start-up Scripts5 Location of Debug Connector5Warning (5)Quick Start JTAG (6)Troubleshooting (8)SYStem.Up Errors8FAQ (8)Configuration (9)System Overview9Blackfin specific SYStem Commands (10)SYStem.CONFIG Configure debugger according to target topology10 Daisy-Chain Example13 TapStates14 SYStem.CONFIG.CORE Assign core to TRACE32 instance15 SYStem.CPU CPU type selection16 SYStem.JtagClock JTAG clock selection17 SYStem.LOCK Lock and tristate the debug port17 SYStem.MemAccess Real-time memory access (non-intrusive)18 SYStem.Mode System mode selection19 SYStem.Option.IMASKASM Interrupt disable19 SYStem.Option.IMASKHLL Interrupt disable20Breakpoints (21)Software Breakpoints21 On-chip Breakpoints21 Breakpoint in ROM21Example for Breakpoints22 Memory Classes (23)CPU specific TrOnchip Commands (24)JTAG Connector (25)Blackfin DebuggerVersion 10-Oct-2023 IntroductionThis document describes the processor specific settings and features for the Blackfin Embedded Media Processor. TRACE32-ICD supports all Blackfin devices which are equipped with the JT AG debug interface.Please keep in mind that only the Processor Architecture Manual (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.If some of the described functions, options, signals or connections in this Processor Architecture Manual are only valid for a single CPU the name is added in brackets.Brief Overview of Documents for New UsersArchitecture-independent information:•“Training Basic Debugging” (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger.•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger. T32Start is only available for Windows.•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.Architecture-specific information:•“Processor Architecture Manuals”: These manuals describe commands that are specific for the processor architecture supported by your Debug Cable. T o access the manual for your processorarchitecture, proceed as follows:-Choose Help menu > Processor Architecture Manual.•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating system-aware debugging. The appropriate OS Awareness manual informs you how to enable theOS-aware debugging.Demo and Start-up ScriptsLauterbach provides ready-to-run start-up scripts for known Blackfin based hardware.To search for PRACTICE scripts, do one of the following in TRACE32 PowerView:•Type at the command line: WELCOME.SCRIPTS•or choose File menu > Search for Script.Y ou can now search the demo folder and its subdirectories for PRACTICE start-up scripts(*.cmm) and other demo software.Y ou can also manually navigate in the ~~/demo/blackfin/ subfolder of the system directory ofTRACE32.Location of Debug ConnectorLocate the debug connector on your target board as close as possible to the processor to minimize the capacitive influence of the trace length and cross coupling of noise onto the JT AG signals. WarningSignal LevelThe debugger output voltage follows the target voltage level. It supports a voltage range of 0.4…5.2V. ESD ProtectionNOTE:T o prevent debugger and target from damage it is recommended to connect ordisconnect the debug cable only while the target power is OFF.Recommendation for the software start:•Disconnect the debug cable from the target while the target power is off.•Connect the host system, the TRACE32 hardware and the debug cable.•Start the TRACE32 software.•Connect the debug cable to the target.•Switch the target power ON.Power down:•Switch off the target power.•Disconnect the debug cable from the target.Quick Start JTAGStarting up the debugger is done as follows:1.Select the device prompt B: for the ICD Debugger, if the device prompt is not active after the TRACE32 software was started.2.Select the CPU type to load the CPU specific settings.3.Enter debug mode:This command resets the CPU and enters debug mode. After the execution of this command access to the registers and to memory is possible. Before performing the first access to external SDRAM or FLASH the External Bus Interface Unit (EBIU) must be configured.4.The following command sequence is for the BF537 processor and configures the SDRAM controller with default values that were derived for maximum flexibility. They work for a system clock frequency between 54MHz and 133MHz.In the example a ST M29W320DB flash device is used in 16-bit mode. All four memory banks and CLKOUT are enabled.B:SYStem.CPU BF537SYStem.Up; configure SDRAM controllerData.Set 0xFFC00A1sLONG 0x0091998D Data.Set 0xFFC00A14 %WORD 0x0025Data.Set 0xFFC00A1C %WORD 0x03A0; EBIU_SDGCTL ; EBIU_SDBCTL ; EBIU_SDRRC; enable all flash memory banks and clock outData.Set 0xFFC00A00 %WORD 0x00FF; EBIU_AMGCTL; ST M29W320DB flash device in 16-bit modeFLASH.Create 1. 0x20000000--0x20003FFF 0x4000 AM29LV100 Word FLASH.Create 1. 0x20004000--0x20007FFF 0x2000 AM29LV100 Word FLASH.Create 1. 0x20008000--0x2000FFFF 0x8000 AM29LV100 Word FLASH.Create 1. 0x20010000--0x203FFFFF 0x10000 AM29LV100 Word5.Load the program.Data.LOAD.Elf demo.dxe; The file demo.dxe is in ELF format The option of the Data.LOAD command depends on the file format generated by the compiler. A detailed description of the Data.LOAD command is given in the “General Commands Reference”. The start-up sequence can be automated using the programming language PRACTICE. A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm, ASCII format) and executed with the command DO<file>.B::; Select the ICD device promptWinClear; Delete all windowsSYStem.CPU BF537; select the processorSYStem.Up; Reset the target and enter debug modeData.Load.Elf sieve.dxe; Load the applicationRegister.Set PC main; Set the PC to function mainList.Mix; Open disassembly window *) Register.view; Open register window *) PER.view; Open window with peripheral register *) Break.Set sieve; Set breakpoint to function sieveBreak.Set 0x1000 /p; Set on-chip breakpoint to address 1000; Refer to the restrictions in; On-chip Breakpoints.*) These commands open windows on the screen. The window position can be specified with the WinPOS command.TroubleshootingSYStem.Up ErrorsThe SYStem.Up command is the first command of a debug session where communication with the target is required. If you receive error messages while executing this command this may have the following reasons.All The target has no power.All There are additional loads or capacities on the JTAG lines.All The JTAG clock is too fast.FAQPlease refer to https:///kb.Configuration System OverviewBlackfin specific SYStem CommandsSYStem.CONFIG Configure debugger according to target topologyThe four parameters IRPRE, IRPOST , DRPRE, DRPOST are required to inform the debugger about the T AP controller position in the JT AG chain, if there is more than one core in the JT AG chain (e.g. ARM + DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up . See Daisy-chain Example .For some CPU selections (SYStem.CPU ) the above setting might be automatically included, since the required system configuration of these CPUs is known.T riState has to be used if several debuggers (“via separate cables”) are connected to a common JT AG port at the same time in order to ensure that always only one debugger drives the signal lines. T APState and TCKLevel define the T AP state and TCK level which is selected when the debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down resistor, other trigger inputs need to be kept in inactive state.Format:SYStem.CONFIG <parameter> <number_or_address>SYStem.MultiCore <parameter> <number_or_address> (deprecated)<parameter>:CORE <core><parameter>:(JTAG):DRPRE <bits>DRPOST <bits>IRPRE <bits>IRPOST <bits>DAPDRPOST <bits>DAPDRPRE <bits>DAPIRPOST <bits>DAPIRPRE <bits>TAPState <state>TCKLevel <level>TriState [ON | OFF ]Slave [ON | OFF ]DEBUGPORTTYPE [JTAG | SWD ]SWDPIDLEHIGH [ON | OFF ]SWDPTargetSel <value>CORE For multicore debugging one TRACE32 PowerView GUI has to be startedper core. To bundle several cores in one processor as required by thesystem this command has to be used to define core and processorcoordinates within the system topology.Further information can be found in SYStem.CONFIG.CORE.… DRPOST <bits>Defines the TAP position in a JT AG scan chain. Number of TAPs in theJTAG chain between the TDI signal and the TAP you are describing. InBYPASS mode, each TAP contributes one data register bit. See possibleTAP types and example below.Default: 0.… DRPRE <bits>Defines the TAP position in a JT AG scan chain. Number of TAPs in theJTAG chain between the TAP you are describing and the TDO signal. InBYPASS mode, each TAP contributes one data register bit. See possibleTAP types and example below.Default: 0.… IRPOST <bits>Defines the TAP position in a JT AG scan chain. Number of InstructionRegister (IR) bits of all TAPs in the JT AG chain between TDI signal andthe TAP you are describing. See possible T AP types and example below.Default: 0.… IRPRE <bits>Defines the TAP position in a JT AG scan chain. Number of InstructionRegister (IR) bits of all TAPs in the JTAG chain between the T AP you aredescribing and the TDO signal. See possible TAP types and examplebelow.Default: 0.TAPState(default: 7 = Select-DR-Scan) This is the state of the TAP controller whenthe debugger switches to tristate mode. All states of the JTAG T APcontroller are selectable.TCKLevel (default: 0) Level of TCK signal when all debuggers are tristated. TriState(default: OFF) If several debuggers share the same debug port, thisoption is required. The debugger switches to tristate mode after eachdebug port access. Then other debuggers can access the port. JT AG:This option must be used, if the JTAG line of multiple debug boxes areconnected by a JTAG joiner adapter to access a single JTAG chain. Slave(default: OFF) If more than one debugger share the same debug port, allexcept one must have this option active.JTAG: Only one debugger - the “master” - is allowed to control the signalsnTRST and nSRST (nRESET).DEBUGPORTTYPE [JTAG | SWD]It specifies the used debug port type “JT AG”, “SWD”. It assumes the selected type is supported by the target.Default: JT AG.SWDPIdleHigh [ON | OFF]Keep SWDIO line high when idle. Only for Serialwire Debug mode. Usually the debugger will pull the SWDIO data line low, when no operation is in progress, so while the clock on the SWCLK line is stopped (kept low).Y ou can configure the debugger to pull the SWDIO data linehigh, when no operation is in progress by usingSYStem.CONFIG SWDPIdleHigh ONDefault: OFF.SWDPTargetSel<value>Device address in case of a multidrop serial wire debug port.Default: none set (any address accepted).Daisy-Chain ExampleBelow, configuration for core C.Instruction register length of •Core A: 3 bit •Core B: 5 bit •Core D: 6 bitSYStem.CONFIG.IRPRE 6.; IR Core D SYStem.CONFIG.IRPOST 8.; IR Core A + B SYStem.CONFIG.DRPRE 1.; DR Core D SYStem.CONFIG.DRPOST 2.; DR Core A + BSYStem.CONFIG.CORE 0. 1.; Target Core C is Core 0 in Chip 1Core A Core B Core CCore D TDOTDI Chip 0Chip 1TapStates0Exit2-DR1Exit1-DR2Shift-DR3Pause-DR4Select-IR-Scan5Update-DR6Capture-DR7Select-DR-Scan8Exit2-IR9Exit1-IR10Shift-IR11Pause-IR12Run-Test/Idle13Update-IR14Capture-IR15Test-Logic-ResetSYStem.CONFIG.CORE Assign core to TRACE32 instance Format:SYStem.CONFIG.CORE<core_index><chip_index>SYStem.MultiCore.CORE<core_index><chip_index> (deprecated) <chip_index>:1 (i)<core_index>:1…kDefault core_index: depends on the CPU, usually 1. for generic chipsDefault chip_index: derived from CORE= parameter of the configuration file (config.t32). The COREparameter is defined according to the start order of the GUI in T32Start with ascending values.T o provide proper interaction between different parts of the debugger, the systems topology must bemapped to the debugger’s topology model. The debugger model abstracts chips and sub cores of these chips. Every GUI must be connect to one unused core entry in the debugger topology model. Once the SYStem.CPU is selected, a generic chip or non-generic chip is created at the default chip_index.Non-generic ChipsNon-generic chips have a fixed number of sub cores, each with a fixed CPU type.Initially, all GUIs are configured with different chip_index values. Therefore, you have to assign thecore_index and the chip_index for every core. Usually, the debugger does not need further information to access cores in non-generic chips, once the setup is correct.Generic ChipsGeneric chips can accommodate an arbitrary amount of sub-cores. The debugger still needs information how to connect to the individual cores e.g. by setting the JT AG chain coordinates.Start-up ProcessThe debug system must not have an invalid state where a GUI is connected to a wrong core type of a non-generic chip, two GUIs are connected to the same coordinate or a GUI is not connected to a core. The initial state of the system is valid since every new GUI uses a new chip_index according to its CORE= parameter of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must be merged by calling SYStem.CONFIG.CORE.SYStem.CPU CPU type selection Format:SYStem.CPU <cpu><cpu>:BF531 | BF532 | BF533 | BF534…Default selection: BF534.Selects the CPU type.SYStem.JtagClock JT AG clock selection Format:SYStem.JtagClock [<frequency>]SYStem.BdmClock<frequency>(deprecated)Default frequency: 1MHz.Selects the JT AG port frequency (TCK). Any frequency up to 50MHz can be entered, it will be generated by the debuggers internal PLL.For CPUs which come up with very low clock speeds it might be necessary to slow down the JT AGfrequency. After initialization of the CPUs PLL the JT AG clock can be increased.SYStem.LOCK Lock and tristate the debug port Format:SYStem.LOCK [ON | OFF]Default: OFF.If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the SYStem.LOCK command is to give debug access to another tool.SYStem.MemAccess Real-time memory access (non-intrusive) Format:SYStem.MemAccess Denied | StopAndGo | BTCBTC“BTC” allows a non-intrusive memory access while the core is running, if aBackground T elemetry Channel (BTC) is defined in your application. Anyinformation on how to create such a channel can be found in AnalogDevices’ VisualDSP++ user’s manual. The JT AG clock speed should be asfast as possible to get good performanceDenied Real-time memory access during program execution to target is disabled.StopAndGo Temporarily halts the core(s) to perform the memory access. Each stoptakes some time depending on the speed of the JT AG port, the number ofthe assigned cores, and the operations that should be performed.SYStem.Mode System mode selectionFormat:SYStem.Mode <mode>SYStem.Attach (alias for SYStem.Mode Attach)SYStem.Down (alias for SYStem.Mode Down)SYStem.Up (alias for SYStem.Mode Up)<mode>:DownGoAttachUpDown Disables the debugger.Go Resets the target with debug mode enabled and prepares the CPU fordebug mode entry. After this command the CPU is in the system.upmode and running. Now, the processor can be stopped with the breakcommand or if a break condition occurs.Attach User program remains running (no reset) and the debug interface isinitialized.Up Resets the target and sets the CPU to debug mode. After execution ofthis command the CPU is stopped and prepared for debugging.StandBy Not supported.NoDebug Not supported.SYStem.Option.IMASKASM Interrupt disable Format:SYStem.Option.IMASKASM [ON | OFF]Mask interrupts during assembler single steps. Useful to prevent interrupt disturbance during assembler single stepping.SYStem.Option.IMASKHLL Interrupt disable Format:SYStem.Option.IMASKHLL [ON | OFF]Mask interrupts during HLL single steps. Useful to prevent interrupt disturbance during HLL single stepping.BreakpointsThere are two types of breakpoints available: software breakpoints and on-chip breakpoints. Software BreakpointsSoftware breakpoints are the default breakpoints. A special breakcode is patched to memory so it only can be used in RAM or FLASH areas.There is no restriction in the number of software breakpoints.On-chip BreakpointsThe Blackfin processor has a total of six instruction and two data on-chip breakpoints.A pair of two breakpoints may be further grouped together to form a range breakpoint. A range breakpointcan be including or excluding. In the first case the core is stopped if an address in the range is detected, in the second case the core is stopped when an address outside of the range is observed.Breakpoint in ROMWith the command MAP.BOnchip<range> it is possible to inform the debugger about ROM(FLASH,EPROM) address ranges in target. If a breakpoint is set within the specified address range the debugger uses automatically the available on-chip breakpoints.Example for BreakpointsAssume you have a target with FLASH from 0x20000000 to 0x200FFFFF and RAM from 0x0 to 0x1000000. The command to configure TRACE32 correctly for this configuration is: Map.BOnchip 0x20000000--0x200FFFFFThe following breakpoint combinations are possible.Software breakpoints:Break.Set 0x0 /Program; Software Breakpoint 1Break.Set 0x1000 /Program; Software Breakpoint 2On-chip breakpoints:Break.Set 0x20000100 /Program; On-chip Breakpoint 1Break.Set 0x2000ff00 /Program; On-chip Breakpoint 2Memory ClassesThe following memory classes are available: Memory Class DescriptionP ProgramD DataCPU specific TrOnchip CommandsThe TrOnchip command group is not available for the Blackfin debugger.JTAG ConnectorSignal Pin Pin SignalGND12EMU-N/C34GNDVDDIO56TMSN/C78TCKN/C910TRST-N/C1112TDIGND1314TDOJTAG Connector Signal Description CPU Signal TMS JTAG-TMS,TMSoutput of debuggerTDI TDI JTAG-TDI,output of debuggerTCK TCK JTAG-TCK,output of debugger/TRST /TRST JTAG-TRST,output of debuggerTDO TDO JTAG-TDO,input for debugger/EMU JTAG Emulation Flag /EMUVDDIO VDDIO This pin is used by the debugger to sense the targetI/O voltage and to set the drive levels accordingly. Ifthe sensed voltage level is too low (e.g. target has nopower) the debugger powers down its drivers toprevent the target from damage.。
TRACE32 调试器使用指南 TRACE32 Trace Tutorial说明书
T race T utorial Release 02.2023TRACE32 Online HelpTRACE32 DirectoryTRACE32 IndexTRACE32 Debugger Getting Started ..............................................................................................Trace Tutorial (1)History (3)About the Tutorial (3)What is Trace? (3)Trace Use Cases4Trace Methods (5)Simulator Demo (6)Trace Configuration (7)Trace Recording (8)Displaying the Trace Results (10)Trace List10 Displaying Function Run-Times13 Graphical Charts13 Numerical Statistics and Function Tree14 Duration Analysis15 Distance Analysis16 Variable Display17 Track Option18Searching Trace Results (19)Trace Save and Load (20)Version 10-Feb-2023 History18-Jun-21New manual.About the TutorialThis tutorial is an introduction to the trace functionality in TRACE32. It shows how to perform a tracerecording and how to display the recorded trace information.For simplicity, we use in this tutorial a TRACE32 Instruction Set Simulator, which offers a full tracesimulation. The steps and features described in this document are however valid for all TRACE32 products with trace support.The tutorial assumes that the TRACE32 software is already installed. Please refer to “TRACE32Installation Guide” (installation.pdf) for information about the installation process.Please refer to “ICD Tutorial” (icd_tutorial.pdf) for an introduction to debugging in TRACE32 PowerView. What is Trace?T race is the continuous recording of runtime information for later analysis. In this tutorial, we use the term trace synonymously with core trace. A core trace generates information about program execution on a core,i.e. program flow and data trace. The TRACE32 Instruction Set Simulator used in this tutorial supports a fulltrace simulation including the full program flow as well as all read and write data accesses to the memory. A real core may not support all types of trace information. Please refer to your Processor Architecture Manual for more information.Trace Use CasesT race is mainly used in the following cases:1.Understand the program execution in detail in order to find complex runtime errors more quickly.2.Analysis of the code performance of the target code3.Verification of real-time requirements4.Code-coverage measurementsTrace MethodsTRACE32 supports various trace methods. The trace method can be selected in the Trace configuration window, which can be opened from the menu Trace > Configuration…If a trace method is not supported by the current hardware/software setup, it is greyed out in the trace configuration window. NONE means that no trace method is selected.We use in this tutorial the trace method Analyzer. Please refer to the description of the commandTrace.METHOD for more information about the different trace methods.Simulator DemoWe use in this tutorial a TRACE32 Simulator for Arm. The described steps are however valid for the TRACE32 Simulator for other core architectures.T o load a demo on the simulator, follow these steps:1.Start the script search dialog from the menu File > Search for scripts…2.Enter in the search field “compiler demo”3.Select a demo from the list with a double click, a PSTEP window will appear. Press the“Continue” button.We will use here the demo “GNU C Example for SRAM”.Trace ConfigurationIn order to set up the trace, follow these steps:1.Open the menu Trace > Configuration… The trace method Analyzer [A] should be selected perdefault. If this is not the case, select this trace method2.Clear the contents of the trace buffer by pressing the Init button [B].3.Select the trace operation mode [C].In mode Fifo , new trace records will overwrite older records. The trace buffer includes thus always the last trace cycles before stopping the recording.In Mode Stack , the recording is stopped if the trace buffer is full. The trace buffer always includes in this case the first cycles after starting the recording.Mode Leash is similar to mode Stack , the program execution is however stopped when the trace buffer is nearly full.TRACE32 supports other trace modes. Some of these modes depend on the core architecture. Please refer to the documentation of the command Trace.Mode for more information. We will keep here the default trace mode selection, which is Fifo .4.The SIZE field [D] indicates the size of the trace buffer. As we are using a TRACE32 Simulator, the trace buffer is reserved by the TRACE32 PowerView application on the host. It is thuspossible to increase the size of this buffer. If a TRACE32 trace hardware is used with a real chip, the size of the trace buffer is limited by the size of the memory available on the trace tool.In order to have a longer trace recording, we will set the trace buffer size to 10000000.BACDThe same configuration steps can be performed using the following PRACTICE script:Trace RecordingPress the Go button to start the program execution.The trace recording is automatically started with the program execution. The state in the Trace window changes from OFF to Arm [A]. The used field displays the fill state of the trace buffer [B].In order to stop the trace recording, stop the program execution with the Break button. The state in the trace window changes to OFF .Trace.METHOD Analyzer Trace.InitTrace.Mode FifoTrace.SIZE 10000000.BACThe trace recording is automatically started and stopped when starting and stopping the program execution because of the AutoArm[C] setting in the Trace window, which is per default enabled. The trace recording can also be started/stopped manually while the program execution is running using the radio buttons Armand OFF of the Trace window [A].Displaying the Trace ResultsTRACE32 offers different view for displaying the trace results. This document shows some examples.Please note that the trace results can only be displayed if the trace state in the Trace window is OFF. It is not possible to display the trace results while recording.The caption of a TRACE32 window includes the TRACE32 command that can be executed in the TRACE32 command line or in a PRACTICE script to open this window, e.g. here Trace.ListTrace ListA list view of the trace results can be opened from the menu T race > List > Default. The same window canbe opened from the Trace configuration window by pressing the List button.The Trace.List window displays the recorded trace packets together with the corresponding assembler and source code.In our case, trace packets are program fetches (cycle fetch) or data accesses (e.g. wr-long and rd-long for 32bit write and read accesses). Each trace packet has a record number displayed in the record column. The record number is a negative index for Fifo mode.As we are using a Simulator, each assembly instruction has an own trace packet. This is not the case with a real hardware trace.The displayed information can be reduced using the Less button. By pressing Less three times, only the high-level source code is displayed. This can be reverted using the More button.A double click on a line with an assembly instruction or high-level source code opens a List window showing the corresponding line in the code.Using the TRACE32 menu Trace > List > Tracing with Source , you get a Trace.List and a List /Track window. When doing a simple click on a line in the Trace.List window, the List window will automaticallydisplay the corresponding code line.The timing information (see ti.back column) is generated in this case by the TRACE32 Instruction Set Simulator. With a real core trace, timestamps are either generated by the TRACE32 trace hardware or by the onchip trace module.Double clickSimpleclickDisplaying Function Run-TimesTRACE32 supports nested and flat function run-time analysis based on the trace results. Please refer to the video “Flat vs. Nesting Function Runtime Analysis” for an introduction to function run-time analysis inTRACE32:/tut_profiling.htmlGraphical ChartsBy selecting the menu Trace > Chart > Symbols, you can get a graphical chart that shows the distribution of program execution time at different symbols. The displayed results are based on a flat analysis:The corresponding nesting analysis can be displayed using the menu Perf > Function Runtime > Show as Timing.The In and Out buttons can be used to zoom in/out. Alternatively, you can select a position in the window and then use the mouse wheel to zoom in/out.Numerical Statistics and Function TreeThe menu entry Perf > Function Runtime >Show Numerical displays numerical statistics for each function with various information as total run-time, minimum, maximum and average run-times, ratio, and number of function calls.ABParents [A] displays for example a caller tree for the selected function. By doing a right mouse click on func1 and selecting Parents, we see the run-times of the functions func2 and func9, which have called func1 in thetrace recording.Children [B] displays the run-times of the functions called by the selected function, for example here the function subst called by the function encode.A function call tree view of all function recorded in the trace can be displayed using the menu entries Perf >Function Runtime > Show as Tree or Perf > Function Runtime > Show Detailed Tree.Duration AnalysisBy doing a right mouse click on a function in the numerical statistics window (Trace.STATistic.Func) then selecting Duration Analysis, you get an analysis of the function run-times between function entry and exit including the time spent in called subroutines, e.g. here for the function subst (P:0x114C corresponds to the start address of the subst function):The time interval can be changed using the Zoom buttons.Distance AnalysisBy doing a right mouse click on a function in the numerical statistics window (Trace.STATistic.Func) then selecting Distance Analysis, you can get run-times between two consecutive calls of the selected function,e.g. here for the function subst (P:0x114C corresponds to the start address of the subst function):Variable DisplayThe Trace.ListVar command allows to list recorded variables in the trace. If the command is used without parameters all recorded variables are displayed:Y ou can optionally add one or multiple variables as parameters.Example: display all accesses to the variables plot1 and plot2The Draw button can then be used to plot the displayed variables graphically against time. This corresponds to the following TRACE32 command:Please refer for more information about the Trace.DRAW command to “Application Note forTrace.DRAW” (app_trace_draw.pdf).Trace.ListVar Trace.ListVar %DEFault plot1 plot2Trace.DRAW.Var %DEFault plot1 plot2Track OptionThe /Track options allows to track windows that display the trace results. Y ou just need to add the /Track option after the command that opens a trace window, e.g.Trace.List /TrackThe cursor will then follow the movement in other trace windows, e.g. Trace.Chart.Func. Default is time tracking. If no time information is available, tracking to record number is performed.TRACE32 windows that displays the trace results graphically, e.g. Trace.Chart.Func, additionally accept the /ZoomTrack option. If the tracking is performed with another graphical window, the same zoom factor is used in this case.Trace.Chart.Func /ZoomTrackSearching Trace ResultsThe Find button allows to search for specific information in the trace results.Example 1: find the first call of function func21.Enter “func2” under address / expression2.Select Program under cycle3.Press the Find First button. The next entries to func2 in the trace can then be found using theNext buttonExample 2: Find all write accesses to the variable mstatic1 with the value 0x01.Enter “mstatic1” under address / expression2.Select Write under cycle3.Enter 0x0 under Data4.Press the Find All buttonPlease refer to “Application Note for Trace.Find” (app_trace_find.pdf) for more information about Trace.Find.Trace Save and LoadThe recorded trace can be stored in a file using the command Trace.SAVE , e.g.The saved file can then be loaded in TRACE32 PowerView using the command Trace.LOADThe TRACE32 trace display windows will show in this case a LOAD message in the low left cornerPlease note that TRACE32 additionally allows to export/import the trace results in different formats. Refer to the documentation of the command groups Trace.EXPORT and Trace.IMPORT for more information. Trace.SAVE file.adTrace.LOAD file.ad。
TRACE32 pdebug Target Server for ARM 用户手册说明书
TRACE32 pdebug T arget Server for ARMRelease 09.2023TRACE32 Online HelpTRACE32 DirectoryTRACE32 IndexTRACE32 Documents ...................................................................................................................... OS Awareness Manuals ................................................................................................................ OS Awareness and Run Mode Debugging for QNX ................................................................ TRACE32 pdebug Target Server for ARM .. (1)Operation Theory (3)Quick Start of the TRACE32 pdebug Front-end4Pdebug Front-end Specific Commands (6)SYStem.Mode Establish communication to debug agent6 SYStem.PORT Set communication settings6Version 09-Oct-2023Operation TheoryThe TRACE32 pdebug front-end is a software debugger solution for QNX. It provides single processdebugging.pdebug is a QNX application that provides access to process-level debugging from a remote host.Single process debugging works as follows:•pdebug is started together with the communication parameters and the process name on the target via the terminal window.•TRACE32 links to pdebug via Ethernet or RS232 and thus becomes the front-end for debugging.Quick Start of the TRACE32 pdebug Front-endThe TRACE32 pdebug front-end is set up for single process debugging as follows:1.Start pdebug on the target.2.Start TRACE32 as pdebug front-end. To do so, edit your configuration file (default: config.t32) and insert the statementrm the debugger about the CPU type on your target using the SYStem.CPU command e.g.4.Define the communication parameters with the SYStem.PORT command eg:5.Establish the communication to the pdebug agent with SYStem.Mode Attach :6.Load the symbols of the process to get symbol information (apply /NoCODE option to load symbols only).7.Go till mainA simple start sequence is shown below:PBI=QNXSYStem.CPU *SYStem.PORT 10.0.0.1:8000SYStem.Mode AttachData.LOAD.Elf myprocess /NoCODEGo main ListSYStem.Down WinCLEARSYStem.CPU *SYStem.PORT 10.0.0.1:8000SYStem.Mode AttachData.LOAD.ELF myprocess /NoCODE Go main List.Mix ENDDO; switch the debugger to down state ; clear all windows; select your target CPU; define communication parameters ; connect to pdebug; load the process symbols ; enter the process; open source code windowThe list of running tasks can be displayed using the command TASK.List.tasks.•To attach to a running process, use TASK.select.•To start a new process for debugging, use TASK.RUN.•To detach form a process, use TASK.DETach.•To kill a process, use TASK.KILL.Pdebug Front-end Specific CommandsSYStem.Mode Establish communication to debug agent Format:SYStem.Mode <mode><mode>:DownAttachDefault: DownDown TRACE32 has no connection to pdebug.Attach TRACE32 establishes the connection to pdebug.If you switch from Up to Down:•The process is killed.•The connection is closed.SYStem.PORT Set communication settings Format:SYStem.PORT <settings><mode>:COM1 BAUD=9600HOST:PORTSets the communication parameters. Y ou can use a serial or a TCP communication.SYStem.PORT COM1 baud=9600SYStem.PORT 10.1.2.99:8000。
TRACE32调试技巧
TRACE32调试技巧1.掌握TRACE32命令语法。
TRACE32使用一种类似于汇编语言的命令语法，了解和熟悉这些命令可以提高对调试环境的理解和使用。
2.使用TRACE32的源代码浏览和功能。
TRACE32可以直接打开源代码文件，并支持跳转、和定位到指定代码位置。
这个功能非常有用，可以提供更详细的调试信息。
3.使用断点和观察点。
TRACE32支持不同类型的断点和观察点，包括地址断点、条件断点、数据断点等。
合理使用这些断点和观察点可以精确地定位问题和跟踪变量值的变化。
4.使用TRACE32的软件仿真功能。
TRACE32可以模拟目标系统的操作环境，并在主机上进行软件调试。
这种模拟可以提供更快速和安全的调试环境，同时也方便了调试任务的并行执行。
5.学会使用TRACE32的事件记录功能。
TRACE32可以记录目标系统的事件流，并生成详细的事件记录文件。
这些文件可以被用于分析目标系统的运行状态、调试问题和优化性能。
6.添加自定义的TRACE32脚本和命令。
TRACE32支持用户自定义脚本和命令，可以根据实际需要扩展和定制TRACE32的功能。
这可以帮助提高调试效率，并解决特定的调试问题。
7.学习TRACE32的调试工具链集成。
TRACE32可以与其他开发工具集成，包括编译器、汇编器、链接器和性能分析器等。
学习如何使用TRACE32和这些工具一起工作，可以提供更完整的调试解决方案。
8.利用TRACE32的调试数据可视化功能。
TRACE32可以通过图表、图像和统计数据来展示和分析调试数据。
这可以帮助开发人员更直观地理解和评估调试结果。
9.使用TRACE32的远程调试功能。
TRACE32支持通过网络远程调试目标系统，这对于分布式系统开发和调试非常有用。
远程调试可以提供灵活性和便利性，减少不必要的移动和安装工作。
10.参考TRACE32的在线文档和示例。
TRACE32提供了全面的在线文档和示例，可以帮助开发人员更好地理解和使用TRACE32、学习这些文档和示例是提高TRACE32调试技巧的有效途径。
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目录1．系统组成1．1硬件1．1.1主机1．1.2调试电缆1．1.3通过USB与PC连接1．1.4通过JTAG与目标连接1．1.5对PC硬件的要求1．1.6对目标板硬件的要求1．1.7加电1．2软件1．2.1驱动程序的安装2．PowerView调试界面的使用3．1 打开调试界面3．2 JTAG连接设置3．3 运行脚本文件3．4 观察/修改寄存器3．5 观察/修改存储器3．6 下载程序3．7 观察符号表3．8 打开程序列表窗口3．9 单步执行程序3．10 设置软件断点3．11 设置Onchip硬件断点3．12 设置数据观察断点3．13 全速运行程序3．14 停止运行程序3．15 观察变量3．16 观察堆栈3．17 在线Flash编程1．系统组成TRACE-ICP调试系统由硬件和软件两部分组成，硬件是自行研发的，软件是第三方的。
下面分成硬件和软件两部分来介绍。
1．1硬件TRACE-ICP的硬件设计采用模块化的结构，分为主机和调试电缆两部分。
1．1.1主机下面三张照片是TRACE-ICP主机的顶视图和前视图以及后视图。
图一、TRACE-ICP顶视图图二、TRACE-ICP前视图图三、TRACE-ICP后视图在图二中的连接器是标准DB25/M连接器，用于连接调试电缆。
在图三中，有两个连接器和一个LED指示灯。
左边的连接器是USB接口，用于通过USB电缆和PC连接。
右边的连接器是TRACE-ICP的外接5VDC电源接口。
TRACE-ICP可以通过USB供电，在USB供电不足的情况下，使用外接电源。
LED指示灯是TRACE-ICP的电源指示灯。
1．1.2调试电缆下图是TRACE-ICP的调试电缆的照片。
图四、TRACE-ICP的调试电缆TRACE-ICP的调试电缆有两个连接端，一个是标准的DB25/F连接器，用于和TRACE-ICP主机相连，另一个是针距为2.54毫米的标准IDC20连接器，用于和目标板连接。
这个IDC20接口通常称为JTAG接口，因为这个接口是与目标板上的ARM处理器的JTAG信号连接的。
图中的20针扁平电缆可以通过拔插的方式更换。
1．1.3通过USB与PC连接USB电缆按照接头连接器的口径来分，有一大一小。
大的一端连接PC机，小的一端连接TRACE-ICP主机。
下面的图五和图六说明了这两种连接情况。
图五、USB线与PC连接图六、USB线与TRACE-ICP连接1．1.4通过JTAG与目标连接目标板上的JTAG调试接口的信号定义如下图所示。
图七、JTAG调试接口的信号定义目标板上的JTAG调试接口使用针距为2.54毫米的IDC20连接器。
调试电缆上的IDC20连接器的上面有一个三角印记，该印记所对应的引脚连接目标板JTAG接口的1脚。
TRACE-ICP与目标板的连接情况如下图所示。
图八、TRACE-ICP与目标板的连接1．1.5对PC硬件的要求要求连接TRACE-ICP的PC能够提供标准的USB接口。
1．1.6对目标板硬件的要求目标处理器基于ARM7/9内核，处理器I/O引脚电源电压为1.8到3.3伏。
1．1.7加电首先通过JTAG接口将TRACE-ICP和目标板连接，注意目标板的JTAG接口信号要与TRACE-ICP的调试电缆的信号一一对应，图七所示是TRACE-ICP的调试电缆的JTAG接口信号的线序。
先给TRACE-ICP加电，再给目标板加电。
TRACE-ICP的加电就是通过USB线与已上电的PC连接。
如果TRACE-ICP是通过USB HUB与PC连接，而USB HUB的供电能力又不足，可以选择一个接头为内正外负的5VDC电源通过TRACE-ICP后面的外接电源接口给TRACE-ICP供电。
1．2软件TRACE-ICP能够使用德国Lauterbach公司的PowerView调试软件，能够使用GDB调试软件。
1．2.1 驱动程序的安装当第一次将TRACE-ICP通过USB线与PC连接的时候，如果是在Windows操作系统下，系统将会提示安装设备驱动程序。
驱动程序在安装盘的”bin”目录下,文件名是t32usb.inf和t32usbxp.sys。
建议客户以手动方式安装驱动程序，速度快。
安装步骤如下几幅图所示。
图九、选择手动安装驱动程序图十、选择驱动程序图十一、安装驱动程序图十二、驱动程序安装完成1．2.2 PowerView调试界面的安装运行安装盘根目录下的setup.bat文件。
在安装过程中，做下面的几个图示中的选择，就可以正确地安装好调试界面软件。
图十三、选择ICD安装当出现图十三所示的界面时，选择红色圆圈中的按钮。
图十四、选择USB接口安装当出现图十四所示的界面时，选择“USB Interface”。
图十五、选择不需要License安装当出现图十五所示的界面时，选择“License Key not necessary”。
图十六、选择安装目录当出现图十六所示的界面时，选择红色圆圈中的按钮，打开安装目录选择对话框，选择将要安装到的目录。
图十七、选择安装的处理器当出现图十七所示的界面时，选择图中蓝色条所示的处理器列表。
图十八、选择不注册当出现图十八所示的界面时，选择“Register later”，接下来，按照提示完成安装。
3．PowerView调试界面的使用3．1 打开调试界面从Windows开始—〉所有程序—〉TRACE32—〉Trace32 ICD ARM USB启动调试界面，如下图所示。
图二十一、启动调试界面启动之后的调试界面如下图所示。
图二十二、调试界面在图二十二中的红圈中的“system down”指示目标板已经供电，如果目标板电源电压低或没有的话，红圈的区域会显示“POWER DOWN”。
TRACE-ICP通过JTAG接口的1脚检测目标板电压，电压范围应该在1.8到3.3伏之间。
如图二十二中红色字体所指示的那样，调试界面分成五个区域，从上到下依次是主菜单区、快捷按钮区、工作区、行命令输入区、行命令软件区、状态显示区。
主菜单区是各种菜单命令的入口区域。
快捷按钮区是各种常用命令的快捷使用按钮。
用户可以自定义主菜单和快捷按钮。
工作区是各种对话框窗口的显示区域。
行命令输入区是各种命令通过手动输入执行的区域。
行命令软键区是协助用户输入行命令的区域，它提供所有行命令的软键输入方法。
状态显示区指示当前的调试状态。
3．2 JTAG连接设置该设置的作用是告诉调试界面目标板JTAG链路的设置情况，以便能够正确连接，这些设置主要包括：1、选择要调试的处理器型号。
2、是否有多个器件串联在同一个JTAG链路里，连接顺序如何，每个器件的JTAG IR寄存器的宽度是多少。
（情况一）3、JTAG时钟使用TCK还是RTCK。
TCK由TRACE-ICP提供，一般情况下选用10MHz。
RTCK是TRACE-ICP的TCK进入目标JTAG链路之后，从目标JTAG链路返回的时钟，它与目标处理器的时钟同步。
一般情况下，具有睡眠模式的处理器多选用RTCK作JTAG时钟，如ARM926EJ-S。
（情况二）4、通过JTAG与目标连接时，是否要先复位目标板。
JTAG口上的SRST信号产生复位信号。
（情况三）5、通过JTAG与目标连接时，是否要停止目标处理器运行。
（情况四）从主菜单“CPU”中选择“System Settings…”，打开如下图所示对话框。
从“CPU”下拉菜单里选择要调试的处理器。
图二十三、System Settings对话框对于前面描述的第一种情况，多个器件串联在同一个JTAG链上，用户需要在图二十三所示的对话框中选择“MultiCore”，打开MultiCore对话窗口，如下图所示。
图二十四、MultiCore对话框在图二十四中，最上方的红框中的部分描述多个器件在一个 JTAG 链上的位置。
所谓“JTAG串联”，就是一个器件的TDI和另一个器件的TDO相连，没有连接的TDI与JTAG口的TDI连接，没有连接的TDO与JTAG口的TDO 连接。
图二十四中的红框中的图形形象地描述了这种连接。
在图形中，“core”表示被调试的处理器，如ARM926EJ-S，“IRPOST”表示连接在JTAG TDI和“core”的TDI之间的器件的JTAG IR寄存器长度的和，在“IRPOST”下方的编辑框内要填入这个和的值，“DRPOST”表示连接在JTAG TDI和“core”的TDI之间的器件的数目，在“DRPOST”下方的编辑框内填入这个数目值，“IRPRE”表示连接在JTAG TDO和“core”的TDO之间的器件的JTAG IR 寄存器长度的和，在“IRPRE”下方的编辑框内要填入这个和的值，“DRPRE”表示连接在JTAG TDO和“core”的TDO之间的器件的数目，在“DRPRE”下方的编辑框内填入这个数目值。
填入上面四个值，就完成了JTAG MultCore 的设置。
对前面描述的第二种情况，JTAG时钟的选择，可以通过System Settings对话框上的JtagClock列表框来实现，如下图所示。
图二十五、JtagClock列表框图二十五中的红框中的部分就是JtagClock列表框，通过这个列表框用户可以选择JTAG时钟是TCK或RTCK，选择TCK的时候，顺便选择它的频率，5MHz 或10MHz或25MHz，也可以手动在编辑框中输入频率值，如1MHz。
对前面描述的第三种情况，通过JTAG与目标连接时，是否要先复位目标板，用户可以通过下图中红框中的单选钮进行选择。
图二十六、系统复位选择在图二十六中，红框中的“EnReset”单选钮如果在前面打勾（选择），表示在TRACE-ICP做JTAG连接时会做系统复位。
通过前面三种情况，用户完成了在JTAG连接动作之前的设置工作，接下来，用户就可以连接目标了。
这个连接通过下图中的红框中的“Up”或“Attach”单选钮来完成。
图二十七、JTAG连接在图二十七中，选择红框中的“Up”单选钮，JTAG通讯连接之后，目标处理器会停止执行，选择红框中的“Attach”单选钮，JTAG通讯连接之后，目标处理器处于它在JTAG通讯之前的状态，原来是运行的，那么，它现在仍然保持运行状态，这就是我们前面描述的第四种情况，如果用户在选择“Up”或“Attach”单选钮之后，在“Up”前面的小园框中有一个绿色园点，表明JTAG 通讯已经连接成功。
如下图所示。
图二十八、JTAG UP连接成功如果选择“Attach”按钮并且目标处理器正在运行的话，在界面的状态显示区会有一个绿色的“Running”条显示，如下图所示。
图二十九、JTAG Attach连接成功在图二十九中，用户可以通过点击红圈中的按钮停止程序执行，以便观察程序当前的处理器执行状态。