Trace32 基础配置与调试
关于TRACE32使用说明
目录1．系统组成1．1硬件1．1.1主机1．1.2调试电缆1．1.3通过USB与PC连接1．1.4通过JTAG与目标连接1．1.5对PC硬件的要求1．1.6对目标板硬件的要求1．1.7加电1．2软件1．2.1驱动程序的安装2．PowerView调试界面的使用3．1 打开调试界面3．2 JTAG连接设置3．3 运行脚本文件3．4 观察/修改寄存器3．5 观察/修改存储器3．6 下载程序3．7 观察符号表3．8 打开程序列表窗口3．9 单步执行程序3．10 设置软件断点3．11 设置Onchip硬件断点3．12 设置数据观察断点3．13 全速运行程序3．14 停止运行程序3．15 观察变量3．16 观察堆栈3．17 在线Flash编程1．系统组成TRACE-ICP调试系统由硬件和软件两部分组成，硬件是自行研发的，软件是第三方的。
下面分成硬件和软件两部分来介绍。
1．1硬件TRACE-ICP的硬件设计采用模块化的结构，分为主机和调试电缆两部分。
1．1.1主机下面三张照片是TRACE-ICP主机的顶视图和前视图以及后视图。
图一、TRACE-ICP顶视图图二、TRACE-ICP前视图图三、TRACE-ICP后视图在图二中的连接器是标准DB25/M连接器，用于连接调试电缆。
在图三中，有两个连接器和一个LED指示灯。
左边的连接器是USB接口，用于通过USB电缆和PC连接。
右边的连接器是TRACE-ICP的外接5VDC电源接口。
TRACE-ICP可以通过USB供电，在USB供电不足的情况下，使用外接电源。
LED指示灯是TRACE-ICP的电源指示灯。
1．1.2调试电缆下图是TRACE-ICP的调试电缆的照片。
图四、TRACE-ICP的调试电缆TRACE-ICP的调试电缆有两个连接端，一个是标准的DB25/F连接器，用于和TRACE-ICP主机相连，另一个是针距为2.54毫米的标准IDC20连接器，用于和目标板连接。
trace32 基本原理
Trace32基本原理Trace32是一款用于调试和分析嵌入式系统的实时追踪工具。
它提供了强大的功能，可以帮助开发人员在嵌入式系统中定位和解决各种问题。
本文将详细介绍Trace32的基本原理，包括调试器的结构、调试会话的建立和调试过程中的基本操作。
1. 调试器的结构Trace32调试器的整体结构由多个模块组成，包括调试程序、调试接口、调试硬件和调试API。
下面将依次介绍每个模块的功能和原理。
1.1 调试程序：Trace32调试程序是一个运行在宿主主机上的软件，负责控制调试会话的建立、维护和管理。
它提供了用户界面和命令行接口，可以通过图形界面或命令行输入指令来控制调试会话。
1.2 调试接口：Trace32调试接口是连接目标系统和调试程序的桥梁，用于传输调试指令和数据。
它可以通过串口、以太网、USB等方式与目标系统进行通信。
调试接口还负责解析和执行调试指令，并将调试结果返回给调试程序。
1.3 调试硬件：Trace32调试硬件是一种嵌入在目标系统中的硬件模块，用于实时监控和跟踪目标系统的运行状态。
它可以通过调试接口与调试程序进行通信，并提供实时调试数据的获取和传输功能。
1.4 调试API：Trace32调试API是一组用于访问和控制Trace32调试器的接口和函数。
开发人员可以使用这些API来编写自定义的调试脚本和工具，实现自动化的调试和分析过程。
2. 调试会话的建立为了开始调试一个目标系统，首先需要建立一个调试会话。
调试会话是Trace32与目标系统之间的通信通道，通过这个通道可以传输和接收调试指令和数据。
建立调试会话的过程一般包括以下几个步骤：2.1 配置调试硬件：首先需要连接和配置Trace32调试硬件与目标系统的连接方式。
可以通过串口、以太网、USB等方式连接调试硬件，并设置相应的通信参数。
2.2 加载调试程序：在宿主主机上启动Trace32调试程序，并加载与目标系统对应的调试程序。
调试程序将根据目标系统的体系结构和硬件情况，自动适配对应的调试接口和硬件。
Lauterbach黑芯调试器TRACE32在线帮助说明书
Blackfin Debugger Release 09.2023Blackfin DebuggerTRACE32 Online HelpTRACE32 DirectoryTRACE32 IndexTRACE32 Documents ......................................................................................................................ICD In-Circuit Debugger ................................................................................................................Processor Architecture Manuals ..............................................................................................Blackfin ....................................................................................................................................Blackfin Debugger (1)Introduction (4)Brief Overview of Documents for New Users4 Demo and Start-up Scripts5 Location of Debug Connector5Warning (5)Quick Start JTAG (6)Troubleshooting (8)SYStem.Up Errors8FAQ (8)Configuration (9)System Overview9Blackfin specific SYStem Commands (10)SYStem.CONFIG Configure debugger according to target topology10 Daisy-Chain Example13 TapStates14 SYStem.CONFIG.CORE Assign core to TRACE32 instance15 SYStem.CPU CPU type selection16 SYStem.JtagClock JTAG clock selection17 SYStem.LOCK Lock and tristate the debug port17 SYStem.MemAccess Real-time memory access (non-intrusive)18 SYStem.Mode System mode selection19 SYStem.Option.IMASKASM Interrupt disable19 SYStem.Option.IMASKHLL Interrupt disable20Breakpoints (21)Software Breakpoints21 On-chip Breakpoints21 Breakpoint in ROM21Example for Breakpoints22 Memory Classes (23)CPU specific TrOnchip Commands (24)JTAG Connector (25)Blackfin DebuggerVersion 10-Oct-2023 IntroductionThis document describes the processor specific settings and features for the Blackfin Embedded Media Processor. TRACE32-ICD supports all Blackfin devices which are equipped with the JT AG debug interface.Please keep in mind that only the Processor Architecture Manual (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.If some of the described functions, options, signals or connections in this Processor Architecture Manual are only valid for a single CPU the name is added in brackets.Brief Overview of Documents for New UsersArchitecture-independent information:•“Training Basic Debugging” (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger.•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger. T32Start is only available for Windows.•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.Architecture-specific information:•“Processor Architecture Manuals”: These manuals describe commands that are specific for the processor architecture supported by your Debug Cable. T o access the manual for your processorarchitecture, proceed as follows:-Choose Help menu > Processor Architecture Manual.•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating system-aware debugging. The appropriate OS Awareness manual informs you how to enable theOS-aware debugging.Demo and Start-up ScriptsLauterbach provides ready-to-run start-up scripts for known Blackfin based hardware.To search for PRACTICE scripts, do one of the following in TRACE32 PowerView:•Type at the command line: WELCOME.SCRIPTS•or choose File menu > Search for Script.Y ou can now search the demo folder and its subdirectories for PRACTICE start-up scripts(*.cmm) and other demo software.Y ou can also manually navigate in the ~~/demo/blackfin/ subfolder of the system directory ofTRACE32.Location of Debug ConnectorLocate the debug connector on your target board as close as possible to the processor to minimize the capacitive influence of the trace length and cross coupling of noise onto the JT AG signals. WarningSignal LevelThe debugger output voltage follows the target voltage level. It supports a voltage range of 0.4…5.2V. ESD ProtectionNOTE:T o prevent debugger and target from damage it is recommended to connect ordisconnect the debug cable only while the target power is OFF.Recommendation for the software start:•Disconnect the debug cable from the target while the target power is off.•Connect the host system, the TRACE32 hardware and the debug cable.•Start the TRACE32 software.•Connect the debug cable to the target.•Switch the target power ON.Power down:•Switch off the target power.•Disconnect the debug cable from the target.Quick Start JTAGStarting up the debugger is done as follows:1.Select the device prompt B: for the ICD Debugger, if the device prompt is not active after the TRACE32 software was started.2.Select the CPU type to load the CPU specific settings.3.Enter debug mode:This command resets the CPU and enters debug mode. After the execution of this command access to the registers and to memory is possible. Before performing the first access to external SDRAM or FLASH the External Bus Interface Unit (EBIU) must be configured.4.The following command sequence is for the BF537 processor and configures the SDRAM controller with default values that were derived for maximum flexibility. They work for a system clock frequency between 54MHz and 133MHz.In the example a ST M29W320DB flash device is used in 16-bit mode. All four memory banks and CLKOUT are enabled.B:SYStem.CPU BF537SYStem.Up; configure SDRAM controllerData.Set 0xFFC00A1sLONG 0x0091998D Data.Set 0xFFC00A14 %WORD 0x0025Data.Set 0xFFC00A1C %WORD 0x03A0; EBIU_SDGCTL ; EBIU_SDBCTL ; EBIU_SDRRC; enable all flash memory banks and clock outData.Set 0xFFC00A00 %WORD 0x00FF; EBIU_AMGCTL; ST M29W320DB flash device in 16-bit modeFLASH.Create 1. 0x20000000--0x20003FFF 0x4000 AM29LV100 Word FLASH.Create 1. 0x20004000--0x20007FFF 0x2000 AM29LV100 Word FLASH.Create 1. 0x20008000--0x2000FFFF 0x8000 AM29LV100 Word FLASH.Create 1. 0x20010000--0x203FFFFF 0x10000 AM29LV100 Word5.Load the program.Data.LOAD.Elf demo.dxe; The file demo.dxe is in ELF format The option of the Data.LOAD command depends on the file format generated by the compiler. A detailed description of the Data.LOAD command is given in the “General Commands Reference”. The start-up sequence can be automated using the programming language PRACTICE. A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm, ASCII format) and executed with the command DO<file>.B::; Select the ICD device promptWinClear; Delete all windowsSYStem.CPU BF537; select the processorSYStem.Up; Reset the target and enter debug modeData.Load.Elf sieve.dxe; Load the applicationRegister.Set PC main; Set the PC to function mainList.Mix; Open disassembly window *) Register.view; Open register window *) PER.view; Open window with peripheral register *) Break.Set sieve; Set breakpoint to function sieveBreak.Set 0x1000 /p; Set on-chip breakpoint to address 1000; Refer to the restrictions in; On-chip Breakpoints.*) These commands open windows on the screen. The window position can be specified with the WinPOS command.TroubleshootingSYStem.Up ErrorsThe SYStem.Up command is the first command of a debug session where communication with the target is required. If you receive error messages while executing this command this may have the following reasons.All The target has no power.All There are additional loads or capacities on the JTAG lines.All The JTAG clock is too fast.FAQPlease refer to https:///kb.Configuration System OverviewBlackfin specific SYStem CommandsSYStem.CONFIG Configure debugger according to target topologyThe four parameters IRPRE, IRPOST , DRPRE, DRPOST are required to inform the debugger about the T AP controller position in the JT AG chain, if there is more than one core in the JT AG chain (e.g. ARM + DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up . See Daisy-chain Example .For some CPU selections (SYStem.CPU ) the above setting might be automatically included, since the required system configuration of these CPUs is known.T riState has to be used if several debuggers (“via separate cables”) are connected to a common JT AG port at the same time in order to ensure that always only one debugger drives the signal lines. T APState and TCKLevel define the T AP state and TCK level which is selected when the debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down resistor, other trigger inputs need to be kept in inactive state.Format:SYStem.CONFIG <parameter> <number_or_address>SYStem.MultiCore <parameter> <number_or_address> (deprecated)<parameter>:CORE <core><parameter>:(JTAG):DRPRE <bits>DRPOST <bits>IRPRE <bits>IRPOST <bits>DAPDRPOST <bits>DAPDRPRE <bits>DAPIRPOST <bits>DAPIRPRE <bits>TAPState <state>TCKLevel <level>TriState [ON | OFF ]Slave [ON | OFF ]DEBUGPORTTYPE [JTAG | SWD ]SWDPIDLEHIGH [ON | OFF ]SWDPTargetSel <value>CORE For multicore debugging one TRACE32 PowerView GUI has to be startedper core. To bundle several cores in one processor as required by thesystem this command has to be used to define core and processorcoordinates within the system topology.Further information can be found in SYStem.CONFIG.CORE.… DRPOST <bits>Defines the TAP position in a JT AG scan chain. Number of TAPs in theJTAG chain between the TDI signal and the TAP you are describing. InBYPASS mode, each TAP contributes one data register bit. See possibleTAP types and example below.Default: 0.… DRPRE <bits>Defines the TAP position in a JT AG scan chain. Number of TAPs in theJTAG chain between the TAP you are describing and the TDO signal. InBYPASS mode, each TAP contributes one data register bit. See possibleTAP types and example below.Default: 0.… IRPOST <bits>Defines the TAP position in a JT AG scan chain. Number of InstructionRegister (IR) bits of all TAPs in the JT AG chain between TDI signal andthe TAP you are describing. See possible T AP types and example below.Default: 0.… IRPRE <bits>Defines the TAP position in a JT AG scan chain. Number of InstructionRegister (IR) bits of all TAPs in the JTAG chain between the T AP you aredescribing and the TDO signal. See possible TAP types and examplebelow.Default: 0.TAPState(default: 7 = Select-DR-Scan) This is the state of the TAP controller whenthe debugger switches to tristate mode. All states of the JTAG T APcontroller are selectable.TCKLevel (default: 0) Level of TCK signal when all debuggers are tristated. TriState(default: OFF) If several debuggers share the same debug port, thisoption is required. The debugger switches to tristate mode after eachdebug port access. Then other debuggers can access the port. JT AG:This option must be used, if the JTAG line of multiple debug boxes areconnected by a JTAG joiner adapter to access a single JTAG chain. Slave(default: OFF) If more than one debugger share the same debug port, allexcept one must have this option active.JTAG: Only one debugger - the “master” - is allowed to control the signalsnTRST and nSRST (nRESET).DEBUGPORTTYPE [JTAG | SWD]It specifies the used debug port type “JT AG”, “SWD”. It assumes the selected type is supported by the target.Default: JT AG.SWDPIdleHigh [ON | OFF]Keep SWDIO line high when idle. Only for Serialwire Debug mode. Usually the debugger will pull the SWDIO data line low, when no operation is in progress, so while the clock on the SWCLK line is stopped (kept low).Y ou can configure the debugger to pull the SWDIO data linehigh, when no operation is in progress by usingSYStem.CONFIG SWDPIdleHigh ONDefault: OFF.SWDPTargetSel<value>Device address in case of a multidrop serial wire debug port.Default: none set (any address accepted).Daisy-Chain ExampleBelow, configuration for core C.Instruction register length of •Core A: 3 bit •Core B: 5 bit •Core D: 6 bitSYStem.CONFIG.IRPRE 6.; IR Core D SYStem.CONFIG.IRPOST 8.; IR Core A + B SYStem.CONFIG.DRPRE 1.; DR Core D SYStem.CONFIG.DRPOST 2.; DR Core A + BSYStem.CONFIG.CORE 0. 1.; Target Core C is Core 0 in Chip 1Core A Core B Core CCore D TDOTDI Chip 0Chip 1TapStates0Exit2-DR1Exit1-DR2Shift-DR3Pause-DR4Select-IR-Scan5Update-DR6Capture-DR7Select-DR-Scan8Exit2-IR9Exit1-IR10Shift-IR11Pause-IR12Run-Test/Idle13Update-IR14Capture-IR15Test-Logic-ResetSYStem.CONFIG.CORE Assign core to TRACE32 instance Format:SYStem.CONFIG.CORE<core_index><chip_index>SYStem.MultiCore.CORE<core_index><chip_index> (deprecated) <chip_index>:1 (i)<core_index>:1…kDefault core_index: depends on the CPU, usually 1. for generic chipsDefault chip_index: derived from CORE= parameter of the configuration file (config.t32). The COREparameter is defined according to the start order of the GUI in T32Start with ascending values.T o provide proper interaction between different parts of the debugger, the systems topology must bemapped to the debugger’s topology model. The debugger model abstracts chips and sub cores of these chips. Every GUI must be connect to one unused core entry in the debugger topology model. Once the SYStem.CPU is selected, a generic chip or non-generic chip is created at the default chip_index.Non-generic ChipsNon-generic chips have a fixed number of sub cores, each with a fixed CPU type.Initially, all GUIs are configured with different chip_index values. Therefore, you have to assign thecore_index and the chip_index for every core. Usually, the debugger does not need further information to access cores in non-generic chips, once the setup is correct.Generic ChipsGeneric chips can accommodate an arbitrary amount of sub-cores. The debugger still needs information how to connect to the individual cores e.g. by setting the JT AG chain coordinates.Start-up ProcessThe debug system must not have an invalid state where a GUI is connected to a wrong core type of a non-generic chip, two GUIs are connected to the same coordinate or a GUI is not connected to a core. The initial state of the system is valid since every new GUI uses a new chip_index according to its CORE= parameter of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must be merged by calling SYStem.CONFIG.CORE.SYStem.CPU CPU type selection Format:SYStem.CPU <cpu><cpu>:BF531 | BF532 | BF533 | BF534…Default selection: BF534.Selects the CPU type.SYStem.JtagClock JT AG clock selection Format:SYStem.JtagClock [<frequency>]SYStem.BdmClock<frequency>(deprecated)Default frequency: 1MHz.Selects the JT AG port frequency (TCK). Any frequency up to 50MHz can be entered, it will be generated by the debuggers internal PLL.For CPUs which come up with very low clock speeds it might be necessary to slow down the JT AGfrequency. After initialization of the CPUs PLL the JT AG clock can be increased.SYStem.LOCK Lock and tristate the debug port Format:SYStem.LOCK [ON | OFF]Default: OFF.If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the SYStem.LOCK command is to give debug access to another tool.SYStem.MemAccess Real-time memory access (non-intrusive) Format:SYStem.MemAccess Denied | StopAndGo | BTCBTC“BTC” allows a non-intrusive memory access while the core is running, if aBackground T elemetry Channel (BTC) is defined in your application. Anyinformation on how to create such a channel can be found in AnalogDevices’ VisualDSP++ user’s manual. The JT AG clock speed should be asfast as possible to get good performanceDenied Real-time memory access during program execution to target is disabled.StopAndGo Temporarily halts the core(s) to perform the memory access. Each stoptakes some time depending on the speed of the JT AG port, the number ofthe assigned cores, and the operations that should be performed.SYStem.Mode System mode selectionFormat:SYStem.Mode <mode>SYStem.Attach (alias for SYStem.Mode Attach)SYStem.Down (alias for SYStem.Mode Down)SYStem.Up (alias for SYStem.Mode Up)<mode>:DownGoAttachUpDown Disables the debugger.Go Resets the target with debug mode enabled and prepares the CPU fordebug mode entry. After this command the CPU is in the system.upmode and running. Now, the processor can be stopped with the breakcommand or if a break condition occurs.Attach User program remains running (no reset) and the debug interface isinitialized.Up Resets the target and sets the CPU to debug mode. After execution ofthis command the CPU is stopped and prepared for debugging.StandBy Not supported.NoDebug Not supported.SYStem.Option.IMASKASM Interrupt disable Format:SYStem.Option.IMASKASM [ON | OFF]Mask interrupts during assembler single steps. Useful to prevent interrupt disturbance during assembler single stepping.SYStem.Option.IMASKHLL Interrupt disable Format:SYStem.Option.IMASKHLL [ON | OFF]Mask interrupts during HLL single steps. Useful to prevent interrupt disturbance during HLL single stepping.BreakpointsThere are two types of breakpoints available: software breakpoints and on-chip breakpoints. Software BreakpointsSoftware breakpoints are the default breakpoints. A special breakcode is patched to memory so it only can be used in RAM or FLASH areas.There is no restriction in the number of software breakpoints.On-chip BreakpointsThe Blackfin processor has a total of six instruction and two data on-chip breakpoints.A pair of two breakpoints may be further grouped together to form a range breakpoint. A range breakpointcan be including or excluding. In the first case the core is stopped if an address in the range is detected, in the second case the core is stopped when an address outside of the range is observed.Breakpoint in ROMWith the command MAP.BOnchip<range> it is possible to inform the debugger about ROM(FLASH,EPROM) address ranges in target. If a breakpoint is set within the specified address range the debugger uses automatically the available on-chip breakpoints.Example for BreakpointsAssume you have a target with FLASH from 0x20000000 to 0x200FFFFF and RAM from 0x0 to 0x1000000. The command to configure TRACE32 correctly for this configuration is: Map.BOnchip 0x20000000--0x200FFFFFThe following breakpoint combinations are possible.Software breakpoints:Break.Set 0x0 /Program; Software Breakpoint 1Break.Set 0x1000 /Program; Software Breakpoint 2On-chip breakpoints:Break.Set 0x20000100 /Program; On-chip Breakpoint 1Break.Set 0x2000ff00 /Program; On-chip Breakpoint 2Memory ClassesThe following memory classes are available: Memory Class DescriptionP ProgramD DataCPU specific TrOnchip CommandsThe TrOnchip command group is not available for the Blackfin debugger.JTAG ConnectorSignal Pin Pin SignalGND12EMU-N/C34GNDVDDIO56TMSN/C78TCKN/C910TRST-N/C1112TDIGND1314TDOJTAG Connector Signal Description CPU Signal TMS JTAG-TMS,TMSoutput of debuggerTDI TDI JTAG-TDI,output of debuggerTCK TCK JTAG-TCK,output of debugger/TRST /TRST JTAG-TRST,output of debuggerTDO TDO JTAG-TDO,input for debugger/EMU JTAG Emulation Flag /EMUVDDIO VDDIO This pin is used by the debugger to sense the targetI/O voltage and to set the drive levels accordingly. Ifthe sensed voltage level is too low (e.g. target has nopower) the debugger powers down its drivers toprevent the target from damage.。
TRACE32 调试器使用指南 TRACE32 Trace Tutorial说明书
T race T utorial Release 02.2023TRACE32 Online HelpTRACE32 DirectoryTRACE32 IndexTRACE32 Debugger Getting Started ..............................................................................................Trace Tutorial (1)History (3)About the Tutorial (3)What is Trace? (3)Trace Use Cases4Trace Methods (5)Simulator Demo (6)Trace Configuration (7)Trace Recording (8)Displaying the Trace Results (10)Trace List10 Displaying Function Run-Times13 Graphical Charts13 Numerical Statistics and Function Tree14 Duration Analysis15 Distance Analysis16 Variable Display17 Track Option18Searching Trace Results (19)Trace Save and Load (20)Version 10-Feb-2023 History18-Jun-21New manual.About the TutorialThis tutorial is an introduction to the trace functionality in TRACE32. It shows how to perform a tracerecording and how to display the recorded trace information.For simplicity, we use in this tutorial a TRACE32 Instruction Set Simulator, which offers a full tracesimulation. The steps and features described in this document are however valid for all TRACE32 products with trace support.The tutorial assumes that the TRACE32 software is already installed. Please refer to “TRACE32Installation Guide” (installation.pdf) for information about the installation process.Please refer to “ICD Tutorial” (icd_tutorial.pdf) for an introduction to debugging in TRACE32 PowerView. What is Trace?T race is the continuous recording of runtime information for later analysis. In this tutorial, we use the term trace synonymously with core trace. A core trace generates information about program execution on a core,i.e. program flow and data trace. The TRACE32 Instruction Set Simulator used in this tutorial supports a fulltrace simulation including the full program flow as well as all read and write data accesses to the memory. A real core may not support all types of trace information. Please refer to your Processor Architecture Manual for more information.Trace Use CasesT race is mainly used in the following cases:1.Understand the program execution in detail in order to find complex runtime errors more quickly.2.Analysis of the code performance of the target code3.Verification of real-time requirements4.Code-coverage measurementsTrace MethodsTRACE32 supports various trace methods. The trace method can be selected in the Trace configuration window, which can be opened from the menu Trace > Configuration…If a trace method is not supported by the current hardware/software setup, it is greyed out in the trace configuration window. NONE means that no trace method is selected.We use in this tutorial the trace method Analyzer. Please refer to the description of the commandTrace.METHOD for more information about the different trace methods.Simulator DemoWe use in this tutorial a TRACE32 Simulator for Arm. The described steps are however valid for the TRACE32 Simulator for other core architectures.T o load a demo on the simulator, follow these steps:1.Start the script search dialog from the menu File > Search for scripts…2.Enter in the search field “compiler demo”3.Select a demo from the list with a double click, a PSTEP window will appear. Press the“Continue” button.We will use here the demo “GNU C Example for SRAM”.Trace ConfigurationIn order to set up the trace, follow these steps:1.Open the menu Trace > Configuration… The trace method Analyzer [A] should be selected perdefault. If this is not the case, select this trace method2.Clear the contents of the trace buffer by pressing the Init button [B].3.Select the trace operation mode [C].In mode Fifo , new trace records will overwrite older records. The trace buffer includes thus always the last trace cycles before stopping the recording.In Mode Stack , the recording is stopped if the trace buffer is full. The trace buffer always includes in this case the first cycles after starting the recording.Mode Leash is similar to mode Stack , the program execution is however stopped when the trace buffer is nearly full.TRACE32 supports other trace modes. Some of these modes depend on the core architecture. Please refer to the documentation of the command Trace.Mode for more information. We will keep here the default trace mode selection, which is Fifo .4.The SIZE field [D] indicates the size of the trace buffer. As we are using a TRACE32 Simulator, the trace buffer is reserved by the TRACE32 PowerView application on the host. It is thuspossible to increase the size of this buffer. If a TRACE32 trace hardware is used with a real chip, the size of the trace buffer is limited by the size of the memory available on the trace tool.In order to have a longer trace recording, we will set the trace buffer size to 10000000.BACDThe same configuration steps can be performed using the following PRACTICE script:Trace RecordingPress the Go button to start the program execution.The trace recording is automatically started with the program execution. The state in the Trace window changes from OFF to Arm [A]. The used field displays the fill state of the trace buffer [B].In order to stop the trace recording, stop the program execution with the Break button. The state in the trace window changes to OFF .Trace.METHOD Analyzer Trace.InitTrace.Mode FifoTrace.SIZE 10000000.BACThe trace recording is automatically started and stopped when starting and stopping the program execution because of the AutoArm[C] setting in the Trace window, which is per default enabled. The trace recording can also be started/stopped manually while the program execution is running using the radio buttons Armand OFF of the Trace window [A].Displaying the Trace ResultsTRACE32 offers different view for displaying the trace results. This document shows some examples.Please note that the trace results can only be displayed if the trace state in the Trace window is OFF. It is not possible to display the trace results while recording.The caption of a TRACE32 window includes the TRACE32 command that can be executed in the TRACE32 command line or in a PRACTICE script to open this window, e.g. here Trace.ListTrace ListA list view of the trace results can be opened from the menu T race > List > Default. The same window canbe opened from the Trace configuration window by pressing the List button.The Trace.List window displays the recorded trace packets together with the corresponding assembler and source code.In our case, trace packets are program fetches (cycle fetch) or data accesses (e.g. wr-long and rd-long for 32bit write and read accesses). Each trace packet has a record number displayed in the record column. The record number is a negative index for Fifo mode.As we are using a Simulator, each assembly instruction has an own trace packet. This is not the case with a real hardware trace.The displayed information can be reduced using the Less button. By pressing Less three times, only the high-level source code is displayed. This can be reverted using the More button.A double click on a line with an assembly instruction or high-level source code opens a List window showing the corresponding line in the code.Using the TRACE32 menu Trace > List > Tracing with Source , you get a Trace.List and a List /Track window. When doing a simple click on a line in the Trace.List window, the List window will automaticallydisplay the corresponding code line.The timing information (see ti.back column) is generated in this case by the TRACE32 Instruction Set Simulator. With a real core trace, timestamps are either generated by the TRACE32 trace hardware or by the onchip trace module.Double clickSimpleclickDisplaying Function Run-TimesTRACE32 supports nested and flat function run-time analysis based on the trace results. Please refer to the video “Flat vs. Nesting Function Runtime Analysis” for an introduction to function run-time analysis inTRACE32:/tut_profiling.htmlGraphical ChartsBy selecting the menu Trace > Chart > Symbols, you can get a graphical chart that shows the distribution of program execution time at different symbols. The displayed results are based on a flat analysis:The corresponding nesting analysis can be displayed using the menu Perf > Function Runtime > Show as Timing.The In and Out buttons can be used to zoom in/out. Alternatively, you can select a position in the window and then use the mouse wheel to zoom in/out.Numerical Statistics and Function TreeThe menu entry Perf > Function Runtime >Show Numerical displays numerical statistics for each function with various information as total run-time, minimum, maximum and average run-times, ratio, and number of function calls.ABParents [A] displays for example a caller tree for the selected function. By doing a right mouse click on func1 and selecting Parents, we see the run-times of the functions func2 and func9, which have called func1 in thetrace recording.Children [B] displays the run-times of the functions called by the selected function, for example here the function subst called by the function encode.A function call tree view of all function recorded in the trace can be displayed using the menu entries Perf >Function Runtime > Show as Tree or Perf > Function Runtime > Show Detailed Tree.Duration AnalysisBy doing a right mouse click on a function in the numerical statistics window (Trace.STATistic.Func) then selecting Duration Analysis, you get an analysis of the function run-times between function entry and exit including the time spent in called subroutines, e.g. here for the function subst (P:0x114C corresponds to the start address of the subst function):The time interval can be changed using the Zoom buttons.Distance AnalysisBy doing a right mouse click on a function in the numerical statistics window (Trace.STATistic.Func) then selecting Distance Analysis, you can get run-times between two consecutive calls of the selected function,e.g. here for the function subst (P:0x114C corresponds to the start address of the subst function):Variable DisplayThe Trace.ListVar command allows to list recorded variables in the trace. If the command is used without parameters all recorded variables are displayed:Y ou can optionally add one or multiple variables as parameters.Example: display all accesses to the variables plot1 and plot2The Draw button can then be used to plot the displayed variables graphically against time. This corresponds to the following TRACE32 command:Please refer for more information about the Trace.DRAW command to “Application Note forTrace.DRAW” (app_trace_draw.pdf).Trace.ListVar Trace.ListVar %DEFault plot1 plot2Trace.DRAW.Var %DEFault plot1 plot2Track OptionThe /Track options allows to track windows that display the trace results. Y ou just need to add the /Track option after the command that opens a trace window, e.g.Trace.List /TrackThe cursor will then follow the movement in other trace windows, e.g. Trace.Chart.Func. Default is time tracking. If no time information is available, tracking to record number is performed.TRACE32 windows that displays the trace results graphically, e.g. Trace.Chart.Func, additionally accept the /ZoomTrack option. If the tracking is performed with another graphical window, the same zoom factor is used in this case.Trace.Chart.Func /ZoomTrackSearching Trace ResultsThe Find button allows to search for specific information in the trace results.Example 1: find the first call of function func21.Enter “func2” under address / expression2.Select Program under cycle3.Press the Find First button. The next entries to func2 in the trace can then be found using theNext buttonExample 2: Find all write accesses to the variable mstatic1 with the value 0x01.Enter “mstatic1” under address / expression2.Select Write under cycle3.Enter 0x0 under Data4.Press the Find All buttonPlease refer to “Application Note for Trace.Find” (app_trace_find.pdf) for more information about Trace.Find.Trace Save and LoadThe recorded trace can be stored in a file using the command Trace.SAVE , e.g.The saved file can then be loaded in TRACE32 PowerView using the command Trace.LOADThe TRACE32 trace display windows will show in this case a LOAD message in the low left cornerPlease note that TRACE32 additionally allows to export/import the trace results in different formats. Refer to the documentation of the command groups Trace.EXPORT and Trace.IMPORT for more information. Trace.SAVE file.adTrace.LOAD file.ad。
TRACE32调试技巧
TRACE32调试技巧1.掌握TRACE32命令语法。
TRACE32使用一种类似于汇编语言的命令语法，了解和熟悉这些命令可以提高对调试环境的理解和使用。
2.使用TRACE32的源代码浏览和功能。
TRACE32可以直接打开源代码文件，并支持跳转、和定位到指定代码位置。
这个功能非常有用，可以提供更详细的调试信息。
3.使用断点和观察点。
TRACE32支持不同类型的断点和观察点，包括地址断点、条件断点、数据断点等。
合理使用这些断点和观察点可以精确地定位问题和跟踪变量值的变化。
4.使用TRACE32的软件仿真功能。
TRACE32可以模拟目标系统的操作环境，并在主机上进行软件调试。
这种模拟可以提供更快速和安全的调试环境，同时也方便了调试任务的并行执行。
5.学会使用TRACE32的事件记录功能。
TRACE32可以记录目标系统的事件流，并生成详细的事件记录文件。
这些文件可以被用于分析目标系统的运行状态、调试问题和优化性能。
6.添加自定义的TRACE32脚本和命令。
TRACE32支持用户自定义脚本和命令，可以根据实际需要扩展和定制TRACE32的功能。
这可以帮助提高调试效率，并解决特定的调试问题。
7.学习TRACE32的调试工具链集成。
TRACE32可以与其他开发工具集成，包括编译器、汇编器、链接器和性能分析器等。
学习如何使用TRACE32和这些工具一起工作，可以提供更完整的调试解决方案。
8.利用TRACE32的调试数据可视化功能。
TRACE32可以通过图表、图像和统计数据来展示和分析调试数据。
这可以帮助开发人员更直观地理解和评估调试结果。
9.使用TRACE32的远程调试功能。
TRACE32支持通过网络远程调试目标系统，这对于分布式系统开发和调试非常有用。
远程调试可以提供灵活性和便利性，减少不必要的移动和安装工作。
10.参考TRACE32的在线文档和示例。
TRACE32提供了全面的在线文档和示例，可以帮助开发人员更好地理解和使用TRACE32、学习这些文档和示例是提高TRACE32调试技巧的有效途径。
TRACE32调试技巧
TRACE32调试技巧1. 调试步骤l 连接好 TRACE32-ICD 和目标板，注意不要带电插拔 JTAG ，容易损坏 TRACE32 或目标板，然后依次打开 TRACE32-ICD 和目标板的电源。
l 开启调试软件 TRACE32l 设置 CPU 类型，状态等，可以通过命令或菜单，命令如下：sys.resetsys.CPU ARM7TDMI ; 这里设置 CPU 类型sys.up ; 启动调试，如果正常的话，状态为 system.ready; 否则会报错，需要检查 CPU 设置是否正确，TRACE32 和目标板的连接和电源是否正常如果调试正常启动后，就可以下载编译好的文件（可以是 .elf 、 .binary 等文件）到 RAM 或 FLASH 中调试了l 下载编译文件，命令如下：data.load.elf E:/source/test.elf /PATH E:/source这里的/PATH选项是用来指明源代码的路径，在调试时TRACE就可以查找到源代码了。
这里 TRACE会根据 .elf 文件里包含的目标代码起始地址加载到 RAM 的对应地址上，也可以指定加载到 RAM 的地址，但须和编译时的设置一致，否则程序不能正常运行。
注： TRACE 也可以把编译目标文件烧录到 flash 中进行调试，需要使用 flash 烧录相关命令，这里就不详述了。
l 然后就可以设置断点进行调试了，如：break.set 0x0c008000TRACE32 的断点有两种，一种是硬件断点（在 FLASH 中的断点），另一种是软断点（在 RAM 中的断点）；硬件断点需要 CPU 的支持，如 ARM7 最多只支持 2 个硬件断点，如果使用了软断点的话，就只能使用一个硬断点了；而软断点没有限制，可以设置很多个。
注：在TRACE32中，如果要使用硬件断点，需要先设置好FLASH内存映射范围，如下命令：Map.bonchip 0x0000--0xfffff ; 具体范围根据目标板 FLASH 的范围设置l 设置好断点就可以正常调试了。
TRACE32调试培训 深入掌握嵌入式系统调试技能
并行调试是一种有效的多核调试策略，通过同时监控多个线程的执行情况，可以更快地定 位问题，提高调试效率。
3 同步和异步调试方法
同步和异步是两种常用的多核调试方法，同步方法需要开发者手动控制线程的执行顺序， 而异步方法则可以让线程自主运行，根据实际需求选择合适的调试方法，可以提高调试的 效率和准确性。
通过实际的数据监控和变量 查看操作，展示TRACE32如 何帮助开发者快速定位问题 ，提高调试效率。
03 连接操作步骤详解
硬件连接要求
连接硬件准备
在进行TRACE32调试培训前 ，请确保所有需要的硬件设 备齐全并处于良好的工作状 态。
电脑系统要求
电脑应具备足够的运行内存 和硬盘空间，推荐使用 Windows系统，并安装有支 持TRACE32的软件开发工具 包。
。
参加TRACE32调试培训后，参训者将能够快速定
位和解决嵌入式系统中的问题，提高故障排除的
速度和准确性。同时，他们还将具备独立完成项
目调试的能力，为个人职业发展和团队工作提供
有力支持。
TRACE32简介
TRACE32的发展历 程
TRACE32是一款由德国Keil 公司开发的，具有强大功能 和广泛应用的微处理器开发 工具。它自1985年问世以来 ，不断更新升级，以满足日 益增长的嵌入式系统开发需 求。
TRACE32是一种强大的嵌入 式系统调试工具，它支持多 种处理器和操作系统，可以 实时追踪程序的运行状态， 帮助我们快速定位问题。
在TRACE32中，我们可以通 过设置断点、查看寄存器值 、单步执行等方式来调试程 序，这些基本操作是每个调 试工程师必须掌握的技能。
除了基本操作，TRACE32还 有许多高级功能，如内存分 析、性能分析等，这些功能 可以帮助我们更深入地理解 程序的运行机制，提高我们 的调试效率。
TRACE32使用
• 6.4）查看CPU寄存器：
Thank You！
由于th100使用的那根小线fpc很容易受到干扰如果出现连接不成功的情况建议使用防干扰的fpc线或更换testboard试试不用怀疑跳线问题
TRACE32 使用
刘小春 2009-05-26
1，TRACE32作用：
在线实时仿真 • 设置实时地址和数据断点、单步执行、对 ARM内核完全存取和控制。 • 跟踪调试程序异常原因。
2，硬件连接
• • TH100连接Trace32及开发板跳线方法： 1.1）下图为TH100，TRACE32和开发板 连接方法：
TRACE32，手机，开发板连接图：
• 1.2）下图适用于TH100接开发板跳线方法。 • J14和J13两个跳线帽放到左边 ，J7在右边
• •
•
1.3）TH100连接Trace32注意事项： 图中的开发板的版本是 “TG100_TESTBOARD_V2.10_PCB(07 0619)”，请尽量使用此版本的Test Board。 由于TH100使用的那根小线(FPC)很容易 受到干扰，如果出现连接不成功的情况， 建议使用防干扰的FPC线或更换Test Board试试，不用怀疑跳线问题。
TRACE32运行截图：
7，TRACE32调试
• • • • • • 6.1）断点 最多可设置两个硬件断点。 可设置条件断点。 6.2）单步跟踪，跳转 6.3）查看堆栈，变量和内存 当TRACE停在断点上，或者处于break状态下执 行view—stackframe查看堆栈中函数调用关系。 • 查看变量和读取制定内存接好TRACE32，手 机和开发板。 • 5.2）运行TRACE32程序，选择脚本 “file—open batch file…— js_it_debug.cmm”。 • 5.3）长按手机开机键，执行 js_it_debug.cmm脚本开机，如下图所示：
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
Confidential Documents
30
Trace32 基础配置及调试
软件安装 硬件连接 T32Start配置 基本的连接步骤 基本调试方法
2012/3/15
Lauterbach Academy
Confidential Documents
31
新建一个配置工程
• 选中Configuration Tree，单击右键，将鼠标移动到Add上选 中其下级子菜单Configuration,单击鼠标左键
9
输入license key
2012/3/15
Lauterbach Academy
Confidential Documents
10
选择主机OS
2012/3/15
Lauterbach Academy
Confidential Documents
11
选择目标平台CPU类型
2012/3/15
Lauterbach Academy
27
硬件连接
PowerDebug USB II: • 304 DMIPS • 200 MHz • USB 2.0 通 信接口
2012/3/15
Lauterbach Academy
Confidential Documents
28
各类转换接口
Adaption for Arm Adaption for CEVA-X Preprocessor Adaption for ARM ETM Preprocessor MIPI-60 ARM Converter ARM-20 to/from ARM-14 Debugger Adaption for Intel® Atom™/x86 JTAG Connector for PowerPC440
Confidential Documents
35
增加要调式的目标核
2012/3/15
Lauterbach Academy
Confidential Documents
36
选择与HOST的连接方式
2012/3/15
Lauterbach Academy
Confidential Documents
37
选择目标板的CPU类型
39
启动Trace32
选中主工程，然后我们就可以通过点击Start来启动我们 的Trace32。
2012/3/15
Lauterbach Academy
Confidential Documents
40
Trace32 基础配置及调试
软件安装 硬件连接 T32Start配置 基本的连接步骤
2012/3/15
Lauterbach Academy
Confidential Documents
38
路径修改
将WorkingPath 和SystemPath改成我们实际的工作路径及我 们实际的系统路路径
2012/3/15
Lauterbach Academy
Confidential Documents
更多内容访问： • /ad.html
2012/3/15 Lauterbach Academy Confidential Documents 29
一个最简的调试环境
我们以建立一个arm平台的为例，看如何配置一个 调试的环境
2012/3/15
Lauterbach Academy
Next的模式会在当前代码的下一条代 码打一个临时断点，当程序执行以后 会一直运行直到碰到这个临时断点， 它可以帮助我们直接跨过一个循环体。
2012/3/15 Lauterbach Academy Confidential Documents 54
Return
点击return，最 后停在函数出 口处639
2012/3/15
Lauterbach Academy
Confidential Documents
45
设置CPU参数
选择我们的目标 CPU的一些参数， 在我们连接我们 的调试工具与目 标平台之前。
2012/3/15
Lauterbach Academy
Confidential Documents
46
25
安装完成
2012/3/15
Lauterbach Academy
Confidential Documents
26
Trace32 基础配置及调试
软件安装 硬件连接 T32Start配置 基本的连接步骤 基本调试方法
2012/3/15
Lauterbach Academy
Confidential Documents
2012/3/15
Lauterbach Academy
Confidential Documents
48
Trace32 基础配置及调试
软件安装 硬件连接 T32Start配置 基本的连接步骤 基本调试方法
2012/3/15
Lauterbach Academy
Confidential Documents
3
欢迎界面
2012/3/15
Lauterbach Academy
Confidential Documents
4
软件授权
2012/3/15
Lauterbach Academy
Confidential Documents
5
安装路径选择
2012/3/15
Lauterbach Academy
Confidential Documents
2012/3/15
Lauterbach Academy
Confidential Documents
56
Go
执行应用程序，直到碰到用户设置的 断点才停下来。
2012/3/15
Lauterbach Academy
Confidential Documents
57
Q&A?
• 您可以访问以下网站得到更多，更新的信息 • • FAQ: /faq.html
6
安装类型选择
2012/3/15
Lauterbach Academy
Confidential Documents
7
工具类型选择
2012/3/15
Lauterbach Academy
Confidential Documents
8
选择平台接口
2012/3/15
Lauterbach Academy
Confidential Documents
2012/3/15
Lauterbach Academy
Confidential Documents
23
程序安装包类型
2012/3/15
Lauterbach Academy
Confidential Documents
24
注册方式
2012/3/15
Lauterbach Academy
Confidential Documents
17
临时文件夹设置
2012/3/15
Lauterbach Academy
Confidential Documents
18
调试环境字体大小
2012/3/15
Lauterbach Academy
Confidential Documents
19
显示语言的选择
2012/3/15
Lauterbach Academy
Return 会在一个函数的最后一行设置 一个临时断点，当在函数体内点击 Return以后，程序会一直运行直到停 在设置的临时断点的位置。
2012/3/15
Lauterbach Academy
Confidential Documents
55
Up
Up会从当前函数执行结束，跳到应用 它的函数的下条指令
2012/3/15
Lauterbach Academy
Confidential Documents
32
配置一个新的工程名
修改默认工程名 Configuration 为Omap4430panda
2012/3/15
Lauterbach Academy
Confidential Documents
33
添加Podbus 设备链路
2012/3/15
Lauterbach Academy
Confidential Documents
52
Over
单步运行。 在碰到子函数的时候会进入子函数中 的第一条代码。
பைடு நூலகம்2012/3/15
Lauterbach Academy
Confidential Documents
53
Next
在代码执行到632 时点击step 程序会跳出循环 到634执行
参数设置帮助
对于这些参数的设置我们 可以参看Help 下的ICD Target Manual.我们就可以 看到我们目标平台的相对 应的文档。
2012/3/15
Lauterbach Academy
Confidential Documents
47
建立与CPU的连接
点击Up我们就可以让 我们的工具与我们的 目标板建立连接了。 它将完成以下内容： 1. 重启目标CPU 2. 初始化连接 3. CPU指向Reset Vector
Trace32 基础配置及调试
Able.zhou
软件安装 硬件连接 T32Start配置 基本的连接步骤 基本调试方法