ALTERA公司CPLD_和_FPGA_选型列表
Altera_FPGA_配置模式
FPGA配置模式时间：2011-09-12 23:15:16 来源：作者：FPGA有多种配置模式：并行主模式为一片FPGA加一片EPROM的方式;主从模式可以支持一片PROM编程多片FPGA;串行模式可以采用串行PROM编程FPGA;外设模式可以将FPGA作为微处理器的外设，由微处理器对其编程。
如何实现快速的时序收敛、降低功耗和成本、优化时钟管理并降低FPGA与PCB并行设计的复杂性等问题，一直是采用FPGA的系统设计工程师需要考虑的关键问题。
如今，随着FPGA向更高密度、更大容量、更低功耗和集成更多IP的方向发展，系统设计工程师在从这些优异性能获益的同时，不得不面对由于FPGA前所未有的性能和能力水平而带来的新的设计挑战。
在很多项目设计中采用Altera 公司基于SRAM架构Cyclone系列器件。
Cyclone器件与其他FPGA器件一样是基于门阵列方式为用户提供可编程资源的，其内部逻辑结构的形成是由配置数据决定的。
这些配置数据可通过多种模式加载到FPGA内部的SRAM中，由于SRAM的易失性，每次上电时，都必须对FPGA进行重新配置。
1 Cyclone FPGA 配置模式Cyclone系列FPGA器件配置方案主要有三种，包括使用低成本配置芯片的主动串行(AS)配置、被动串行(PS)配置以及基于JTAG配置，实际应用时可以使用其中的一种方案配置Cyclone系列FPGA器件，来实现用户编程所要实现的功能。
Cyclone系列FPGA器件是用SRAM单元配置数据的。
由于SRAM掉电后容易丢失数据，配置数据必须即时地下载到上电的Cyclone器件中。
不同的配置模式可采用不同的专用配置芯片或数据源这三种配置模式是由Cyclone器件的模式选择引脚MSEL1和MSEL0的高低电平来决定的，如果你的实际应用只要求单一的配置模式，可以把模式选择引脚连接到VCC端或接地端在切换引脚的过程中，器件的运行状态不会被影响。
第三章 Altera的 CPLDFPGA
Altera的CPLD/FPGA器件系列 Altera的CPLD/FPGA器件 Altera的CPLD/FPGA的配臵
Altera是著名的PLD器件生产厂 商，Altera的PLD器件具有高性能、 高集成度和高性价比的优点，并且 Altera提供了全面的开发工具和丰 富的IP核、宏功能库等，因此 Altera的产品得到了广泛应用。
… 1 6个扩展乘积项
共享扩展项
去P IA
MAX7000器件的宏单元可以单独地配臵成 时序逻辑或组合逻辑工作方式。每个宏单元 由逻辑阵列、乘积项选择矩阵和可编程寄存 器等三个功能块组成。 MAX7000器件的宏单元中的逻辑阵列用来 实现组合逻辑，它为每个宏单元提供五个乘 积项。乘积项选择矩阵把这些乘积项分配到 “或”门和“异或”门作为基本逻辑输入,以 实现组合逻辑功能；或者把这些乘积项作为 宏单元中寄存器的辅助输入来实现清除、预 臵、时钟和时钟使能等控制功能。
APEX系列
APEX20K系列器件是第一个具有多核结构，支持可编程单芯片系统（ SOPC）的PLD器件系列 。这种多核结构集成了乘积项、查找表和嵌入式存储器块（ EAB）。乘积项结构适用于实现复 杂组合逻辑；使用查找表逻辑能实现增强型寄存器功能；查找表结构能有效实现数据通道、增 强型寄存器、数学运算及数字信号处理器等设计；嵌入式系统块（ ESB）能实现多种存储功能 ，包括FIFO、双端口RAM及内容可寻址存储器（CAM）。 APEX20K系列器件的配臵通常是在系统上电时，通过存储一个 Altera串行PROM中的配臵数据 或者由系统控制器提供的配臵数据来完成。Altera提供ISP串行数据配臵芯片，如EPC1、EPC2 、EPC16；APEX20K具有优化的接口，允许微处理器串行或并行，同步或异步对其进行配臵，微 处理器将APEX20K作为存储器对待，重新配臵也很容易。APEX20K器件被配臵后，可以通过重新 复位器件、加载新数据的方法实现在线可配臵。 APEX20KE器件属于超级APEX20K器件，它支持先进的I/O标准和内容可寻址存储器（CAM）， 并具有更多的全局时钟数、增强的“时钟锁定”时钟电路等附加特性。APEX20KE在APEX20K器 件基础上扩展到150万门。 APEXII器件结构与APEX20K器件结构一样，它集成了高速差分I/O，支持使用True-LVDS接口 。在True-LVDS接口中的并串转换、串并转换和CDS电路支持LVDS、LVPECL、HyperTransport和 PCML I/O标准。在一般用户I/O的Flexible-LVDS引脚提供附加的差分支持，增加了整个器件的 带宽，这种电路再加上增强型IOE及对大量I/O标准的支持，使得APEXII器件能满足高速接口的 需要。APEXII其间还具有其他的高性能特征，如双向双端口RAM、CAM、普通的PLL和大量的全 局时钟。
Lattice Semiconductor 产品选择指南：FPGA、CPLD、混合信号等 - 201
PRODUCT SELECTOR GUIDE2012FPGA • CPLD • MIXED SIGNAL • INTELLECTUAL PROPERTY • DEVELOPMENT KITS • DESIGN TOOLSCONTENTS■A dvanced Packaging (4)■F PGA Products (6)■CPLD Products (8)■Power Management and Clock Management Products (8)■Intellectual Property and Reference Designs (10)■Development Kits and Evaluation Boards (14)■P rogramming Hardware (18)■FPGA and CPLD Design Software (19)■PAC-Designer® Design Software (19)Page 2Affordable InnovationLattice Semiconductor is committed to delivering value through innovative low cost, low power solutions.We’re innovating every day to drive down costs and deliver greater value. From cost sensitive consumerelectronics to leading edge communications equipment, designers are using Lattice products in a growingnumber of applications. We’ve shipped over a billion devices to customers worldwide and we understandthat we must deliver cost effective solutions and excellent service in order to succeed.Low Density and Ultra-Low Density FPGAsWe are committed to providing design engineers with the low cost and low power solutions they needto implement their designs quickly, easily and affordably. Lattice FPGA solutions offer unique features,low power, and excellent value for FPGA designs. Our low density LatticeECP3™ family is comprisedof the lowest power, SERDES-enabled FPGAs in the market today, and is ideally suited for deploymentin high volume cost- and power-sensitive wireless and wireline infrastructure, video camera and displayapplications. Our ultra-low density, low cost and low power iCE40™ and MachXO2™ FPGA familiesare ideal for applications ranging from glue logic and bridging to instant-on system control and flexibleI/O expansion. From mobile handsets to leading-edge telecommunications infrastructure, Lattice offerssolutions that minimize cost and power while maximizing value.Power Management and Clock ManagementOur Platform Manager™, Power Manager II and ispClock™ mixed signal product families feature acombination of programmable logic and programmable analog circuitry that allows system designersto reduce system cost and design time. These innovative products provide a fast and easy solution forintegrating a wide range of power and clock management functions within a single integrated circuit. Theseproducts can replace numerous discrete components, reducing cost and conserving board space, whileproviding users with additional design flexibility and time-to-market benefits.Software and Intellectual PropertyOur Lattice Diamond® development tool suite, iCEcube2™ design software, PAC-Designer software, and IPcore program allow design engineers to easily customize our devices for their unique system requirements.Lattice Diamond software tools enable users to synthesize a design, perform analysis, debug, anddownload a logic configuration to our FPGA devices, while iCEcube2 software supports our iCE40 family ofFGPAs. PAC-Designer software is used in the design of our mixed signal products.Our IP core program, LatticeCORE™, provides pre-tested, reusable functions, allowing designers to focuson their unique system architectures. These IP cores provide industry-standard functions including PCIExpress, DDR, Ethernet, CPRI, Serial RapidIO 2.1, SPI4, and embedded microprocessors. In addition, anumber of independent IP providers have teamed with Lattice to offer additional high quality, reusable IPcores. Partners are selected for their industry leadership, high development standards, and commitment tocustomer support.Page 3Page 4Organic Flip Chip BGAFine Pitch BGA1704-BallOrganic fcBGA 42.5 x 42.5 mm 3.25 mm height 1.00 mm pitch1020-BallOrganic fcBGA Revision 233 x 33 mm 3.25 mm height 1.00 mm pitch1152-Ball fpBGA 1156-Ball fpBGA 35 x 35 mm 2.60 mm height 1.00 mm pitc h900-Ball fpBGA 31 x 31 mm 2.60 mm height 1.00 mm pitch672-Ball fpBGA 27 x 27 mm 2.60 mm height 1.00 mm pitch484-Ball fpBGA 23 x 23 mm 2.60 mm height 1.00 mm pitch324-Ball ftBGA 19 x 19 mm 1.70 mm height 1.00 mm pitch256-Ball ftBGA 17 x 17 mmOption 1: 1.55 mm height Option 2: 2.10 mm height Option 3: 1.70 mm height 1.00 mm pitch 256-Ball caBGA 14 x 14 mm 1.70 mm height 0.80 mm pitch332-Ball caBGA 17 x 17 mm 2.00 mm height 0.80 mm pitch208-Ball ftBGA 17 x 17 mm 1.55 mm height 1.00 mm pitch256-Ball fpBGA 17 x 17 mm 2.10 mm height1.00 mm pitchFine Pitch BGAChip Array BGANote: Packages shown actual size. Height specification is max.Page 5208-Pin PQFP 28 x 28 mm (body)4.10 mm height 0.50 mm pitch176-Pin TQFP 24 x 24 mm (body)1.60 mm height 0.50 mm pitch144-Pin TQFP 20 x 20 mm (body)1.60 mm height 0.50 mm pitch100-Pin VQFP 14 x 14 mm (body)1.2 mm height 0.50 mm pitch100-Pin TQFP 128-Pin TQFP 14 x 14 mm (body)1.6 mm height0.50 mm pitch (100 TQFP)0.40 mm pitch (128 TQFP )44-Pin TQFP10 x 10 mm (body)1.20 mm height 1.60 mm height 0.80 mm pitch 48-Pin TQFP 7 x 7 mm (body)1.20 mm height 1.60 mm height0.50 mm pitchVQFP/TQFP/PQFP64-Pin QFNS 9 x 9 mm1.00 mm height 0.50 mm pitch 100-Ball csBGA 8 x 8 mm1.35 mm height 0.50 mm pitch132-Ball csBG A 8 x 8 mmOption 1: 1.35 mm heightOption 2: 1.00 mm height (iCE40)0.50 mm pitch 184-Ball csBG A 8 x 8 mm1.35 mm height 0.50 mm pitch284-Ball csBGA 12 x 12 mm 1.00 mm height 0.50 mm pitch 328-Ball csBGA 10 x 10 mm 1.50 mm height 0.50 mm pitch 132-Ball ucBGA 6 x 6 mm1.00 mm height 0.40 mm pitch 25-Ball WLCSP2.5 x 2.5 mm 0.62 mm height 0.40 mm pitch84-Pin QFNS 7 x 7 mm1.00 mm height 0.50 mm pitch 48-Pin QFNS 7 x 7 mm1.00 mm height 0.50 mm pitch144-Ball csBGA 7 x 7 mm1.10 mm height 0.50 mm pitch 64-Ball ucBGA 4 x 4 mm1.00 mm height 0.40 mm pitch 32-Pin QFNS 5 x 5 mm1.00 mm height 0.50 mm pitch 32-Pin QFN 5 x 5 mm0.60 mm height 0.50 mm pitch 56-Ball csBGA 6 x 6 mm1.35 mm height 0.50 mm pitch 81-Ball csBGA 5 x 5 mm1.00 mm height 0.50 mm pitch 225-Ball ucBGA 7 x 7 mm1.00 mm height 0.40 mm pitch 24-Pin QFNS 4 x 4 mm1.00 mm height 0.50 mm pitch64-Ball csBGA 5 x 5 mm1.10 mm height 0.50 mm pitch121-Ball csBGA 6 x 6 mm1.00 mm height 0.50 mm pitch 121-Ball ucBGA 5 x 5 mm1.00 mm height 0.40 mm pitch 81-Ball ucBGA 4 x 4 mm1.00 mm height 0.40 mm pitch 49-Ball ucBGA 3 x 3 mm1.00 mm height 0.40 mm pitch 36-Ball ucBGA2.5 x 2.5 mm 1.00 mm height0.40 mm pitchQFNS / QFNChip Scale BGAUltra Chip Scale BGAWafer Level Chip ScaleNote: Packages shown actual size. Height specification is max.NEWiCE40™Page 6Page 71) Pb-free only.ispClock ProductsPage 8Platform Manager and Power Manager II Device Selector Guide* ispPAC-POWR1014A OnlyPage 9LatticeCORE IP CoresThe following is a partial listing of LatticeCORE IP, for a complete listing of IP cores from Lattice and its 3rd party partners, please go to /ip.1. LatticeSCM™ MACO®-based IP cores are not included in this table.Page 10IP SuitesLattice IP Suites provide many of the functions required to develop a total solution for common FPGA applications. In addition, multipleLattice FPGA families are supported with each IP Suite, so designers can develop solutions across multiple Lattice families, taking advantage of the best features of each. The following table summarizes which IP cores are included in each IP Suite, and which FPGA families are supported.Page 11Page 12Page 13Page 14Features- Power connections and power sources - ispVM™ programming support- On-board and external reference clock sources• Available on Windows and Linux platforms • Software and IP with a 60-day license (Windows or Linux)• Variety of demos • USB download cable• Comprehensive Image Processing IP Library • On-board Broadcom ® Broadreach™ PHY Enables IP over Coax• On-board FTDI Chip provides easy programming via low cost USB cable- Gigabit Ethernet MAC Demo using Mico32- DDR3 Memory Controller Demo• Available on Windows and Linux platforms • USB A to USB B (Mini) Cable for FPGA Programming via a PC• 12V AC Power Adapter and International Plug Adapters•QuickSTART GuideFeaturesFeaturesFeaturesLatticeECP3 Versa Development KitHDR-60 Video Camera Development KitLatticeECP3 PCI Express Development KitLatticeXP2 Brevia2 Development Kit• LatticeECP3 PCI Express x1/x4 Solutions Board- PCI Express x1 and x4 edge connector interfaces- On-board Boot Flash- Both Serial SPI Flash and Parallel Flash via MachXO programming bridge - Shows interoperation with a highperformance DDR2 memory component - Switches, LEDs, displays for demo purposes- Input connection for lab-power supply• FPGA-based Image Signal Processing• Fully Production-Ready HDR Camera Design • 1080p Capable @ 60 frames per second• Supports up to 16 Megapixel Sensors • Supports up to two sensors simultaneously • Full 60fps in streaming mode needs no external frame buffer• Fast Auto Exposure Instantly Adjust to Changing Light• Greater than 120 dB High Dynamic Range (HDR) Performance• Direct HDMI/DVI output from FPGA • Extremely Low-Latency• The LatticeECP3 Versa Evaluation Board:- PCI Express 1.1 x1 Edge Connector Interface- Two Gigabit Ethernet Ports (RJ45)- 4 SMA Connectors for SERDES Access - USB Mini for FPGA Programming- LatticeECP3 FPGA: LFE3-35EA-FF484- 64 Mbit Serial Flash memory - 1 Gbit DDR3 Memory- 14-segment alpha-numeric display - Switches and LEDs for demos - SERDES Eye Quality Demo - 4 PCI Express Demos• LatticeXP2 FPGA: LFXP2-5E-6TN144C • 2 Mbit SPI Flash Memory • 1 Mbit SRAM• Programmed via included mini-USB Cable • 2x20 and 2x5 Expansion Headers• Push buttons for General Purpose I/O and Reset• 4-bit DIP Switch for user-defined inputs • 8 Status LEDs for user-defined outputsDevelop PCIe-based platforms using a low-cost, low-power SERDES-basedFPGA with proprietary and Lattice provided designs.A fully production ready High Dynamic Range (HDR) camera, designed to fit into commercially available camera housings. Supports full 1080p resolution at 60 frames per second in streaming mode through the FPGA, without the need for an external frame buffer.Industry’s lowest cost platform for design-ing PCI Express and Gigabit Ethernet based systems. The kit includes free demos and reference designs.Easy-to-use, low-cost platform for evaluat-ing and designing with LatticeXP2 FPGAs.Page 15FeaturesFeaturesiCEblink40 Evaluation KitMachXO2 Pico Development KitMachXO2 Control Development Kit• Two versions:- High Performance: iCE40HX1K-VQ100 - Low Power: iCE40LP1K-QN84• Powered by USB input• 1Mbit SPI PROM (enough for two iCE40HX1K images using WarmBoot)• Four capacitive-touch buttons (requires FPGA logic)• Four user LEDs• Dual PMOD header compatible with Digilent PMOD boards (6x2 header)• MachXO2 LCMXO2-1200ZE• 4-character 16-segment LCD display • 4 capacitive touch sense buttons • 1 Mbit SPI Flash• I 2C temperature sensor• Current and voltage sensor circuits • Expansion header for JTAG, I 2C• Standard USB cable for device programming and I 2C communication• RS-232/USB & JTAG/USB interface• RoHS-compliant packaging and process• MachXO2 LCMXO2-4000HC• Power Manager II ispPAC-POWR1014A • 128Mbit LPDDR memory, 4Mbit SPI Flash • Current and voltage sensor circuits • SD memory card socket • Microphone• Audio Amplifier and Delta-Sigma ADC• Up to two DVI sources and one DVI output.• Up to two Display Inputs (7:1 LVDS) and one Display Output (7:1 LVDS)• Audio output channel• Expansion header for JTAG, SPI, I 2C and PLD I/Os.• 3.33 MHz oscillator (can be modified to support 33.33 MHz or 333 kHz)• 1.2V and 3.3V power supplies• All iCE40HX1K I/O available on headers or 0.1” through-holes• Watch battery• QuickSTART Guide• LEDs & switches• Standard USB cable for device programming • RS-232/USB & JTAG/USB interface• RoHS-compliant packaging and process • AC adapter (international plugs)• QuickSTART Guide31, 2012. Standard list price: $39.MachXO Control Development Kit FeaturesMachXO Pico Dev. Kit & MachXO Control Dev. Kit• Preloaded Control SoC Demo • MachXO LCMXO2280• Power Manager II ispPAC-POWR1014A• 2Mbit SPI Flash & 1Mbit SRAM • I 2C temperature sensor • Current and voltage sensor circuits • On-board fan • Interface to 16 x 2 LCD panel*• SD memory and Compact Flash memory card sockets*• Audio output channel• Expansion header for SPI & I 2C • LEDs & switches• Standard USB cable for device programming and I 2C communication • RS-232/USB & JTAG/USB interface • 3” x 1” prototyping area • RoHS-compliant packaging and process * LCD panel and SD/Compact Flash memory not included in the development kit MachXO Mini Development Kit Features• MachXO PLD: LCMXO2280C-4TN144C• 2 Mbit SPI Flash memory • 1 Mbit SRAM• I 2C temperature sensor • USB mini jack sockets for power, JTAG programming, and RS-232 debugging • 2X16 header for off-board expansion provides access to top and right side MachXO banks• Push-buttons for sleep mode and reset• 4-bit DIP switch to user-defined inputs • ADC/DAC circuit • Sleep circuit• 8 LEDs for user-defined outputs• RoHS-compliant packaging and process• Two USB connector cables • QuickSTART GuidePage 16FeaturesFeaturesFeaturesPower Manager II Hercules Development KitProcessorPM Development KitPlatform Manager Development Kit• The Standard Edition Hercules DevelopmentKit features the following:- Preloaded Board Digital ManagementDemo- Hercules Standard Edition eval board- Power Manager II ispPAC-POWR1220AT8 and MachXOLCMXO2280 PLD• The Advanced Edition Hercules DevelopmentKit features the following:- Preloaded Board Digital ManagementDemo- Hercules Advanced Edition evaluationboard with CompactPCI headers- Power Manager II ispPAC-POWR1220AT8 and MachXOLCMXO2280 PLD- Backplane accessory evaluation boardand power supply for live hot-swap• AC adapter (international plugs)• USB Connector Cable• RoHS-compliant packaging and process• Pre-configured Processor Support Demo• ProcessorPM-POWR605• Power Manager II POWR6AT6• 3.3V, 2.5V, and 1.8V supply rails• LEDs• Slide potentiometer• 2x14 expansion header• USB mini jack socket (program/power)• 2 Push-Buttons• Preloaded Power Management Demo• LPTM10-12107, Platform Manager, 208-ballftBGA package• 35mm slide pots to emulate supply railvariations• Pads for user I/O, LED, and switches• JTAG and I2C interface headers• USB Cable• 4-Bit DIP Switch• JTAG and I2C Header Landings• RoHS-compliant packaging and process• USB connector cable• QuickSTART Guide• AC adapter with international plugs• Programmable with ispVM System software• QuickSTART GuideVersatile, ready to use hardware platformsfor evaluating and designing with PowerManager II devices. A Standard and Ad-vanced Edition of each kit is available.Versatile, ready-to-use hardware platformfor evaluating and designing with Proces-sorPM power management devices.A versatile, ready-to-use hardware plat-form for evaluating and designing withPlatform Manager devices.Features:Breakout Board Evaluation Kits•Preprogrammed with hardware test programLCMXO2-1200ZE-1TG144C PLD (MachXO2Breakout Board), LCMXO2280C-FTN256CPLD (MachXO2280 Breakout Board),POWR1014A-02TN48I (POWR1014ABreakout Board), or LC4256ZE-TN144C CPLD(ispMACH 4256ZE Breakout Board)• LEDs•Expansion Header LandingsBreakout Board Evaluation Kits for selectMachXO2, MachXO, ispMACH 4000ZE,Power Manager II devices offer convenienthardware evaluations by providing easyhand-access to PLD I/Os.•Prototyping Area•USB Mini Jack Socket (Program/Power)•JTAG Header Landing•RoHS-compliant packaging and process•USB connector cableFeaturesispMACH 4000ZE Pico Development Kit• Pre-programmed Pico Power Demo• ispMACH 4000ZE device(LC4256ZE-5MN144C)• Power Manager II device(ispPAC-POWR6AT6-01SN32I)• LCD panel• USB mini jack socket for power, JTAGprogramming, and I2C interface• 2X15 header landing for off-board expansionprovides access to LC4256ZE GPIOs,POWR6AT6 VMON inputs, I2C, and JTAG chain• Push-button for global reset• 4-bit DIP switch to user-defined inputs• 3.3V and 2.5V supply rails• Current and voltage sensor circuits• Battery or USB power source• RoHS-compliant packaging and process• Marked for CE, China RoHS Environmental-Friendly Use Period (EFUP) and WasteElectrical and Electronic Equipment (WEEE)Directives• One USB connector cable• QuickSTART GuideBattery-powered, low-cost platform toaccelerate the evaluation of ispMACH4000ZE CPLDs.Page 17Programming HardwarePage 18PAC-Designer — Mixed-Signal Design SoftwarePage 19Technical SupportUSA & Canada: 1-800-LATTICE (528-8423)For other locations: +1-503-268-8001PLDTechnicalandSoftware:***************************MixedSignal:***********************Additionally, customers can receive technical support for Lattice’s Programmable Logic Products from our Asia based applications group, by contacting Lattice Asia applications during the hours of 8:30 a.m. to 5:30 p.m. Beijing Time (CST) +0800 UTC (Chinese and English language only).Asia: +86-21-52989090********************************Corporate HeadquartersLattice Semiconductor Corporation 5555 Northeast Moore CourtHillsboro, Oregon 97124-6421 USA Telephone: +1-503-268-8000Facsimile: +1-503-268-8347Web: Software LicensingEmail:************************Web: /licensing/index.cfmCopyright © 2012 Lattice Semiconductor Corporation. All brand names or product names are trademarks or registered trademarks of their respective holders. Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), Lattice Diamond, LSC, E 2CMOS, FlashBAK, flexiFLASH, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, iCE40, iCEblink, iCEcube2, IPexpress, ISP , ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2, ispGENERATOR, ispJTAG, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP , ispXPGA, ispXPLD, LatticeCORE, LatticeECP3, LatticeECP2, LatticeECP2M, LatticeECP , LatticeECP-DSP , LatticeMico, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP , LatticeXP2, MACH, MachXO, MachXO2, MACO, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, Platform Manager, ProcessorPM, PURESPEED, Reveal, Silicon Forest, Speedlocked, Speed Locking, sysCLOCK, sysCONFIG, sysDSP , sysHSI, sysI/O, sysMEM, The Simple Machine for Complex Design, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP is a service mark of Lattice Semiconductor Corporation.October 2012 • Order #: I0211K。
FPGA选型手册
Version 13.1Altera 产品目录 • 2013 • 1Altera 提供最全面的可编程逻辑器件系列产品—FPGA 、SoC和CPLD结合软件工具，知识产权(IP)、嵌入式处理器、客户支持和技术培训。
Altera 产品的领导地位、卓越的价值以及优质的服务给您带来显著的优势。
将带给您奇思妙想，帮助您更快更好的实现性价比更高的设计。
FPGAAltera FPGA 帮助您获得最佳的灵活性进行创新、差异化，并在市场上保持领先地位。
我们提供三类FPGA ，从业界最高密度和高性能到最具成本效益，以满足市场要求。
概述SoCSoC 将两个分立的器件合并成一个，从而降低了系统功耗和成本，减小电路板面积，同时提高了性能。
SoC 使用宽带互联链路，在FPGA 架构中集成了基于ARM 的硬核处理器系统(HPS)，包括双核ARM®处理器、外设和存储器控制器。
电源采用Enpirion 电源管理产品启动您的FPGA 。
该系列集成产品提供业界领先的小外形封装、低噪声性能和高效率的组合，从而更快地完成设计。
CPLD对于胶合逻辑以及任何控制功能，我们的非易失MAX 系列提供市场上成本最低的CPLD—单芯片解决方案，非常适合接口桥接、电平转换、I/O 扩展和模拟I/O 管理。
高效能设计软件、嵌入式处理、知识产权(IP )、开发套件和培训和Altera 一起，您将获得全面的设计环境以及多种设计工具—所有的工作顺理成章，迅速完成设计。
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最高带宽，最高密度的FPGA 集成收发器种类在片上设计整个系统均衡成本、功耗和性能的FPGA 集成收发器和处理器种类综合设计保护最低系统成本和功耗的FPGA 集成收发器和处理器种类最快的面市时间2 Altera 产品目录 • 2013 •2 1 所有数据在印刷时是正确的，可能会随时更改，恕不另行通知。
ALTERA新一代CPLD：MAX V 介绍
新代MAX V C t h FAE K i H ALTERA 新一代CPLD ：MAX V 介绍--Cytech FAE ：Kevin Han --2011.08.09ALTERA的完整解决方案高密度，高性能FPGA低成本，低功耗CPLD低风险，低成本ASIC低成本，低功耗FPGA成本和功耗优化FPGAMIPS Technology 开发软件丰富的IP开发套件嵌入式软核处理器MIPS Technology©2011 Cytech Corporation -PublicMAX V系列器件预览MAX VMAX V 系列–封装和IO管脚器件型号密度M644.5x4.5E647x7M685x5T10014x14M1006x6T14421x21F25617x17F32419x19Logic Elements换算成Macrocells5M40Z 403230545M80Z 8064305452795M160Z 160128545279795M240Z 2401925279791145M570Z 57044074741141595M1270Z 1,2709801142112715M2210Z2,2101,700203271M = 0.5-mm pitch MBGA package E = 0.5-mm pitch EQFP package T = 0.5-mm pitch TQFP package F = 1.0-mm pitch FBGA package 注=-40°C to +125°C)注：(a)、MAX V 系列（商业级和工业级）已经全部量产（包括所有系列和所有封装）(b)、有关ALTERA 器件的详细封装信息可以参考链接文档：/literature/ds/dspkg.pdf\(c)、上述表格中字母M,E,T,F 后的数字表示管脚数，对应的列表中的数值表示可用IO 数©2011 Cytech Corporation -Public 支持商业级，工业级，扩展级(T j 40C to +125C)MAX V系列器件的软件和IP支持Quartus II software−QuartusII11.0已经支持整个MAX V系列CPLD−支持的操作系统：Windows 7/XP/VISTAQ−QuartusII分为订购版和WEB版MegaCore IP−LVDS TX核−Digital PLL*(在后续软件版本中会支持)−Parallel flash loader (PFL)In system sources and probes(在线调试工具)−In-system sources and probes(−USER FLASH MEM接口(UFM接口）−FIFO/RAM免费的Quartus II Web版支持所有的MAX系列CPLD QuartusII的官网下载链接：https:///download/dnl-index.jsp©2011 Cytech Corporation -PublicMAX V系列器件的特性注：(1)t PD1表示最大的Pin-to-Pin延迟，这里的Pin-to-Pin是在最远的管脚之间，中间还经过了靠近输出管脚的单个LUT和LAB的组合逻辑(2)f CNT表示最高的全局时钟频率，这个最高的时钟频率主要是受IO管脚的限制，实际内部的时钟频率高于上述值©2011 Cytech Corporation -PublicMAX V的管脚和IO©2011 Cytech Corporation -PublicMAX V的订购码©2011 Cytech Corporation -PublicMAX V CPLD的开发板P/N = DK-DEV-5M570ZN开发板的订购链接：/products/devkits/altera/kit-max-v.html©2011 Cytech Corporation -Public现在就开始，用MAX V 来做设计!Q t 下载Quartus IIV11.0White PapersMAX VHandbookQuartus II Web Edition (free)购买Dev KitsDevicesMAX V 的官网链接：/maxv ，包含了MAX V 的手册下载链接，信号完整性分析模型等©2011 Cytech Corporation -PublicMAX V系列器件内核介绍MAX VMAX V的CORE介绍LE和LAB时钟网络用户FLASH块和内部Oscillator I/O结构©2011 Cytech Corporation -PublicMAX V的硅片架构示意图High-densityHigh I/O Count(最多有4个BANK,已经支持LVDS输出) LogicDigital PLL*O iOscillatorUser Flash（所有型号的器件都包含1个*Contact Altera for availabilityCFM(专用配置FLASH存储器）©2011 Cytech Corporation -Public8Kbits的用户FLASH）* Contact Altera for availabilityLogic Element(LE，逻辑单元)©2011 Cytech Corporation -PublicLE的Normal Mode(通用模式)©2011 Cytech Corporation -PublicLE的Dynamic Arithmetic Mode(动态算术模式)©2011 Cytech Corporation -PublicLE RAM在MAX V中LE可以通过QuartusII列化成RAM(new)：1. FIFO synchronous R/W2. FIFO asynchronous R/W2.FIFO asynchronous R/W3. 1 port SRAM4. 2 port SRAM42t SRAM5. Shift registers©2011 Cytech Corporation -PublicLAB(Logic Array Block，逻辑阵列块)©2011 Cytech Corporation -PublicMAX V的时钟网络MAX V系列器件有4个GCLK管脚用于驱动全局时钟网络全局时钟网络给器件中的所有组件提供时钟驱动全局时钟网络还可以用作全局控制信号©2011 Cytech Corporation -Public用户FLASH块所有MAX V些列器件内部都包含有一个8Kbits的用户FLASH内部包含一个UFM内部包含个OSC，可以单独例化出来使用©2011 Cytech Corporation -PublicMAX V 支持的IO电压类型V CCINT (V)V CCIO (V)Input Signal (V)Output Signal (V)1.21.51.82.53.35.01.21.51.82.53.35.01.81.2bb(new )1.5b b b bb 181.8b b bb b 2.5b b b b b 3.3b bb bbb(2)(1)注：（1）3.3V 管脚在输入为5V 电平时需呀加串行限流电阻和钳位二极管（2）3.3V 管脚在驱动5V LVTTL 电平时，满足5V VTTL 电平的Vth ，可以直接驱动。
eda技术实用教程-veriloghdl答案
eda技术实用教程-veriloghdl答案【篇一：eda技术与vhdl程序开发基础教程课后答案】eda的英文全称是electronic design automation2.eda系统设计自动化eda阶段三个发展阶段3. eda技术的应用可概括为4.目前比较流行的主流厂家的eda软件有、5.常用的设计输入方式有原理图输入、文本输入、状态机输入6.常用的硬件描述语言有7.逻辑综合后生成的网表文件为 edif8.布局布线主要完成9.10.常用的第三方eda工具软件有synplify/synplify pro、leonardo spectrum1.8.2选择1.eda技术发展历程的正确描述为（a）a cad-cae-edab eda-cad-caec eda-cae-cadd cae-cad-eda2.altera的第四代eda集成开发环境为（c）a modelsimb mux+plus iic quartus iid ise3.下列eda工具中，支持状态图输入方式的是（b）a quartus iib isec ispdesignexpertd syplify pro4.下列几种仿真中考虑了物理模型参数的仿真是（a）a 时序仿真b 功能仿真c 行为仿真d 逻辑仿真5.下列描述eda工程设计流程正确的是（c）a输入-综合-布线-下载-仿真b布线-仿真-下载-输入-综合c输入-综合-布线-仿真-下载d输入-仿真-综合-布线-下载6.下列编程语言中不属于硬件描述语言的是（d）a vhdlb verilogc abeld php1.8.3问答1.结合本章学习的知识，简述什么是eda技术？谈谈自己对eda技术的认识？答：eda（electronic design automation）工程是现代电子信息工程领域中一门发展迅速的新技术。
2.简要介绍eda技术的发展历程？答：现代eda技术是20世纪90年代初从计算机辅助设计、辅助制造和辅助测试等工程概念发展而来的。
1第二章 CPLD和FPGA的器件结构
PLD中或阵列的表示
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阵列线连接表示
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二、 电路符号表示
与门、或门的表示
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2.3 低密度PLD的原理与结构（简单PLD）略
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2.4 CPLD的原理与结构(P21)
CPLD器件 的结构
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一、CPLD---MAX7000系列（已过时）
MAX7000 MAX7000S MAX7000E
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I\OE
PIA
图1-9 CPLD结构原理 I/O E I/O控制块
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①LAB逻辑阵列块 一个LAB由16个宏单元构成
宏单元的 乘积项 逻辑
局部连线
共享扩展 项提供的 “与非” 乘积项
宏单元的 乘积项 逻辑
图1-10 LAB 结构原理 14/46
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②PIA可编程连线阵列 不同的LAB通过在可编程连线阵列(PIA)上布线， 以相互连接构成所需的逻辑。
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VCCIO
VCCIO VCCIO
VCCIO
VCCIO VCCIO
VCCIO
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VCCIO
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⑧、在系统可编程（ISP） MAX II 器件运行用户在器件工作的状态下更新配 置Flash 存储器。
（2）结构
①LAB逻辑阵列块 一个LAB由10个LE（逻辑单元）构成，而一个 LE又包含一个LUT（查找表）和一个寄存器等。各 LE由LAB Interconnects相联。
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①、成本优化架构 以最小化裸片面积为目标的架构，打破了典型 CPLD 的成本、容量和功耗限制，是上一代CPLD 密度的四倍，成本却只有一半，业界单个I/O 管脚成 本最低。 ②、低功耗 提供了CPLD 业界最低的动态功耗，只有前一 代MAX 系列CPLD 的十分之一。 ③、高性能 支持内部时钟频率高达300 MHz 。
列举altera公司的cpld和fpga产品。
Altera公司是一家知名的半导体公司，致力于生产和销售可编程逻辑器件（PLD）和现场可编程门阵列（FPGA）等产品。
下面将列举Altera公司旗下的CPLD和FPGA产品，帮助大家更好地了解这家公司的产品线。
一、CPLD产品线1. MAX 7000系列MAX 7000系列是Altera公司推出的一款CPLD产品，具有低功耗、高性能和可编程性强的特点。
该系列产品广泛应用于通信、工业控制、汽车电子等领域，为客户提供了稳定可靠的解决方案。
2. MAX 9000系列MAX 9000系列是Altera公司的另一款CPLD产品，采用了先进的CMOS工艺和可编程逻辑单元，具有高密度、可靠性高的特点。
该系列产品在航空航天、国防安全、医疗设备等领域有着广泛的应用。
二、FPGA产品线1. Stratix系列Stratix系列是Altera公司旗下最为知名的FPGA产品之一，拥有高速、高密度、低功耗等特点，适用于需要大规模数据处理和高性能计算的应用场景。
该系列产品常用于人工智能、云计算、数据中心等领域。
2. Cyclone系列Cyclone系列是Altera公司针对中小规模应用市场推出的FPGA产品，具有低成本、低功耗、高性能等特点。
该系列产品在嵌入式系统、工业自动化、网络通信等领域有着广泛的应用。
3. Arria系列Arria系列是Altera公司旗下的高性能FPGA产品，具有高速、低功耗、灵活性强等特点，适用于需要高性能和灵活性的应用场景。
该系列产品在无线通信、高性能计算、高清视频等领域有着广泛的应用。
通过以上列举，我们可以看到Altera公司在CPLD和FPGA领域拥有丰富的产品线，为不同领域的客户提供了多样化的解决方案。
期待Altera在未来能够持续推出更多高性能、低功耗的PLD和FPGA产品，满足客户不断增长的需求。
Altera公司作为半导体行业的领军企业，一直以来致力于为全球各行业提供高性能、低功耗的可编程逻辑器件（PLD）和现场可编程门阵列（FPGA）产品。