freescale MC9S12P128中文手册
飞思卡尔MC9S12XS128单片机各模块使用方法及寄存器配置
飞思卡尔MC9S12XS128单片机各模块使用方法及寄存器配置手把手教你写S12XS128程序--PWM模块介绍该教程以MC9S12XS128单片机为核心进行讲解，全面阐释该16位单片机资源。
本文为第一讲，开始介绍该MCU的PWM模块。
PWM 调制波有8个输出通道，每一个输出通道都可以独立的进行输出。
每一个输出通道都有一个精确的计数器（计算脉冲的个数），一个周期控制寄存器和两个可供选择的时钟源。
每一个P WM 输出通道都能调制出占空比从0—100% 变化的波形。
PWM 的主要特点有：1、它有8个独立的输出通道，并且通过编程可控制其输出波形的周期。
2、每一个输出通道都有一个精确的计数器。
3、每一个通道的P WM 输出使能都可以由编程来控制。
4、PWM 输出波形的翻转控制可以通过编程来实现。
5、周期和脉宽可以被双缓冲。
当通道关闭或PWM 计数器为0时，改变周期和脉宽才起作用。
6、8 字节或16 字节的通道协议。
7、有4个时钟源可供选择（A、SA、B、SB），他们提供了一个宽范围的时钟频率。
8、通过编程可以实现希望的时钟周期。
9、具有遇到紧急情况关闭程序的功能。
10、每一个通道都可以通过编程实现左对齐输出还是居中对齐输出。
1、PWM启动寄存器PWMEPWME 寄存器每一位如图1所示：复位默认值：0000 0000B图1 PWME 寄存器每一个PWM 的输出通道都有一个使能位P WMEx 。
它相当于一个开关，用来启动和关闭相应通道的PWM 波形输出。
当任意的P WMEx 位置1，则相关的P WM 输出通道就立刻可用。
用法：PWME7=1 --- 通道7 可对外输出波形PWME7=0 --- 通道7 不能对外输出波形注意：在通道使能后所输出的第一个波形可能是不规则的。
当输出通道工作在串联模式时（PWMCTL 寄存器中的CONxx置1），那么）使能相应的16位PWM 输出通道是由PWMEx 的高位控制的，例如：设置PWMCTL_CON01 = 1,通道0、1级联，形成一个16位PWM 通道，由通道 1 的使能位控制PWM 的输出。
飞思卡尔MC9S12XS128单片机重点模块讲解
基于飞思卡尔 MC9S12XS128MCU 的模块讲解及测试
安徽工业大学 自动化系 刘昌元 delay(500); if(LED==0x80) LED=0x01; } } 综合以上的两段代码看在 52 单片机和 128 单片机上编程思路基本上没大的区别，唯一的区 别就是 128 单片机有数据方向寄存器来管理 I/O 口。 � 将部分端口做输入口使用，另外一部分端口做输出口使用时：例如我们将 PORTB 的端 口 B7 用来做输入口，B0-B5 口做输出指示，测试代码如下：
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以端口 A 和端口 B 为例讲解，以上是我截取的技术手册上的，从上来看 A 口和 B 口各 有 8 个口，且 A0-A7;B0-B7 全部作为 GPIO （通用输入输出口 )使用。此处 A 口和 B 口 使用方法是一样的，我姑且就以端口 A 来讲解。 A 口和 B 口作为通用输入输出口使用时我们只需要掌握 4 个寄存器即可。 PORTA (A 口
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这一点和 51 单片机的 I/O 口有区别，在典型的 51 单片中 P0 口内部没有上拉电阻，但作为 I/O 口使用时需要外接排阻。其他 P1-P3 口则可以直接作为双向口使用，51 单片在上电复位 后端口被默认的置 1.在 51 单片中端口的某一位置 0 时端口作为输出口使用，置 1 时作为输 入口使用。例如如果我们想把 P1 作为输出口使用时我们可以在程序开始时写 P1=0x00; 如果 我们想把 P1 口作为输入口使用时我们可以写 P1=0xff; 这一点正好和飞思卡尔的 128 单片机 相反，另外 128 单片有专门的数据方向寄存器 DDRA 或者 DDRB 等来管理各个端口的输入 输出选择，51 单片没有。如果我们想把端口 A 作为输入口使用，我们只需写 DDRA=0x00; 即所有位都置 0，如果我们想把端口 A 作为输出口使用，我们只需要写 DDRA=0xff; 即所有 位都置 1 ，而如 果我们想要 把端口 A 的高四 位做输入口 ，低 4 位做输 出口时我们 就 写 DDRA=0x0f; 当我们需要将该端口的某一位做输出或者输入口使用时只需要将该端口对应的 方向位置 1 或者置 0 即可。例如我们想把 A3 口作输入口， A4 口作输出口使用时我们只需 要写： DDRA_DDRA3=0; DDRA_DDRA4=1; 即可。 � � 对于数据方向寄存器的使用只要记住：置 1——输出 置 0——输入 PORTA 数据寄存器也是由 8 位组成，任何时候都可以对它进行读写操作。
MC9S12XS128中文资料
PWMCNTx：
PWM通道计数寄存器。
每个通道都有一个独立的8位计数器，其计数速率由所选择的时钟源决定。计数器的值可以随时读取而不影响计数器运行，也不影响PWM波形输出。在左对齐模式时，计数器从0计数至周期寄存器的值减1；在中心对齐模式，计数器从0计数至周期寄存器的值，然后再倒计数至0。
CFORC：
定时器比较强制寄存器。复位值为0x00。
FOCx=1将强制该位对应通道产生输出比较成功动作，但CxF中断标志位不置位。任何通道的强制比较成功动作若与普通比较成功动作同时发生，则强制比较成功动作优先发生，且CxF标志位不会置位。
被置位后瞬间将自动清除该位，所以任何时候对该寄存器的读动作都将返回0x00。
OC7M：
输出比较通道7屏蔽寄存器。复位值为0x00。
Setting the OC7Mx (x ranges from 0 to 6) will set the corresponding port to be an output port when the corresponding TIOSx (x ranges from 0 to 6) bit is set to be an output compare and the corresponding OCPDx (x ranges from 0 to 6) bit is set to zero to enable the timer port.A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit.
飞思卡尔16位MCUMC9S12P-系列参考手册
飞思卡尔16位MCUMC9S12P-系列参考手册飞思卡尔16位MCU MC9S12P-系列参考手册详情请下载： 16位MC9S12P－Family.pdfThe MC9S12P family is an optimized, automotive, 16-bit microcontroller product line focused on lowcost,high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS family. The MC9S12P family is targeted at generic automotive applications requiring CAN or LIN/J2602 communication. Typical examples of these applications include body controllers, occupant detection, door modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.The MC9S12P family uses many of the same features found on the MC9S12XS family, including errorcorrection code (ECC) on flash memory, a separate data-flash module for diagnostic or data storage, a fastanalog-to-digital converter (ATD) and a frequency modulated phase locked loop (IPLL) that improves theEMC performance.The MC9S12P family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the lowcost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS family, the MC9S12P family run 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12P family is available in 80-pin QFP, 64-pin LQFP, and 48-pin QFN package options and aims to maximize pin compatibility with the MC9S12XS family. Inaddition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.。
MC9S12XS128单片机简介(综合)
MC9S12XS128 单片机简介1、HCS12X 系列单片机简介Freescale公司的16位单片机主要分为HC12、HCS12 HCS12X三个系列。
HC12核心是16 位高速CPU12 核，总线速度8MHZ；HCS12 系列单片机以速度更快的CPU12 内核为核心，简称S12 系列，典型的S12 总线速度可以达到25MHZ。
HCS12X 系列单片机是Freescale 公司于2005 年推出的HCS12 系列增强型产品，基于S12 CPU 内核，可以达到25MHz 的HCS12 的2-5 倍性能。
总线频率最高可达40 MHz。
S12X 系列单片机目前又有几个子系列：MC9S12XA系列、MC9S12XB系列、MC9S12XD系列、MC9S12XE系列、MC9S12XF系列、MC9S12XH 系列和MC9S12XS 系列。
MC9S12XS128 就是S12X 系列中的一个成员。
2、MC9S12XS128 性能概述MC9S12XS128 是16 位单片机，由16 位中央处理单元( CPU12X)、128KB 程序Flash(P-lash)8KB RAM、8KB数据Flash(D-lash)组成片内存储器。
主要功能模块包括：内部存储器内部PLL 锁相环模块 2 个异步串口通讯SCI 1 个串行外设接口SPIMSCAN 模块1 个8 通道输入/输出比较定时器模块TIM 周期中断定时器模块PIT16 通道A/D 转换模块ADC1 个8 通道脉冲宽度调制模块PWM 输入/输出数字I/O 口3、输入/ 输出数字I/O 口MC9S12XS128 有3 种封装，分别为64 引脚、80 引脚、112 引脚封装。
其全名分别为MC9S12XS128MAE、MC9S12XS128MAA、MC9S12XS128MAL。
MC9S12XS 系列具有丰富的输入/ 输出端口资源，同时集成了多种功能模块，端口包括PORTA、PORTB、PORTE、PORTK、PORTT PORTS PORTM PORTR PORTH PORTJ和PORTAD 共11 个端口。
Freescale MC9S12G128微控制器的TWR-S12G128演示板用户指南说明书
D O C -0508-010, RE V AWeb Site: TWR-S12G128Demonstration Board for Freescale MC9S12G128MicrocontrollerUSER GUIDECONTENTSCAUTIONARY NOTES (4)TERMINOLOGY (4)FEATURES (5)MEMORY MAP (6)SOFTWARE DEVELOPMENT (7)DEVELOPMENT SUPPORT (7)OSBDM BOOTLOADER (8)BDM_PORT HEADER (8)POWER (8)POWER SELECT (9)RESET SWITCH (9)LOW VOLTAGE RESET (9)TIMING (10)COMMUNICATIONS (10)RS-232 (10)COM CONNECTCOR (11)COM_EN (11)LIN PORT (11)LIN ENABLE (12)LIN COM INPUT (12)LIN_PWR OPTION (12)MSTR OPTION (12)LIN-J1 CONNECTOR (13)CAN PORT (13)CAN TERMINATION ENABLE (14)STANDBY MODE (14)USER PERIPHERALS (14)POTENTIOMETER (14)USER LED’S (15)PUSHBUTTON SWITCHES (15)EDGE CONNECTOR PINOUT (16)FIGURESFigure 1: Memory Map (6)Figure 2: BDM_PORT Header (8)Figure 3: PWR_SEL Option Header (9)Figure 4: Serial Connections (10)Figure 5: COM1 Connector (11)Figure 6: COM_EN Option Header (11)Figure 7: LIN Block Diagram (11)Figure 8: JP6 Option Header (13)Figure 9: LIN Connector (13)Figure 10: CAN_PORT (13)Figure 11: CAN Termination Enable (14)Figure 12: JP1 Option Header (15)Figure 13: Primary Edge Connector (16)Figure 14: Secondary Edge Connector (18)REVISIONDate Rev CommentsCAUTIONARY NOTES1) Electrostatic Discharge (ESD) prevention measures should be used when handling thisproduct. ESD damage is not a warranty repair item.2) Axiom Manufacturing does not assume any liability arising out of the application or use ofany product or circuit described herein; neither does it convey any license under patent rights or the rights of others.3) EMC Information on the TWR-S12G128 board:a) This product as shipped from the factory with associated power supplies and cables,has been verified to meet with requirements of CE and the FCC as a CLASS A product.b) This product is designed and intended for use as a development platform for hardwareor software in an educational or professional laboratory.c) In a domestic environment, this product may cause radio interference in which case theuser may be required to take adequate prevention measures.d) Attaching additional wiring to this product or modifying the products operation from thefactory default as shipped may effect its performance and cause interference with nearby electronic equipment. If such interference is detected, suitable mitigating measures should be taken.TERMINOLOGYThis development module utilizes option select jumpers to configure default board operation. Terminology for application of the option jumpers is as follows:Jumper – a plastic shunt that connects 2 terminals electricallyJumper on, in, or installed = jumper is a plastic shunt that fits across 2 pins and the shunt is installed so that the 2 pins are connected with the shunt.Jumper off, out, or idle = jumper or shunt is installed so that only 1 pin holds the shunt, no 2 pins are connected, or jumper is removed. It is recommended that the jumpers be placed idle by installing on 1 pin so they will not be lost.Cut-Trace – a circuit trace connection between component pads. The circuit trace may be cut using a knife to break the default connection. To reconnect the circuit, simply install a suitably sized 0-ohm resistor or attach a wire across the pads.Signal names followed by an asterisk (*) denote active-low signals.FEATURESThe TWR-S12G128 is a demonstration board for the MC9S12G128 microcontroller; an automotive, 16-bit microcontroller focused on low-cost, high-performance in a low pin-count device. The MC9S12G128 provides16-bit wide accesses, without wait states, for all peripherals and memories. The MC9S12G128 targets automotive applications requiring CAN or LIN/J2602 communications. Examples include body controllers, occupant detection, etc… The board is designed to interface to the Freescale Tower System, a modular development platform which aids in rapid prototyping and tool-reuse. An integrated Open-Source BDM, software tools, and examples provided with the development board make application development and debug quick and easy. All MCU signals are available on one or both edge connectors.∙MC9S12G128, 100 LQFP∙128K Bytes Flash∙4096 Bytes EEPROM∙8192 Bytes RAM∙25MHz Bus Frequency∙Internal Oscillator∙SCI, SPI, MSCAN∙Integrated Open Source BDM (OSBDM)∙BDM_PORT header for external BDM cable support∙ 1 ea. High-Speed CAN Physical Layer Transceiver∙ 1 ea, Enhanced LIN Physical Layer Transceiver∙RS-232 Serial Data Physical Layer Transceiver∙On-board +5V regulator∙Power input from OSBDM, Tower System, or inputvias at E1/E2∙Power Input Selection Jumpers∙Power input from USB-BDM∙Power input from on-board regulator∙Power input from Tower System edge connector∙User Peripherals∙ 4 User Push Button Switches∙ 4 User LED Indicators∙5K ohm POT w /LP Filter∙User Option Jumpers to disconnect Peripherals∙Connectors∙BDM_PORT Connector for External BDM Cable∙USB mini-AB Connector∙2x5, 0.1” ctr, RS-232 Header∙1x4, 4.2mm, Molex CAN Cable Connector∙2x2, 4.2mm, Molex LIN Cable ConnectorSpecifications:Board Size 3.55” x 3.20” overallPower Input: +5V from USB connector or from Tower SystemNOTE: LIN functionality requires +12V on LIN +V input or +12V at E1/E2 input.MEMORY MAPFigure 1 below shows the target device memory map. Refer to the MC9S12G128 Reference Manual (RM) for further information.Figure 1: Memory Map0x000E–0x000F Reserved 20x0010–0x0017 MMC (memory map control)80x0018–0x0019 Reserved20x001A–0x001B Device ID register20x001C–0x001F PIM (port integration module)40x0020–0x002F DBG (debug module)160x0030–0x0033 Reserved40x0034–0x003F CPMU (clock and power management)120x0040–0x006F TIM0 (timer module)480x0070–0x009F ATD (analog-to-digital converter, 10 bit, 8-channel)48SOFTWARE DEVELOPMENTSoftware development requires the use of a compiler or an assembler supporting the HCS12(X) instruction set and a host PC running a debug interface. CodeWarrior Development Studio is supplied with this board for application development and debug. Refer to the supporting CodeWarrior documentation for details on use and capabilities.DEVELOPMENT SUPPORTApplication development and debug for the target TWR-S12 board is supported through the Open-Source Background Debug Mode (OSBDM) interface or an external BDM interface connector. The OSBDM is fully supported in CodeWarrior and provides direct, non-intrusive access to the target device internals. While in BDM mode, no internal resources are used. Code stepping and break-points are fully supported.Connection between a host PC and the target device is provided via a mini-B, USB connector. The OSBDM is capable of providing power to the target board eliminating the need for external power. Please note that power supplied by the OSBDM is limited by the USB specification. When powered through the OSBDM, total current draw, including the OSBDM, TWR-S12 board, and Tower System must remain less that 500mA. Otherwise, the USB bus will cause the host PC to disconnect the board. Damage to the host PC, target board, or Tower System may result if this current limit is violated.OSBDM BootloaderThe OSBDM is pre-programmed with a bootloader application to allow field updates. The USB bootloader communicates with a GUI application running on a host PC. The GUI application allows the user to update OSBDM firmware easily and quickly. Option jumper JP401 enables the bootloader at startup. This option header is not populated in default configuration. Refer to Freescale Application Note AN3561 for details on using the GUI application and bootloader. The application note may be found at or at /support. BDM_PORT HeaderA compatible HCS12 BDM cable can also be attached to the 6-pin BDM interface header at J3. This header allows the use of external programming/debug cables. Refer to the external programming/debug cable documentation for details on use. The figure below shows the pin-out for the DEBUG header.Figure 2: BDM_PORT HeaderJ4001 2 GND See the associated RM for complete DEBUGdocumentation3 4 RESET*5 6 VDDNOTE: This header is not installed in default configuration.POWERThe TWR-S12 board may be powered from the OSBDM, from the Tower System, from the LIN +V input, or 2 input vias at E1 & E2. The LIN +V input accepts +12V from the LIN bus and uses an on-board regulator to create the board operating voltage. Input vias at E1 & E2 allowconnecting external power to the board if desired. An on-board regulator is used to create the board operating voltage from this input.Use of the on-board regulator requires input voltage between +7.V and +27V. However, input voltage should be kept as low as possible to reduce device self-heating.Power SelectOption headers PWR_SEL selects the input power source for the target board. When powered from the Tower System, the OSBDM voltage output is disabled.Figure 3: PWR_SEL Option HeaderJP5 1●●2Select TWR voltage inputPWR_SEL ●●Select OSBDM voltage input (default)●●Select on-board regulator inputRESET SWITCHThe RESET switch applies an asynchronous RESET input to the MCU. The RESET switch is connected directly to the RESET* input on the MCU. Pressing the RESET switch applies a low voltage level to the RESET* input. A pull-up bias resistor allows normal MCU operation. LOW VOLTAGE RESETThe MC9S12G128 applies a Power-On Reset (POR) circuit and an internal Low Voltage Reset (LVR) circuit to ensure proper device operation. The POR circuit holds the MCU in reset until applied voltage reaches an appropriate level. The LVR forces the device into reset if input voltage falls too low, protecting against brown-out conditions. A user configurable Low-Voltage Detect (LVD) with interrupt output is also available. Consult the MC9S12G128 reference manual for details of POR, LVR, and LVD operation.TIMINGThe TWR-S12G128 internal timing source is active from RESET by default. An external 8MHz crystal oscillator, configured for low-power operation, is also installed. Refer to the target device RM for details on selecting and configuring the desired timing source.COMMUNICATIONSCommunications options for the TWR-S12G128 include serial RS-232, LIN, and CAN. Serial RS-232 communications is supported through a RS-232 physical layer device (PHY) and a 2x5 pin header. A high-speed, enhanced, LIN PHY provides LIN bus communications through a 2x2 Molex connector (pn 39-29-1048). A high-speed CAN PHY provides CAN bus communications through a 1 x 4 Molex connector (pn 39-30-3045).Connecting LIN cables require Molex housing, pn 39-01-2040 and pins, pn 39-00-0217. Connecting CAN cables require Molex housing, pn 39-01-4040, and pins, pn 39-00-0217.The COM_SEL option header connects the MCU SCI signal to either the LIN PHY or the RS-232 PHY. See Figure 6 below for jumper position options. See Figure 4 below for jumper position options.RS-232The TWR-S12G128 applies the MAX3387E, RS-232 transceiver to support serial communications. A standard 2x5 “Berg” pin-header on 0.1” centers and an IDC to DB9 cable supports connecting standard serial cables to the target board. Figure 4 below shows the SCI signal connections.Figure 4: Serial ConnectionsNOTE: For normal RS-232 operation, FORCEOFF* should be actively driven to the high level.Alternately, open CT5 to allow FORCEOFF* to float high.COM ConnectcorA 2x5, 0.1”, standard “Berg” pin-header provides external connections for the SCI port. Figure5 below shows the COM1 pin-out.Figure 5: COM1 Connector2, 71, 7TXD CTSRXD RTS1, 2 TP2GND NCCOM_ENThe COM_EN option header connects the MCU SCI port to either the SCI PHY or the LIN PHY. Figure 6 below shows the option jumper configuration for the COM_EN option header. Figure 6: COM_EN Option HeaderConnects target MCU SCI port to LIN PHY to enable LIN buscommunicationsConnects target MCU SCI port to RS-232 PHY to enable serialcommunicationsLIN PortThe TWR-S12G128 applies the MC33661 LIN bus physical layer device (transceiver) to support LIN communications. The PHY may be configured as a Master or Slave node on the LIN bus. LIN connectors J9 & J10 are configured in parallel to support pass-thru signaling. Figure 7 shows the LIN block diagram.Figure 7: LIN Block DiagramThe LIN interface provides optional features of slew rate control, network supply, and wake up option. Refer to the MC33661 Reference Manual for detail on PHY functionality. The following sections detail functionality for LIN option jumpers.LIN EnableThe LIN PHY is enabled by default. Disable the PHY by connecting the test point, TP3, to GND.LIN COM InputLIN inputs RX and TX are selectable using the COM_EN option header. Refer to Figure 6 above for details on configuring this header.LIN_PWR OptionThe LIN_PWR option jumper connects pin 1 of both LIN connectors to the +V input. In Master mode, this option may be used to power LIN slave devices. This option requires +12V be applied at E1/E2 inputs. In Slave mode, this option allows slave device to draw power from the LIN network. For Slave mode configuration, external power should not be applied to the target board. LIN_PWR is enabled by installing a shunt from JP3-1 to JP3-2. Refer to Figure 8 below.MSTR OptionThe MSTR option jumper allows the LIN transceiver to be configured for Master mode functionality. Master mode may also be set using the INH pin on the PHY. Refer to the MC33661 device datasheet for details on use and configuration. Refer to Figure 8 below.Figure 8: JP6 Option HeaderJP3Connects LIN bus to +V input (default)LIN_PWR Enables LIN Master mode functionality (default)NOTE: LIN PHY may also be configured as a Master Node using the INH pin. Refer to the LINPHY data sheet for details.LIN-J1 ConnectorThe TWR-S12G128 supports two, 2 x 2 Molex connectors to interface to the LIN bus. Figure 9 below details the pin-out of the LIN bus connector. Figure 9: LIN Connector4 3 +V2 1 GNDFront View – Looking into ConnectorNOTE: LIN Port Connector – Molex 39-29-1048 Mates with; Housing – Molex 39-01-2040, Pin – Molex 39-00-0036CAN PortOne, TJA1040T, High-Speed CAN physical-layer transceiver (PHY) is applied to support CANbus communications. A 4-pos, 4.22mm MOLEX connector interfaces to external CAN cabling. Differential input CAN signals, are terminated with 120 ohms. Option headers, JP13 and JP15 allow the user to optionally disconnect signal termination. Avalanche diodes protect the CAN PHY from voltage surges on the input differential signal lines. Figure 10 below shows the CAN connector pin-out. Figure 10: CAN_PORTN CG N DC A N LC A N HLooking into ConnectorNOTE: CAN Port Connector – Molex 39-30-3045Mates with; Housing – Molex 39-01-4040, Pin – Molex 39-00-0217CAN Termination EnableCAN bus termination of 120 ohm with virtual ground is applied to the differential CAN signals on both channels. The SPLIT output from each PHY is connected to the virtual ground providing common-mode stabilization. The differential CAN bus signal termination may be removed using option header JP13 or JP15. To prevent signal corruption, both option jumpers must be installed or both option jumpers must be removed. The CAN bus should not be operated with only 1 signal termination applied. Figure 11 below details the option header shunt positions.Figure 11: CAN Termination EnableEnables CANL termination1 2 Enables CANH terminationStandby ModeThe CAN PHY is configured for normal mode by default. To enable standby (STB) mode, apply a high logic level at test point TP1. Refer to the TJA1040T Reference Manual for use and capabilities of the Standby Mode.USER PERIPHERALSUser I/O includes 1 potentiometer, 4 push button switches, and 4 green LEDs for user I/O. The USER (JP14) option header enables or disables each User I/O function individually. The sections below provide details on user I/O. Figure 12 below shows the USER jumper settings.PotentiometerThe TWR-S12G128 target board applies a single-turn, 5K, ohm potentiometer (POT) to simulate analog input. The POT is connected to an ATD input on the target MCU and is decoupled to minimize noise transients during adjustment. Figure 12 below shows the USER jumper settings.User LED’sThe TWR-S12G128 target board applies 4, green, LEDs for output indication. Each LED is configured for active-low operation. A series, current-limit resistor prevents excessive diode current. Each LED is connected to a timer channel on the target MCU. Figure 12 below shows the USER jumper settings.Pushbutton SwitchesThe TWR-S12G128 provides 4 push-button switches for user input. Each push-button switch is configured for active-low operation and is connected to a key-wakeup input on the target MCU. No bias is applied to these push-button inputs and use of target MCU internal pull-ups is required for proper operation. Figure 12 below shows the USER jumper settings.Figure 12: JP1 Option HeaderSignal ON OFFPAD4/KWAD4/AN4 Enabled DisabledPAD5/KWAD5/AN5 Enabled DisabledPAD6/KWAD6/AN6 Enabled DisabledPAD7/KWAD7/AN7 Enabled DisabledPAD0/KWAD0/AN0 Enabled DisabledPT4/IOC4 Enabled DisabledPT5/IOC5 Enabled DisabledPT6/IOC6 Enabled DisabledPT7/IOC7 Enabled Disabled NOTE: User peripheral input/output is enabled by default.EDGE CONNECTOR PINOUTThe TWR-S12 board connects to the Freescale Tower System using the 2 PCIe Edge Connectors. Following the PCIe specification, the Bx signals are located on the top of the board and the Ax signals are located on bottom. Pin B1 for the primary and secondary connectors are at opposite ends of the board. The figures below show the pin-out of each edge connector.Figure 13: Primary Edge Connector5.0V Power Pri_B01 Pri_A01 5.0V PowerGround Pri_B02 Pri_A02 GroundPri_B03 Pri_A03Elevator Power Sense Pri_B04 Pri_A04Ground Pri_B05 Pri_A05 GroundGround Pri_B06 Pri_A06 GroundPS6/SCK0 Pri_B07 Pri_A07Pri_B08 Pri_A08PS7/API_EXTCLK/SS0 Pri_B09 Pri_A09 PD3Ground Pri_B49 Pri_A49 GroundPri_B50 Pri_A50 PA2Pri_B51 Pri_A51 PA3Pri_B52 Pri_A52 PA4Pri_B53 Pri_A53 PA5Pri_B54 Pri_A54 PA6Pri_B55 Pri_A55 PA7Pri_B56 Pri_A56Pri_B57 Pri_A57Figure 14: Secondary Edge ConnectorMISO1/KWJ0/PJ0 Sec_B11 Sec_A11Sec_B11ASec_B12 Sec_A12Sec_B13 Sec_A13Sec_B14 Sec_A14Sec_B15 Sec_A15PC1 Sec_B16 Sec_A16PC2 Sec_B17 Sec_A17 PC3PC4 Sec_B18 Sec_A18 PC5。
MC9S12系列用户手册-第二部分
NVM 定时：
17
所有的 NVM 程序和擦除操作的时间基准由振荡器决定。要求最小振荡频率 f NVMOSC 能够运行程序和擦除 操作。NVM 模式无法监测频率，所以无法防止程序和擦除操作在高于或低于指定最小频率上运行。尝试 在低频率下的 NVM 模式下运行程序和擦除操作的话，程序的完整性和擦除的转换无法保障。 FLASH 和 EEPROM 的编程和擦除操作， 是通过使用来自振荡器的时钟来计时， 该振荡器分别使用了寄存器 FCLKDIV 和 ECLKDIV。时钟的频率必须被设置到 f NVMOP 指定的范围。
i 2
I
PIO 是所有连接到 VDDX 和 VDDR 的 I/O 口输出电流的总和。
对于 R DSON 有效：
10
R DSON
VOL , 输出低电平驱动 I OL
VOH , 输出高电平驱动 I OH
2．Enabled
PINT I DDRVDDR I DDAVDDA
11
3．PC Board according to EIA/JEDEC Standard 51-7 FAQ：注意的 2 和 3 什么意思？
I/O 特性： 下表描述了所有 5V I/O 管脚特性。有些参数并不一定适用，比如说，不是所有的管脚都有上拉或者下 拉电阻。
电源电流： 所有测量没有输出负载，除非特别说明，电流以单片模式测量。内部电压调节器 enabled，在 Colpitts 模式下，25MHz 总线频率使用 4MHz 振荡器。产品的测试是在 EXTAL 端输入一个方波信号。
I DDR 是表 A-7 所示电流，不是全部的电流流进 VDDR，还有额外的流如外部负载的高电平电流。
PIO RDSON I IOi
i
飞思卡尔MC9S12XS128(定时器)ECT寄存器详解
1、定时器IC/OC功能选择寄存器TIOSIOS[7..0]IC/OC功能选择通道0 相应通道选择为输入捕捉(IC)1 相应通道选择为输出比较(OC)2、定时器比较强制寄存器 CFORCFOC[7..0]设置该寄存器某个FOCn位为1将导致在相应通道上立即产生一个输出比较动作，在初始化输出通道时候非常有用。
【说明】这个状态和正常状态下输出比较发生后，标志位未被置位后的情况相同。
3、输出比较7屏蔽寄存器 OC7MOC7M[7..0]OC7(即通道7的输出比较)具有特殊地位，它匹配时可以直接改变PT7个输出引脚的状态，并覆盖各个引脚原来的匹配动作结果，寄存器OC7M决定哪些通道将处于OC7的管理之下。
OC7M中的各位与PORTT口寄存器的各位一一对应。
当通过TIOS将某个通道设定为输出比较时，将OC7M中的相应位置1，对应的引脚就是输出状态，与DDR中的对应位的状态无关，但OC7Mn并不改变DDR相应位的状态。
【说明】OC7M具有更高的优先级，它优于通过TCTL1和TCTL2寄存器中的OMn和OLn设定的引脚动作，若OC7M中某个位置1，就会阻止相应引脚上由OM和OL设定的动作。
4、输出比较7数据寄存器 OC7DOC7D[7..0]OC7M对于其他OC输出引脚的管理限于将某个二进制值送到对应引脚，这个值保存在寄存器OC7D中的对应位中。
当OC7匹配成功后，若某个OC7Mn=1，则内部逻辑将OC7Dn送到对应引脚。
OC7D中的各位与PORTT口寄存器的各位一一对应。
当通道7比较成功时，如果OC7M中的某个位为1，OC7D中的对应位将被输出到PORTT的对应引脚。
【总结】通道7的输出比较(OC7)具有特殊的位置，在OC7Mn和OC7Dn两个寄存器设置以后，OC7成功输出后将会引起一系列的动作。
比如：OC7M0=1，则通道0处在OC7的管理下，在OC7成功后，系统会将OC7D0的逻辑数据(仅限0或者1)反应在PT0端口上。
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1Chapter1 Device Overview MC9S12P-Family 1.1介绍The MC9S12P 系列单片机是经过优化后有着低成本、高性能、低引脚数的汽车专业级单片机产品，该产品倾向于弥补高端16位单片及产品如MC9S12XS和低端8位单片机产品之间的空缺。
MC9S12P 主要针对于要求使用CAN 或者LIN/J2602通讯接口的汽车应用产品，典型的应用案例包括车身控制器、乘坐人员检测、车门控制、座椅控制、遥控车门开关信号接收器、智能执行器、车灯模块、智能接线器。
The MC9S12P 系列单片机使用了很多MC9S12XS系列单片机相同的功能，包括片内闪存错误纠正代码（ECC）、一个专为数据诊断或者数据存储的单独的数据闪存模块、高速AD转换器和高频调制锁相环（IPLL）有效改善电磁兼容性能。
MC9S12P系列单片机提供的所有16为单片机优点和微处理器效率，同时保持飞思卡尔用户熟悉的8位及16位单片机，低成本，功耗，EMC和高效的代码80针QFP、64针LQFP、40针QFN封装产品，最大限度的与MC9S12尺寸的优点，如同MC9S12XS一样可以无需等待外围设备和内存的状态既可以运行16为带款的寻址，MC9S12P系列单片机主要有XS引脚兼容. I/O口在各种模式下都可以使用，同时具有中断功能的I/O口还可以在停止或等待模式下唤醒。
1.2 芯片特性表一:提供了MC9S12P家庭成员特征摘要,1.P或D寄存器擦除或者编程需要最低总线频率为1MHZ1.2.2 芯片功能• S12 CPU 内核• 高达128 KB具有ECC功能的片上闪存• 4 Kbyte带ECC功能的数据闪存• 高达6 Kb片上静态存储器(SRAM)• 具有内部滤波器的锁相环倍频器(IPLL)• 4–16 MHz 皮尔斯振荡器• 1 MHz内部RC振荡器• 定时器(TIM) 具有16位输入捕捉、输出比较、计数器脉冲累加器功能• 具有8位6通道的脉冲调制模块(PWM)• 10通道12位分辨率的逐次逼近AD转换器• 1个串行通信外部接口(SPI)• 1个支持局域网通讯串行通信(SCI) 模块•一个多可扩展控制器区域网络(MSCAN) 模块(支持CAN 协议2.0A/B)•片上电压调节器(VREG) 可对内部供电及内部电压整流• 自主周期中断(API)1.3 模块特征1.3.1 CPUS12 CPU 是一个高速的16位处理单元:•全16-bit数据通道提供有效的数学运算和高速的数学执行• 包含很多单字节指令，可以有效的利用ROM空间• 宽域变址寻址功能：—采用堆栈指针作为所有变址操作的变址寄存器—除了在自增或自减模式下都可以利用程序计数器作为变址寄存器—使用A\B\D累加器做累加器偏移—自动变址，前递增(++a)、前递减(--a)、后递减（a--）、后递增（a++）(by –8 to +8)1.3.2 带ECC功能的片内闪存• 高达128 Kb程序闪存空间— 32 位数据加7 位ECC (纠错码) 允许单字节纠错和双字节纠错— 512字节擦出扇区空间—自动编程和擦除算法—用户设置读写页面边界—具有可以防止偶然编程或者擦除的保护结构• 4 Kb 数据闪存空间— 16 位数据加6位纠错码允许单字节和双字节纠错功能— 256 字节的擦出扇区空间—自动编程和擦除算法—用户设置读写页面边界1.3.3 片内静态存储器3高达6kb通用RAM1.3.4 外部晶振(XOSC)• 闭环控制皮尔斯晶振频率为4MHZ---16MHZ—振幅增益控制输出电流—低谐波失真信号Signal with low harmonic distortion—低功耗—良好的噪声免疫—无需外部限流电阻—跨导尺寸优化提供良好的振荡器启动保证1.3.5 内部RC晶振(IRC)• 可调的内部参考时钟—频率: 1 MHz—在–40°C to +125°C环境温度范围内调节精度达: 1.5%1.3.6 内部锁相环倍频器(IPLL)—无需外部元件—参考分频器和倍频器提供大变化量的时钟频率—自动带宽控制低频率抖动操作—自动锁定频率—可配置的选项，扩频减少电磁干扰EMC (频率调制frequency modulation) —参考时钟源:–外部4–16 MHz 共振器/晶振(XOSC)–内部RC晶振1 MHz (IRC)1.3.7 系统支撑• 上电复位(POR)• 系统复位发生器• 非法寻址复位•低电压检测中断或复位• 实时中断(RTI)• 计算机正常工作复位(COP) 开门狗—可通过相应窗口设置COP用以采用错误侦测复位通过位操作对闪存进行初始化复位•时钟监控器监控晶振功能正常工作1.3.8 定时器(TIM)• 8通道16位定时器可进行输入捕捉和输出比较• 16-bit带有7位精度预分频器的自由运行计数器•一通道16-bit 脉冲累加器1.3.9 脉冲带宽调制器(PWM)• 6通道8位or 3 通道16-bit脉宽调制器—每个通道都可以对周期和占空比进行编程—中心对齐或者左对齐输出—宽频率范围内可编程逻辑时钟1.3.10 局域网控制器(MSCAN)•速率达1Mbit/s, 满足CAN 2.0 A, B 协议—标准和扩展数据帧— 0–8 字节长度—可编程比特率达1 Mbps•5个FIFO(先进先出)的接收缓冲器•三个内部优先发送缓冲器• 灵活的标识符可编程选通滤波器s:— 2 x 32-bit— 4 x 16-bit— 8 x 8-bit•集成了低通滤波器的唤醒操作• 闭环反馈自检测• CAN 总线监听•总线关闭可通过软件干预或者自动恢复• 16-bit 接收发送信息时钟戳1.3.11 串行通信接口(SCI)•可选择全双工或单工模式•标准的不归零格式•通过可编程脉宽调制选用IrDA 1.4 反转归零格式• 13位波特率可选•可编程字符长度•可编程改变其接收和发送极性for transmitter and receiver•边沿触发接收唤醒•支持LIN总线的间隔检测和传输冲突检测1.3.12 Serial Peripheral Interface Module (SPI) •可配置8- or 16-bit 数据大小•全双工或单线双向•全双工接收和发送• Master or slave 模式•最高位优先or 最低位优先可换• 并口时钟频率相位和极性选择1.3.13 AD转换(ATD)• 10通道12位AD转换器— 3微妙转换时间— 8-/10-/12-位解决方案5—数据结果左对齐或右对齐—停止模式下使用内部晶振作为转换器晶振—低功耗模式下模拟信号比较唤醒—连续转换模式e—多通道扫描•引脚可作为IO口1.3.14 片内电压调节器(VREG)•具有带隙标准的线性电压稳压器• 具有低电压中断功能的低压检测器•上电复位(POR) 电路•低电压复位功能(LVR)•高温传感器1.3.15 背景调试(BDM)• 非插入内存访问指令• 支持在线对片内非易始性存储单元编程1.3.16 调试器(DBG)•64个入口跟踪缓冲器• 三个比较器(A, B and C)—比较器A比较全16位地址总线额16位数据总线—精确寻址和寻址范围比较•两种匹配比较类型—标记位—程序强行置位该类型是在一数学公式出现后一个指令边界可用•四个跟踪模式•四个阶段状态序列发生器stage state sequencer1.4 内部结构框图71.5 引脚图1.6 存储器映像表Table 1-2. Device Register Memory Map注意在表1-2中保留的寄存器空间不分配给任何模块，该寄存器的保留空间是留给以后使用的，对这些保留空间写操作没有任何效果，读该空间返回值都为零。
表1-2显示S12P的CPU和BDM本地地址转换到全局内存映射。
还表明内部资源在内存映射中的位置。
表1-3表示闪光映射D –Flash（数据寄存器）和P –Flash（程序寄存器）闪存的映射。
全部256K全局内存空间可以使用PPAGE页面寄存器在本地64k空间中的0x8000 - 0xBFFF的p-flash窗口看到。
(1)、(2)地址针对MC9S12P64是因为4K的RAM空间S12中的PPAGE页面寄存器属于MMC模块，用于选择分页地址的页91113Figure 1-2. MC9S12P-Family Global Memory Map2.48针封装 VRH and VDDA 共用一个引脚3. 64和48针封装VRL and VSSA 共用一个引脚1.7.3 Detailed Signal Descriptions1.7.3.1 EXTAL, XTAL — 振荡器引脚EXTAL 、XTAL 引脚是晶振驱动和外部时钟引脚，上电复位后所有装置的时钟都来源于内部参考时钟，XTAL 是振荡器输出引脚1.7.3.2 RESET — 外部复位引脚RESET 引脚是一个低电平有效复位双向信号引脚，其可作为输入端使MCU 复位到初始化状态，而当MCU 内部产生复位使其可作为输出引脚。
RESET 脚有内部上拉电路.1.7.3.3 TEST — 测试引脚该引脚是保留给工厂作为测试引脚用，注意TEST 必须与V SSX 引脚相连。
1.7.3.4 BKGD / MODC — 背景调试模式引脚The BKGD/MODC 该引脚作为背景调试通讯的伪漏极开路引脚，在复位时该引脚为作为工作模式选择引脚，该引脚的状态可以在复位上升沿时锁存到MODC 位，其有内部上拉电路。
1.7.3.5 PAD[9:0] / AN[9:0] — Port AD Input Pins of ATDPAD[9:0] 为通用IO 引脚和10通道的AD 转换模拟输入。
1.7.3.6 PA[7:0] — Port A I/O PinsPA[7:0] 通用IO 脚。
1.7.3.7 PB[7:0] — Port B I/O PinsPB[7:0] 为通用IO 口。
1.7.3.8 PE7 — Port E I/O Pin 7 / ECLKX2PE7 是通用IO 口.在复位时内部上拉使能，还可以作为ECKX2的输出 。
1.7.3.9 PE[6:5] — Port E I/O Pin 6-5PE[6:5] 通用IO 口。
1.7.3.10 PE4 / ECLK — Port E I/O Pin 4PE4 为通用IO 引脚. 还可以设置为驱动内部总线的时钟频率引脚ECLKI ， ECLK 可用作参考计时。
ECLK 输出有一个可编程的预分频器。
1.7.3.11 PE[3:2] — Port E I/O Pin 3PE[3:2] 通用IO 脚。
1.7.3.12 PE1 / IRQ ————— Port E Input Pin 1PE1 是通用输入引脚同时还是可屏蔽的中断请求输入引脚，可以实现异步中断请求，该引脚可以使MCU 从停止和等待模式下唤醒。